Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@cs.anu.edu.au) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
17 | #include <linux/errno.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/stddef.h> | |
22 | #include <linux/unistd.h> | |
23 | #include <linux/ptrace.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/user.h> | |
26 | #include <linux/a.out.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/config.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/prctl.h> | |
32 | ||
33 | #include <asm/pgtable.h> | |
34 | #include <asm/uaccess.h> | |
35 | #include <asm/system.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/reg.h> | |
38 | #include <asm/xmon.h> | |
f7f6f4fe | 39 | #include <asm/pmc.h> |
1da177e4 LT |
40 | |
41 | #ifdef CONFIG_XMON | |
fd582ec8 PM |
42 | extern int xmon_bpt(struct pt_regs *regs); |
43 | extern int xmon_sstep(struct pt_regs *regs); | |
44 | extern int xmon_iabr_match(struct pt_regs *regs); | |
45 | extern int xmon_dabr_match(struct pt_regs *regs); | |
46 | ||
7b007de8 | 47 | int (*debugger)(struct pt_regs *regs) = xmon; |
1da177e4 LT |
48 | int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt; |
49 | int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep; | |
50 | int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match; | |
51 | int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match; | |
52 | void (*debugger_fault_handler)(struct pt_regs *regs); | |
53 | #else | |
54 | #ifdef CONFIG_KGDB | |
7b007de8 | 55 | int (*debugger)(struct pt_regs *regs); |
1da177e4 LT |
56 | int (*debugger_bpt)(struct pt_regs *regs); |
57 | int (*debugger_sstep)(struct pt_regs *regs); | |
58 | int (*debugger_iabr_match)(struct pt_regs *regs); | |
59 | int (*debugger_dabr_match)(struct pt_regs *regs); | |
60 | void (*debugger_fault_handler)(struct pt_regs *regs); | |
61 | #else | |
62 | #define debugger(regs) do { } while (0) | |
63 | #define debugger_bpt(regs) 0 | |
64 | #define debugger_sstep(regs) 0 | |
65 | #define debugger_iabr_match(regs) 0 | |
66 | #define debugger_dabr_match(regs) 0 | |
67 | #define debugger_fault_handler ((void (*)(struct pt_regs *))0) | |
68 | #endif | |
69 | #endif | |
70 | ||
71 | /* | |
72 | * Trap & Exception support | |
73 | */ | |
74 | ||
75 | DEFINE_SPINLOCK(die_lock); | |
76 | ||
dc1c1ca3 | 77 | int die(const char * str, struct pt_regs * fp, long err) |
1da177e4 LT |
78 | { |
79 | static int die_counter; | |
80 | int nl = 0; | |
81 | console_verbose(); | |
82 | spin_lock_irq(&die_lock); | |
1da177e4 LT |
83 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); |
84 | #ifdef CONFIG_PREEMPT | |
85 | printk("PREEMPT "); | |
86 | nl = 1; | |
87 | #endif | |
88 | #ifdef CONFIG_SMP | |
89 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
90 | nl = 1; | |
91 | #endif | |
92 | if (nl) | |
93 | printk("\n"); | |
94 | show_regs(fp); | |
95 | spin_unlock_irq(&die_lock); | |
96 | /* do_exit() should take care of panic'ing from an interrupt | |
97 | * context so we don't handle it here | |
98 | */ | |
99 | do_exit(err); | |
100 | } | |
101 | ||
102 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) | |
103 | { | |
104 | siginfo_t info; | |
105 | ||
106 | if (!user_mode(regs)) { | |
107 | debugger(regs); | |
108 | die("Exception in kernel mode", regs, signr); | |
109 | } | |
110 | info.si_signo = signr; | |
111 | info.si_errno = 0; | |
112 | info.si_code = code; | |
113 | info.si_addr = (void __user *) addr; | |
114 | force_sig_info(signr, &info, current); | |
bb0bb3b6 PM |
115 | |
116 | /* | |
117 | * Init gets no signals that it doesn't have a handler for. | |
118 | * That's all very well, but if it has caused a synchronous | |
119 | * exception and we ignore the resulting signal, it will just | |
120 | * generate the same exception over and over again and we get | |
121 | * nowhere. Better to kill it and let the kernel panic. | |
122 | */ | |
123 | if (current->pid == 1) { | |
124 | __sighandler_t handler; | |
125 | ||
126 | spin_lock_irq(¤t->sighand->siglock); | |
127 | handler = current->sighand->action[signr-1].sa.sa_handler; | |
128 | spin_unlock_irq(¤t->sighand->siglock); | |
129 | if (handler == SIG_DFL) { | |
130 | /* init has generated a synchronous exception | |
131 | and it doesn't have a handler for the signal */ | |
132 | printk(KERN_CRIT "init has generated signal %d " | |
133 | "but has no handler for it\n", signr); | |
134 | do_exit(signr); | |
135 | } | |
136 | } | |
1da177e4 LT |
137 | } |
138 | ||
139 | /* | |
140 | * I/O accesses can cause machine checks on powermacs. | |
141 | * Check if the NIP corresponds to the address of a sync | |
142 | * instruction for which there is an entry in the exception | |
143 | * table. | |
144 | * Note that the 601 only takes a machine check on TEA | |
145 | * (transfer error ack) signal assertion, and does not | |
146 | * set any of the top 16 bits of SRR1. | |
147 | * -- paulus. | |
148 | */ | |
149 | static inline int check_io_access(struct pt_regs *regs) | |
150 | { | |
a7fdd90b | 151 | #if defined CONFIG_8xx |
1da177e4 LT |
152 | unsigned long msr = regs->msr; |
153 | const struct exception_table_entry *entry; | |
154 | unsigned int *nip = (unsigned int *)regs->nip; | |
155 | ||
156 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
157 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
158 | /* | |
159 | * Check that it's a sync instruction, or somewhere | |
160 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
161 | * As the address is in the exception table | |
162 | * we should be able to read the instr there. | |
163 | * For the debug message, we look at the preceding | |
164 | * load or store. | |
165 | */ | |
166 | if (*nip == 0x60000000) /* nop */ | |
167 | nip -= 2; | |
168 | else if (*nip == 0x4c00012c) /* isync */ | |
169 | --nip; | |
55b6332e MT |
170 | /* eieio from I/O string functions */ |
171 | else if ((*nip) == 0x7c0006ac || *(nip+1) == 0x7c0006ac) | |
172 | nip += 2; | |
173 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3 || | |
174 | (*(nip+1) >> 26) == 3) { | |
1da177e4 LT |
175 | /* sync or twi */ |
176 | unsigned int rb; | |
177 | ||
178 | --nip; | |
179 | rb = (*nip >> 11) & 0x1f; | |
180 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
181 | (*nip & 0x100)? "OUT to": "IN from", | |
182 | regs->gpr[rb] - _IO_BASE, nip); | |
183 | regs->msr |= MSR_RI; | |
184 | regs->nip = entry->fixup; | |
185 | return 1; | |
186 | } | |
187 | } | |
a7fdd90b | 188 | #endif /* CONFIG_8xx */ |
1da177e4 LT |
189 | return 0; |
190 | } | |
191 | ||
192 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
193 | /* On 4xx, the reason for the machine check or program exception | |
194 | is in the ESR. */ | |
195 | #define get_reason(regs) ((regs)->dsisr) | |
33d9e9b5 | 196 | #ifndef CONFIG_FSL_BOOKE |
1da177e4 LT |
197 | #define get_mc_reason(regs) ((regs)->dsisr) |
198 | #else | |
199 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) | |
200 | #endif | |
443a848c | 201 | #define REASON_FP ESR_FP |
33d9e9b5 | 202 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) |
1da177e4 LT |
203 | #define REASON_PRIVILEGED ESR_PPR |
204 | #define REASON_TRAP ESR_PTR | |
205 | ||
206 | /* single-step stuff */ | |
207 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
208 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
209 | ||
210 | #else | |
211 | /* On non-4xx, the reason for the machine check or program | |
212 | exception is in the MSR. */ | |
213 | #define get_reason(regs) ((regs)->msr) | |
214 | #define get_mc_reason(regs) ((regs)->msr) | |
215 | #define REASON_FP 0x100000 | |
216 | #define REASON_ILLEGAL 0x80000 | |
217 | #define REASON_PRIVILEGED 0x40000 | |
218 | #define REASON_TRAP 0x20000 | |
219 | ||
220 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
221 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
222 | #endif | |
223 | ||
224 | /* | |
225 | * This is "fall-back" implementation for configurations | |
226 | * which don't provide platform-specific machine check info | |
227 | */ | |
228 | void __attribute__ ((weak)) | |
229 | platform_machine_check(struct pt_regs *regs) | |
230 | { | |
231 | } | |
232 | ||
dc1c1ca3 | 233 | void machine_check_exception(struct pt_regs *regs) |
1da177e4 LT |
234 | { |
235 | unsigned long reason = get_mc_reason(regs); | |
236 | ||
237 | if (user_mode(regs)) { | |
238 | regs->msr |= MSR_RI; | |
239 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
240 | return; | |
241 | } | |
242 | ||
243 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
244 | /* the qspan pci read routines can cause machine checks -- Cort */ | |
245 | bad_page_fault(regs, regs->dar, SIGBUS); | |
246 | return; | |
247 | #endif | |
248 | ||
249 | if (debugger_fault_handler) { | |
250 | debugger_fault_handler(regs); | |
251 | regs->msr |= MSR_RI; | |
252 | return; | |
253 | } | |
254 | ||
255 | if (check_io_access(regs)) | |
256 | return; | |
257 | ||
258 | #if defined(CONFIG_4xx) && !defined(CONFIG_440A) | |
259 | if (reason & ESR_IMCP) { | |
260 | printk("Instruction"); | |
261 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
262 | } else | |
263 | printk("Data"); | |
264 | printk(" machine check in kernel mode.\n"); | |
265 | #elif defined(CONFIG_440A) | |
266 | printk("Machine check in kernel mode.\n"); | |
267 | if (reason & ESR_IMCP){ | |
268 | printk("Instruction Synchronous Machine Check exception\n"); | |
269 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
270 | } | |
271 | else { | |
272 | u32 mcsr = mfspr(SPRN_MCSR); | |
273 | if (mcsr & MCSR_IB) | |
274 | printk("Instruction Read PLB Error\n"); | |
275 | if (mcsr & MCSR_DRB) | |
276 | printk("Data Read PLB Error\n"); | |
277 | if (mcsr & MCSR_DWB) | |
278 | printk("Data Write PLB Error\n"); | |
279 | if (mcsr & MCSR_TLBP) | |
280 | printk("TLB Parity Error\n"); | |
281 | if (mcsr & MCSR_ICP){ | |
282 | flush_instruction_cache(); | |
283 | printk("I-Cache Parity Error\n"); | |
284 | } | |
285 | if (mcsr & MCSR_DCSP) | |
286 | printk("D-Cache Search Parity Error\n"); | |
287 | if (mcsr & MCSR_DCFP) | |
288 | printk("D-Cache Flush Parity Error\n"); | |
289 | if (mcsr & MCSR_IMPE) | |
290 | printk("Machine Check exception is imprecise\n"); | |
291 | ||
292 | /* Clear MCSR */ | |
293 | mtspr(SPRN_MCSR, mcsr); | |
294 | } | |
295 | #elif defined (CONFIG_E500) | |
296 | printk("Machine check in kernel mode.\n"); | |
297 | printk("Caused by (from MCSR=%lx): ", reason); | |
298 | ||
299 | if (reason & MCSR_MCP) | |
300 | printk("Machine Check Signal\n"); | |
301 | if (reason & MCSR_ICPERR) | |
302 | printk("Instruction Cache Parity Error\n"); | |
303 | if (reason & MCSR_DCP_PERR) | |
304 | printk("Data Cache Push Parity Error\n"); | |
305 | if (reason & MCSR_DCPERR) | |
306 | printk("Data Cache Parity Error\n"); | |
307 | if (reason & MCSR_GL_CI) | |
308 | printk("Guarded Load or Cache-Inhibited stwcx.\n"); | |
309 | if (reason & MCSR_BUS_IAERR) | |
310 | printk("Bus - Instruction Address Error\n"); | |
311 | if (reason & MCSR_BUS_RAERR) | |
312 | printk("Bus - Read Address Error\n"); | |
313 | if (reason & MCSR_BUS_WAERR) | |
314 | printk("Bus - Write Address Error\n"); | |
315 | if (reason & MCSR_BUS_IBERR) | |
316 | printk("Bus - Instruction Data Error\n"); | |
317 | if (reason & MCSR_BUS_RBERR) | |
318 | printk("Bus - Read Data Bus Error\n"); | |
319 | if (reason & MCSR_BUS_WBERR) | |
320 | printk("Bus - Read Data Bus Error\n"); | |
321 | if (reason & MCSR_BUS_IPERR) | |
322 | printk("Bus - Instruction Parity Error\n"); | |
323 | if (reason & MCSR_BUS_RPERR) | |
324 | printk("Bus - Read Parity Error\n"); | |
33d9e9b5 KG |
325 | #elif defined (CONFIG_E200) |
326 | printk("Machine check in kernel mode.\n"); | |
327 | printk("Caused by (from MCSR=%lx): ", reason); | |
328 | ||
329 | if (reason & MCSR_MCP) | |
330 | printk("Machine Check Signal\n"); | |
331 | if (reason & MCSR_CP_PERR) | |
332 | printk("Cache Push Parity Error\n"); | |
333 | if (reason & MCSR_CPERR) | |
334 | printk("Cache Parity Error\n"); | |
335 | if (reason & MCSR_EXCP_ERR) | |
336 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
337 | if (reason & MCSR_BUS_IRERR) | |
338 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
339 | if (reason & MCSR_BUS_DRERR) | |
340 | printk("Bus - Read Bus Error on data load\n"); | |
341 | if (reason & MCSR_BUS_WRERR) | |
342 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
343 | #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ | |
1da177e4 LT |
344 | printk("Machine check in kernel mode.\n"); |
345 | printk("Caused by (from SRR1=%lx): ", reason); | |
346 | switch (reason & 0x601F0000) { | |
347 | case 0x80000: | |
348 | printk("Machine check signal\n"); | |
349 | break; | |
350 | case 0: /* for 601 */ | |
351 | case 0x40000: | |
352 | case 0x140000: /* 7450 MSS error and TEA */ | |
353 | printk("Transfer error ack signal\n"); | |
354 | break; | |
355 | case 0x20000: | |
356 | printk("Data parity error signal\n"); | |
357 | break; | |
358 | case 0x10000: | |
359 | printk("Address parity error signal\n"); | |
360 | break; | |
361 | case 0x20000000: | |
362 | printk("L1 Data Cache error\n"); | |
363 | break; | |
364 | case 0x40000000: | |
365 | printk("L1 Instruction Cache error\n"); | |
366 | break; | |
367 | case 0x00100000: | |
368 | printk("L2 data cache parity error\n"); | |
369 | break; | |
370 | default: | |
371 | printk("Unknown values in msr\n"); | |
372 | } | |
373 | #endif /* CONFIG_4xx */ | |
374 | ||
375 | /* | |
376 | * Optional platform-provided routine to print out | |
377 | * additional info, e.g. bus error registers. | |
378 | */ | |
379 | platform_machine_check(regs); | |
380 | ||
381 | debugger(regs); | |
382 | die("machine check", regs, SIGBUS); | |
383 | } | |
384 | ||
385 | void SMIException(struct pt_regs *regs) | |
386 | { | |
387 | debugger(regs); | |
388 | #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB)) | |
389 | show_regs(regs); | |
390 | panic("System Management Interrupt"); | |
391 | #endif | |
392 | } | |
393 | ||
dc1c1ca3 | 394 | void unknown_exception(struct pt_regs *regs) |
1da177e4 LT |
395 | { |
396 | printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
397 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
398 | _exception(SIGTRAP, regs, 0, 0); | |
399 | } | |
400 | ||
dc1c1ca3 | 401 | void instruction_breakpoint_exception(struct pt_regs *regs) |
1da177e4 LT |
402 | { |
403 | if (debugger_iabr_match(regs)) | |
404 | return; | |
405 | _exception(SIGTRAP, regs, TRAP_BRKPT, 0); | |
406 | } | |
407 | ||
408 | void RunModeException(struct pt_regs *regs) | |
409 | { | |
410 | _exception(SIGTRAP, regs, 0, 0); | |
411 | } | |
412 | ||
413 | /* Illegal instruction emulation support. Originally written to | |
414 | * provide the PVR to user applications using the mfspr rd, PVR. | |
415 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
416 | * memory access caused an access fault. Return zero on success. | |
417 | * | |
418 | * There are a couple of ways to do this, either "decode" the instruction | |
419 | * or directly match lots of bits. In this case, matching lots of | |
420 | * bits is faster and easier. | |
421 | * | |
422 | */ | |
423 | #define INST_MFSPR_PVR 0x7c1f42a6 | |
424 | #define INST_MFSPR_PVR_MASK 0xfc1fffff | |
425 | ||
426 | #define INST_DCBA 0x7c0005ec | |
427 | #define INST_DCBA_MASK 0x7c0007fe | |
428 | ||
429 | #define INST_MCRXR 0x7c000400 | |
430 | #define INST_MCRXR_MASK 0x7c0007fe | |
431 | ||
432 | #define INST_STRING 0x7c00042a | |
433 | #define INST_STRING_MASK 0x7c0007fe | |
434 | #define INST_STRING_GEN_MASK 0x7c00067e | |
435 | #define INST_LSWI 0x7c0004aa | |
436 | #define INST_LSWX 0x7c00042a | |
437 | #define INST_STSWI 0x7c0005aa | |
438 | #define INST_STSWX 0x7c00052a | |
439 | ||
440 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) | |
441 | { | |
442 | u8 rT = (instword >> 21) & 0x1f; | |
443 | u8 rA = (instword >> 16) & 0x1f; | |
444 | u8 NB_RB = (instword >> 11) & 0x1f; | |
445 | u32 num_bytes; | |
91de1fff | 446 | unsigned long EA; |
1da177e4 LT |
447 | int pos = 0; |
448 | ||
449 | /* Early out if we are an invalid form of lswx */ | |
450 | if ((instword & INST_STRING_MASK) == INST_LSWX) | |
92b4dc16 | 451 | if ((rT == rA) || (rT == NB_RB)) |
1da177e4 LT |
452 | return -EINVAL; |
453 | ||
454 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
455 | ||
456 | switch (instword & INST_STRING_MASK) { | |
457 | case INST_LSWX: | |
458 | case INST_STSWX: | |
459 | EA += NB_RB; | |
460 | num_bytes = regs->xer & 0x7f; | |
461 | break; | |
462 | case INST_LSWI: | |
463 | case INST_STSWI: | |
464 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; | |
465 | break; | |
466 | default: | |
467 | return -EINVAL; | |
468 | } | |
469 | ||
470 | while (num_bytes != 0) | |
471 | { | |
472 | u8 val; | |
473 | u32 shift = 8 * (3 - (pos & 0x3)); | |
474 | ||
475 | switch ((instword & INST_STRING_MASK)) { | |
476 | case INST_LSWX: | |
477 | case INST_LSWI: | |
478 | if (get_user(val, (u8 __user *)EA)) | |
479 | return -EFAULT; | |
480 | /* first time updating this reg, | |
481 | * zero it out */ | |
482 | if (pos == 0) | |
483 | regs->gpr[rT] = 0; | |
484 | regs->gpr[rT] |= val << shift; | |
485 | break; | |
486 | case INST_STSWI: | |
487 | case INST_STSWX: | |
488 | val = regs->gpr[rT] >> shift; | |
489 | if (put_user(val, (u8 __user *)EA)) | |
490 | return -EFAULT; | |
491 | break; | |
492 | } | |
493 | /* move EA to next address */ | |
494 | EA += 1; | |
495 | num_bytes--; | |
496 | ||
497 | /* manage our position within the register */ | |
498 | if (++pos == 4) { | |
499 | pos = 0; | |
500 | if (++rT == 32) | |
501 | rT = 0; | |
502 | } | |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
508 | static int emulate_instruction(struct pt_regs *regs) | |
509 | { | |
510 | u32 instword; | |
511 | u32 rd; | |
512 | ||
513 | if (!user_mode(regs)) | |
514 | return -EINVAL; | |
515 | CHECK_FULL_REGS(regs); | |
516 | ||
517 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
518 | return -EFAULT; | |
519 | ||
520 | /* Emulate the mfspr rD, PVR. | |
521 | */ | |
522 | if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { | |
523 | rd = (instword >> 21) & 0x1f; | |
524 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
525 | return 0; | |
526 | } | |
527 | ||
528 | /* Emulating the dcba insn is just a no-op. */ | |
529 | if ((instword & INST_DCBA_MASK) == INST_DCBA) | |
530 | return 0; | |
531 | ||
532 | /* Emulate the mcrxr insn. */ | |
533 | if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { | |
534 | int shift = (instword >> 21) & 0x1c; | |
535 | unsigned long msk = 0xf0000000UL >> shift; | |
536 | ||
537 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); | |
538 | regs->xer &= ~0xf0000000UL; | |
539 | return 0; | |
540 | } | |
541 | ||
542 | /* Emulate load/store string insn. */ | |
543 | if ((instword & INST_STRING_GEN_MASK) == INST_STRING) | |
544 | return emulate_string_inst(regs, instword); | |
545 | ||
546 | return -EINVAL; | |
547 | } | |
548 | ||
549 | /* | |
550 | * After we have successfully emulated an instruction, we have to | |
551 | * check if the instruction was being single-stepped, and if so, | |
552 | * pretend we got a single-step exception. This was pointed out | |
553 | * by Kumar Gala. -- paulus | |
554 | */ | |
555 | static void emulate_single_step(struct pt_regs *regs) | |
556 | { | |
557 | if (single_stepping(regs)) { | |
558 | clear_single_step(regs); | |
559 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
560 | } | |
561 | } | |
562 | ||
563 | /* | |
564 | * Look through the list of trap instructions that are used for BUG(), | |
565 | * BUG_ON() and WARN_ON() and see if we hit one. At this point we know | |
566 | * that the exception was caused by a trap instruction of some kind. | |
567 | * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0 | |
568 | * otherwise. | |
569 | */ | |
570 | extern struct bug_entry __start___bug_table[], __stop___bug_table[]; | |
571 | ||
572 | #ifndef CONFIG_MODULES | |
573 | #define module_find_bug(x) NULL | |
574 | #endif | |
575 | ||
25433b12 | 576 | struct bug_entry *find_bug(unsigned long bugaddr) |
1da177e4 LT |
577 | { |
578 | struct bug_entry *bug; | |
579 | ||
580 | for (bug = __start___bug_table; bug < __stop___bug_table; ++bug) | |
581 | if (bugaddr == bug->bug_addr) | |
582 | return bug; | |
583 | return module_find_bug(bugaddr); | |
584 | } | |
585 | ||
586 | int check_bug_trap(struct pt_regs *regs) | |
587 | { | |
588 | struct bug_entry *bug; | |
589 | unsigned long addr; | |
590 | ||
591 | if (regs->msr & MSR_PR) | |
592 | return 0; /* not in kernel */ | |
593 | addr = regs->nip; /* address of trap instruction */ | |
594 | if (addr < PAGE_OFFSET) | |
595 | return 0; | |
596 | bug = find_bug(regs->nip); | |
597 | if (bug == NULL) | |
598 | return 0; | |
599 | if (bug->line & BUG_WARNING_TRAP) { | |
600 | /* this is a WARN_ON rather than BUG/BUG_ON */ | |
601 | #ifdef CONFIG_XMON | |
9122ee33 | 602 | xmon_printf(KERN_ERR "Badness in %s at %s:%ld\n", |
1da177e4 LT |
603 | bug->function, bug->file, |
604 | bug->line & ~BUG_WARNING_TRAP); | |
605 | #endif /* CONFIG_XMON */ | |
9122ee33 | 606 | printk(KERN_ERR "Badness in %s at %s:%ld\n", |
1da177e4 LT |
607 | bug->function, bug->file, |
608 | bug->line & ~BUG_WARNING_TRAP); | |
609 | dump_stack(); | |
610 | return 1; | |
611 | } | |
612 | #ifdef CONFIG_XMON | |
9122ee33 | 613 | xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%ld!\n", |
1da177e4 LT |
614 | bug->function, bug->file, bug->line); |
615 | xmon(regs); | |
616 | #endif /* CONFIG_XMON */ | |
9122ee33 | 617 | printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n", |
1da177e4 LT |
618 | bug->function, bug->file, bug->line); |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
dc1c1ca3 | 623 | void program_check_exception(struct pt_regs *regs) |
1da177e4 LT |
624 | { |
625 | unsigned int reason = get_reason(regs); | |
626 | extern int do_mathemu(struct pt_regs *regs); | |
627 | ||
628 | #ifdef CONFIG_MATH_EMULATION | |
629 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
630 | * but there seems to be a hardware bug on the 405GP (RevD) | |
631 | * that means ESR is sometimes set incorrectly - either to | |
632 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
633 | * hardware people - not sure if it can happen on any illegal | |
634 | * instruction or only on FP instructions, whether there is a | |
635 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
636 | if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { | |
637 | emulate_single_step(regs); | |
638 | return; | |
639 | } | |
640 | #endif /* CONFIG_MATH_EMULATION */ | |
641 | ||
642 | if (reason & REASON_FP) { | |
643 | /* IEEE FP exception */ | |
644 | int code = 0; | |
645 | u32 fpscr; | |
646 | ||
647 | /* We must make sure the FP state is consistent with | |
648 | * our MSR_FP in regs | |
649 | */ | |
650 | preempt_disable(); | |
651 | if (regs->msr & MSR_FP) | |
652 | giveup_fpu(current); | |
653 | preempt_enable(); | |
654 | ||
25c8a78b | 655 | fpscr = current->thread.fpscr.val; |
1da177e4 LT |
656 | fpscr &= fpscr << 22; /* mask summary bits with enables */ |
657 | if (fpscr & FPSCR_VX) | |
658 | code = FPE_FLTINV; | |
659 | else if (fpscr & FPSCR_OX) | |
660 | code = FPE_FLTOVF; | |
661 | else if (fpscr & FPSCR_UX) | |
662 | code = FPE_FLTUND; | |
663 | else if (fpscr & FPSCR_ZX) | |
664 | code = FPE_FLTDIV; | |
665 | else if (fpscr & FPSCR_XX) | |
666 | code = FPE_FLTRES; | |
667 | _exception(SIGFPE, regs, code, regs->nip); | |
668 | return; | |
669 | } | |
670 | ||
671 | if (reason & REASON_TRAP) { | |
672 | /* trap exception */ | |
673 | if (debugger_bpt(regs)) | |
674 | return; | |
675 | if (check_bug_trap(regs)) { | |
676 | regs->nip += 4; | |
677 | return; | |
678 | } | |
679 | _exception(SIGTRAP, regs, TRAP_BRKPT, 0); | |
680 | return; | |
681 | } | |
682 | ||
683 | /* Try to emulate it if we should. */ | |
684 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
685 | switch (emulate_instruction(regs)) { | |
686 | case 0: | |
687 | regs->nip += 4; | |
688 | emulate_single_step(regs); | |
689 | return; | |
690 | case -EFAULT: | |
691 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
692 | return; | |
693 | } | |
694 | } | |
695 | ||
696 | if (reason & REASON_PRIVILEGED) | |
697 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
698 | else | |
699 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
700 | } | |
701 | ||
dc1c1ca3 | 702 | void single_step_exception(struct pt_regs *regs) |
1da177e4 LT |
703 | { |
704 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
705 | if (debugger_sstep(regs)) | |
706 | return; | |
707 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
708 | } | |
709 | ||
dc1c1ca3 | 710 | void alignment_exception(struct pt_regs *regs) |
1da177e4 LT |
711 | { |
712 | int fixed; | |
713 | ||
714 | fixed = fix_alignment(regs); | |
715 | if (fixed == 1) { | |
716 | regs->nip += 4; /* skip over emulated instruction */ | |
6c26e03b | 717 | emulate_single_step(regs); |
1da177e4 LT |
718 | return; |
719 | } | |
720 | if (fixed == -EFAULT) { | |
721 | /* fixed == -EFAULT means the operand address was bad */ | |
722 | if (user_mode(regs)) | |
723 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar); | |
724 | else | |
725 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
726 | return; | |
727 | } | |
728 | _exception(SIGBUS, regs, BUS_ADRALN, regs->dar); | |
729 | } | |
730 | ||
731 | void StackOverflow(struct pt_regs *regs) | |
732 | { | |
733 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
734 | current, regs->gpr[1]); | |
735 | debugger(regs); | |
736 | show_regs(regs); | |
737 | panic("kernel stack overflow"); | |
738 | } | |
739 | ||
740 | void nonrecoverable_exception(struct pt_regs *regs) | |
741 | { | |
742 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
743 | regs->nip, regs->msr); | |
744 | debugger(regs); | |
745 | die("nonrecoverable exception", regs, SIGKILL); | |
746 | } | |
747 | ||
748 | void trace_syscall(struct pt_regs *regs) | |
749 | { | |
750 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
751 | current, current->pid, regs->nip, regs->link, regs->gpr[0], | |
752 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); | |
753 | } | |
754 | ||
755 | #ifdef CONFIG_8xx | |
756 | void SoftwareEmulation(struct pt_regs *regs) | |
757 | { | |
758 | extern int do_mathemu(struct pt_regs *); | |
759 | extern int Soft_emulate_8xx(struct pt_regs *); | |
760 | int errcode; | |
761 | ||
762 | CHECK_FULL_REGS(regs); | |
763 | ||
764 | if (!user_mode(regs)) { | |
765 | debugger(regs); | |
766 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
767 | } | |
768 | ||
769 | #ifdef CONFIG_MATH_EMULATION | |
770 | errcode = do_mathemu(regs); | |
771 | #else | |
772 | errcode = Soft_emulate_8xx(regs); | |
773 | #endif | |
774 | if (errcode) { | |
775 | if (errcode > 0) | |
776 | _exception(SIGFPE, regs, 0, 0); | |
777 | else if (errcode == -EFAULT) | |
778 | _exception(SIGSEGV, regs, 0, 0); | |
779 | else | |
780 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
781 | } else | |
782 | emulate_single_step(regs); | |
783 | } | |
784 | #endif /* CONFIG_8xx */ | |
785 | ||
786 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
787 | ||
788 | void DebugException(struct pt_regs *regs, unsigned long debug_status) | |
789 | { | |
790 | if (debug_status & DBSR_IC) { /* instruction completion */ | |
791 | regs->msr &= ~MSR_DE; | |
792 | if (user_mode(regs)) { | |
793 | current->thread.dbcr0 &= ~DBCR0_IC; | |
794 | } else { | |
795 | /* Disable instruction completion */ | |
796 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
797 | /* Clear the instruction completion event */ | |
798 | mtspr(SPRN_DBSR, DBSR_IC); | |
799 | if (debugger_sstep(regs)) | |
800 | return; | |
801 | } | |
802 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
803 | } | |
804 | } | |
805 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
806 | ||
807 | #if !defined(CONFIG_TAU_INT) | |
808 | void TAUException(struct pt_regs *regs) | |
809 | { | |
810 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
811 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
812 | } | |
813 | #endif /* CONFIG_INT_TAU */ | |
814 | ||
fd582ec8 PM |
815 | /* |
816 | * FP unavailable trap from kernel - print a message, but let | |
817 | * the task use FP in the kernel until it returns to user mode. | |
818 | */ | |
819 | void kernel_fp_unavailable_exception(struct pt_regs *regs) | |
820 | { | |
821 | regs->msr |= MSR_FP; | |
822 | printk(KERN_ERR "floating point used in kernel (task=%p, pc=%lx)\n", | |
823 | current, regs->nip); | |
824 | } | |
825 | ||
dc1c1ca3 | 826 | void altivec_unavailable_exception(struct pt_regs *regs) |
1da177e4 LT |
827 | { |
828 | static int kernel_altivec_count; | |
829 | ||
830 | #ifndef CONFIG_ALTIVEC | |
831 | if (user_mode(regs)) { | |
832 | /* A user program has executed an altivec instruction, | |
833 | but this kernel doesn't support altivec. */ | |
834 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
835 | return; | |
836 | } | |
837 | #endif | |
838 | /* The kernel has executed an altivec instruction without | |
839 | first enabling altivec. Whinge but let it do it. */ | |
840 | if (++kernel_altivec_count < 10) | |
841 | printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n", | |
842 | current, regs->nip); | |
843 | regs->msr |= MSR_VEC; | |
844 | } | |
845 | ||
846 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 847 | void altivec_assist_exception(struct pt_regs *regs) |
1da177e4 LT |
848 | { |
849 | int err; | |
850 | ||
851 | preempt_disable(); | |
852 | if (regs->msr & MSR_VEC) | |
853 | giveup_altivec(current); | |
854 | preempt_enable(); | |
e378cc16 PM |
855 | if (!user_mode(regs)) { |
856 | printk(KERN_ERR "altivec assist exception in kernel mode" | |
857 | " at %lx\n", regs->nip); | |
858 | debugger(regs); | |
859 | die("altivec assist exception", regs, SIGFPE); | |
860 | return; | |
861 | } | |
1da177e4 LT |
862 | |
863 | err = emulate_altivec(regs); | |
864 | if (err == 0) { | |
865 | regs->nip += 4; /* skip emulated instruction */ | |
866 | emulate_single_step(regs); | |
867 | return; | |
868 | } | |
869 | ||
870 | if (err == -EFAULT) { | |
871 | /* got an error reading the instruction */ | |
872 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
873 | } else { | |
874 | /* didn't recognize the instruction */ | |
875 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
876 | printk(KERN_ERR "unrecognized altivec instruction " | |
877 | "in %s at %lx\n", current->comm, regs->nip); | |
878 | current->thread.vscr.u[3] |= 0x10000; | |
879 | } | |
880 | } | |
881 | #endif /* CONFIG_ALTIVEC */ | |
882 | ||
83f7da8a | 883 | #ifdef CONFIG_E500 |
dc1c1ca3 | 884 | void performance_monitor_exception(struct pt_regs *regs) |
1da177e4 LT |
885 | { |
886 | perf_irq(regs); | |
887 | } | |
83f7da8a | 888 | #endif |
1da177e4 LT |
889 | |
890 | #ifdef CONFIG_FSL_BOOKE | |
891 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
892 | unsigned long error_code) | |
893 | { | |
894 | /* We treat cache locking instructions from the user | |
895 | * as priv ops, in the future we could try to do | |
896 | * something smarter | |
897 | */ | |
898 | if (error_code & (ESR_DLK|ESR_ILK)) | |
899 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
900 | return; | |
901 | } | |
902 | #endif /* CONFIG_FSL_BOOKE */ | |
903 | ||
904 | #ifdef CONFIG_SPE | |
905 | void SPEFloatingPointException(struct pt_regs *regs) | |
906 | { | |
907 | unsigned long spefscr; | |
908 | int fpexc_mode; | |
909 | int code = 0; | |
910 | ||
911 | spefscr = current->thread.spefscr; | |
912 | fpexc_mode = current->thread.fpexc_mode; | |
913 | ||
914 | /* Hardware does not neccessarily set sticky | |
915 | * underflow/overflow/invalid flags */ | |
916 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { | |
917 | code = FPE_FLTOVF; | |
918 | spefscr |= SPEFSCR_FOVFS; | |
919 | } | |
920 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
921 | code = FPE_FLTUND; | |
922 | spefscr |= SPEFSCR_FUNFS; | |
923 | } | |
924 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
925 | code = FPE_FLTDIV; | |
926 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
927 | code = FPE_FLTINV; | |
928 | spefscr |= SPEFSCR_FINVS; | |
929 | } | |
930 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
931 | code = FPE_FLTRES; | |
932 | ||
933 | current->thread.spefscr = spefscr; | |
934 | ||
935 | _exception(SIGFPE, regs, code, regs->nip); | |
936 | return; | |
937 | } | |
938 | #endif | |
939 | ||
a2f40ccd KG |
940 | #ifdef CONFIG_BOOKE_WDT |
941 | /* | |
942 | * Default handler for a Watchdog exception, | |
943 | * spins until a reboot occurs | |
944 | */ | |
945 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
946 | { | |
947 | /* Generic WatchdogHandler, implement your own */ | |
948 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
949 | return; | |
950 | } | |
951 | ||
952 | void WatchdogException(struct pt_regs *regs) | |
953 | { | |
954 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
955 | WatchdogHandler(regs); | |
956 | } | |
957 | #endif | |
958 | ||
1da177e4 LT |
959 | void __init trap_init(void) |
960 | { | |
961 | } |