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[PATCH] powerpc: trivial: modify comments to refer to new location of files
[deliverable/linux.git] / arch / ppc / platforms / 4xx / ebony.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Ebony board specific routines
3 *
4 * Matt Porter <mporter@kernel.crashing.org>
5 * Copyright 2002-2005 MontaVista Software Inc.
6 *
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
5ce17b18 8 * Copyright (c) 2003-2005 Zultys Technologies
1da177e4
LT		 9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/config.h>
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/errno.h>
21#include <linux/reboot.h>
22#include <linux/pci.h>
23#include <linux/kdev_t.h>
24#include <linux/types.h>
25#include <linux/major.h>
26#include <linux/blkdev.h>
27#include <linux/console.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/initrd.h>
1da177e4
LT		 31#include <linux/seq_file.h>
32#include <linux/root_dev.h>
33#include <linux/tty.h>
34#include <linux/serial.h>
35#include <linux/serial_core.h>
36
37#include <asm/system.h>
38#include <asm/pgtable.h>
39#include <asm/page.h>
40#include <asm/dma.h>
41#include <asm/io.h>
42#include <asm/machdep.h>
43#include <asm/ocp.h>
44#include <asm/pci-bridge.h>
45#include <asm/time.h>
46#include <asm/todc.h>
47#include <asm/bootinfo.h>
48#include <asm/ppc4xx_pic.h>
49#include <asm/ppcboot.h>
5ce17b18 50#include <asm/tlbflush.h>
1da177e4
LT		 51
52#include <syslib/gen550.h>
53#include <syslib/ibm440gp_common.h>
54
d5f7b06b 55extern bd_t __res;
1da177e4
LT		 56
57static struct ibm44x_clocks clocks __initdata;
58
59/*
60 * Ebony external IRQ triggering/polarity settings
61 */
62unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
68 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
76};
77
78static void __init
79ebony_calibrate_decr(void)
80{
81 unsigned int freq;
82
83 /*
84 * Determine system clock speed
85 *
86 * If we are on Rev. B silicon, then use
87 * default external system clock. If we are
88 * on Rev. C silicon then errata forces us to
89 * use the internal clock.
90 */
400d2212 91 if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0)
95409aac
TR		 92 freq = EBONY_440GP_RB_SYSCLK;
93 else
94 freq = EBONY_440GP_RC_SYSCLK;
1da177e4
LT		 95
96 ibm44x_calibrate_decr(freq);
97}
98
99static int
100ebony_show_cpuinfo(struct seq_file *m)
101{
102 seq_printf(m, "vendor\t\t: IBM\n");
103 seq_printf(m, "machine\t\t: Ebony\n");
104
105 return 0;
106}
107
108static inline int
109ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
110{
111 static char pci_irq_table[][4] =
112 /*
113 * PCI IDSEL/INTPIN->INTLINE
114 * A B C D
115 */
116 {
117 { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
118 { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
119 { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
120 { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
121 };
122
123 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
124 return PCI_IRQ_TABLE_LOOKUP;
125}
126
127#define PCIX_WRITEL(value, offset) \
128 (writel(value, pcix_reg_base + offset))
129
130/*
131 * FIXME: This is only here to "make it work". This will move
132 * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
133 * configuration library. -Matt
134 */
135static void __init
136ebony_setup_pcix(void)
137{
ba724a37 138 void __iomem *pcix_reg_base;
1da177e4
LT		 139
140 pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
141
142 /* Disable all windows */
143 PCIX_WRITEL(0, PCIX0_POM0SA);
144 PCIX_WRITEL(0, PCIX0_POM1SA);
145 PCIX_WRITEL(0, PCIX0_POM2SA);
146 PCIX_WRITEL(0, PCIX0_PIM0SA);
147 PCIX_WRITEL(0, PCIX0_PIM1SA);
148 PCIX_WRITEL(0, PCIX0_PIM2SA);
149
150 /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
151 PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
152 PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
153 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
154 PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
155 PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
156
157 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
158 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
159 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
160 PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
161
162 eieio();
163}
164
165static void __init
166ebony_setup_hose(void)
167{
168 struct pci_controller *hose;
169
170 /* Configure windows on the PCI-X host bridge */
171 ebony_setup_pcix();
172
173 hose = pcibios_alloc_controller();
174
175 if (!hose)
176 return;
177
178 hose->first_busno = 0;
179 hose->last_busno = 0xff;
180
181 hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
182
183 pci_init_resource(&hose->io_resource,
184 EBONY_PCI_LOWER_IO,
185 EBONY_PCI_UPPER_IO,
186 IORESOURCE_IO,
187 "PCI host bridge");
188
189 pci_init_resource(&hose->mem_resources[0],
190 EBONY_PCI_LOWER_MEM,
191 EBONY_PCI_UPPER_MEM,
192 IORESOURCE_MEM,
193 "PCI host bridge");
194
195 hose->io_space.start = EBONY_PCI_LOWER_IO;
196 hose->io_space.end = EBONY_PCI_UPPER_IO;
197 hose->mem_space.start = EBONY_PCI_LOWER_MEM;
198 hose->mem_space.end = EBONY_PCI_UPPER_MEM;
92a11f9e
AV		 199 hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
200 isa_io_base = (unsigned long)hose->io_base_virt;
1da177e4
LT		 201
202 setup_indirect_pci(hose,
203 EBONY_PCI_CFGA_PLB32,
204 EBONY_PCI_CFGD_PLB32);
205 hose->set_cfg_type = 1;
206
207 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
208
209 ppc_md.pci_swizzle = common_swizzle;
210 ppc_md.pci_map_irq = ebony_map_irq;
211}
212
213TODC_ALLOC();
214
215static void __init
216ebony_early_serial_map(void)
217{
218 struct uart_port port;
219
220 /* Setup ioremapped serial port access */
221 memset(&port, 0, sizeof(port));
222 port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
223 port.irq = 0;
224 port.uartclk = clocks.uart0;
225 port.regshift = 0;
9b4a1617 226 port.iotype = UPIO_MEM;
59a675b2 227 port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
1da177e4
LT		 228 port.line = 0;
229
230 if (early_serial_setup(&port) != 0) {
231 printk("Early serial init of port 0 failed\n");
232 }
233
234#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
235 /* Configure debug serial access */
236 gen550_init(0, &port);
5ce17b18
ES		 237
238 /* Purge TLB entry added in head_44x.S for early serial access */
239 _tlbie(UART0_IO_BASE);
1da177e4
LT		 240#endif
241
242 port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
243 port.irq = 1;
244 port.uartclk = clocks.uart1;
245 port.line = 1;
246
247 if (early_serial_setup(&port) != 0) {
248 printk("Early serial init of port 1 failed\n");
249 }
250
251#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
252 /* Configure debug serial access */
253 gen550_init(1, &port);
254#endif
255}
256
257static void __init
258ebony_setup_arch(void)
259{
260 struct ocp_def *def;
261 struct ocp_func_emac_data *emacdata;
262
263 /* Set mac_addr for each EMAC */
264 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
265 emacdata = def->additions;
266 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
267 emacdata->phy_mode = PHY_MODE_RMII;
268 memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
269
270 def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
271 emacdata = def->additions;
272 emacdata->phy_map = 0x00000001; /* Skip 0x00 */
273 emacdata->phy_mode = PHY_MODE_RMII;
274 memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
275
276 /*
277 * Determine various clocks.
278 * To be completely correct we should get SysClk
279 * from FPGA, because it can be changed by on-board switches
280 * --ebs
281 */
282 ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
283 ocp_sys_info.opb_bus_freq = clocks.opb;
284
285 /* Setup TODC access */
286 TODC_INIT(TODC_TYPE_DS1743,
287 0,
288 0,
289 ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
290 8);
291
292 /* init to some ~sane value until calibrate_delay() runs */
293 loops_per_jiffy = 50000000/HZ;
294
295 /* Setup PCI host bridge */
296 ebony_setup_hose();
297
298#ifdef CONFIG_BLK_DEV_INITRD
299 if (initrd_start)
300 ROOT_DEV = Root_RAM0;
301 else
302#endif
303#ifdef CONFIG_ROOT_NFS
304 ROOT_DEV = Root_NFS;
305#else
306 ROOT_DEV = Root_HDA1;
307#endif
308
309 ebony_early_serial_map();
310
311 /* Identify the system */
312 printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
313}
314
315void __init platform_init(unsigned long r3, unsigned long r4,
316 unsigned long r5, unsigned long r6, unsigned long r7)
317{
d5f7b06b 318 ibm44x_platform_init(r3, r4, r5, r6, r7);
1da177e4
LT		 319
320 ppc_md.setup_arch = ebony_setup_arch;
321 ppc_md.show_cpuinfo = ebony_show_cpuinfo;
322 ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
323
324 ppc_md.calibrate_decr = ebony_calibrate_decr;
325 ppc_md.time_init = todc_time_init;
326 ppc_md.set_rtc_time = todc_set_rtc_time;
327 ppc_md.get_rtc_time = todc_get_rtc_time;
328
329 ppc_md.nvram_read_val = todc_direct_read_val;
330 ppc_md.nvram_write_val = todc_direct_write_val;
331#ifdef CONFIG_KGDB
332 ppc_md.early_serial_map = ebony_early_serial_map;
333#endif
334}
335
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