Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Author: Armin Kuster <akuster@mvista.com> |
3 | * | |
4 | * 2002 (c) MontaVista, Software, Inc. This file is licensed under | |
5 | * the terms of the GNU General Public License version 2. This program | |
6 | * is licensed "as is" without any warranty of any kind, whether express | |
7 | * or implied. | |
8 | */ | |
9 | ||
10 | #ifdef __KERNEL__ | |
11 | #ifndef __ASM_IBM405GPR_H__ | |
12 | #define __ASM_IBM405GPR_H__ | |
13 | ||
14 | #include <linux/config.h> | |
15 | ||
16 | /* ibm405.h at bottom of this file */ | |
17 | ||
18 | /* PCI | |
19 | * PCI Bridge config reg definitions | |
20 | * see 17-19 of manual | |
21 | */ | |
22 | ||
23 | #define PPC405_PCI_CONFIG_ADDR 0xeec00000 | |
24 | #define PPC405_PCI_CONFIG_DATA 0xeec00004 | |
25 | ||
26 | #define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */ | |
27 | /* setbat */ | |
28 | #define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */ | |
29 | #define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */ | |
30 | #define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */ | |
31 | ||
32 | #define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */ | |
33 | #define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */ | |
34 | #define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */ | |
35 | #define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */ | |
36 | ||
37 | #define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE | |
38 | ||
39 | #define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE) | |
40 | #define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR | |
41 | #define PPC4xx_PCI_IO_SIZE ((uint)64*1024) | |
42 | #define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR) | |
43 | #define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR | |
44 | #define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) | |
45 | #define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000) | |
46 | #define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR | |
47 | #define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) | |
48 | #define PPC4xx_ONB_IO_PADDR ((uint)0xef600000) | |
49 | #define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR | |
50 | #define PPC4xx_ONB_IO_SIZE ((uint)4*1024) | |
51 | ||
52 | /* serial port defines */ | |
53 | #define RS_TABLE_SIZE 2 | |
54 | ||
55 | #define UART0_INT 0 | |
56 | #define UART1_INT 1 | |
57 | ||
58 | #define PCIL0_BASE 0xEF400000 | |
59 | #define UART0_IO_BASE 0xEF600300 | |
60 | #define UART1_IO_BASE 0xEF600400 | |
61 | #define EMAC0_BASE 0xEF600800 | |
62 | ||
63 | #define BD_EMAC_ADDR(e,i) bi_enetaddr[i] | |
64 | ||
65 | #define STD_UART_OP(num) \ | |
66 | { 0, BASE_BAUD, 0, UART##num##_INT, \ | |
67 | (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ | |
68 | iomem_base: (u8 *)UART##num##_IO_BASE, \ | |
69 | io_type: SERIAL_IO_MEM}, | |
70 | ||
71 | #if defined(CONFIG_UART0_TTYS0) | |
72 | #define SERIAL_DEBUG_IO_BASE UART0_IO_BASE | |
73 | #define SERIAL_PORT_DFNS \ | |
74 | STD_UART_OP(0) \ | |
75 | STD_UART_OP(1) | |
76 | #endif | |
77 | ||
78 | #if defined(CONFIG_UART0_TTYS1) | |
79 | #define SERIAL_DEBUG_IO_BASE UART1_IO_BASE | |
80 | #define SERIAL_PORT_DFNS \ | |
81 | STD_UART_OP(1) \ | |
82 | STD_UART_OP(0) | |
83 | #endif | |
84 | ||
85 | /* DCR defines */ | |
86 | #define DCRN_CHCR_BASE 0x0B1 | |
87 | #define DCRN_CHPSR_BASE 0x0B4 | |
88 | #define DCRN_CPMSR_BASE 0x0B8 | |
89 | #define DCRN_CPMFR_BASE 0x0BA | |
90 | ||
91 | #define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */ | |
92 | #define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */ | |
93 | #define CHR0_UDIV 0x0000003E /* UART internal clock divisor */ | |
94 | #define CHR1_CETE 0x00800000 /* CPU external timer enable */ | |
95 | ||
96 | #define DCRN_CHPSR_BASE 0x0B4 | |
97 | #define PSR_PLL_FWD_MASK 0xC0000000 | |
98 | #define PSR_PLL_FDBACK_MASK 0x30000000 | |
99 | #define PSR_PLL_TUNING_MASK 0x0E000000 | |
100 | #define PSR_PLB_CPU_MASK 0x01800000 | |
101 | #define PSR_OPB_PLB_MASK 0x00600000 | |
102 | #define PSR_PCI_PLB_MASK 0x00180000 | |
103 | #define PSR_EB_PLB_MASK 0x00060000 | |
104 | #define PSR_ROM_WIDTH_MASK 0x00018000 | |
105 | #define PSR_ROM_LOC 0x00004000 | |
106 | #define PSR_PCI_ASYNC_EN 0x00001000 | |
107 | #define PSR_PCI_ARBIT_EN 0x00000400 | |
108 | ||
109 | #define IBM_CPM_IIC0 0x80000000 /* IIC interface */ | |
110 | #define IBM_CPM_PCI 0x40000000 /* PCI bridge */ | |
111 | #define IBM_CPM_CPU 0x20000000 /* processor core */ | |
112 | #define IBM_CPM_DMA 0x10000000 /* DMA controller */ | |
113 | #define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */ | |
114 | #define IBM_CPM_DCP 0x04000000 /* CodePack */ | |
115 | #define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */ | |
116 | #define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */ | |
117 | #define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */ | |
118 | #define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */ | |
119 | #define IBM_CPM_UART0 0x00200000 /* serial port 0 */ | |
120 | #define IBM_CPM_UART1 0x00100000 /* serial port 1 */ | |
121 | #define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */ | |
122 | #define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */ | |
123 | #define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */ | |
124 | #define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \ | |
125 | | IBM_CPM_OPB | IBM_CPM_EBC \ | |
126 | | IBM_CPM_SDRAM0 | IBM_CPM_PLB \ | |
127 | | IBM_CPM_UIC | IBM_CPM_TMRCLK) | |
128 | ||
129 | #define DCRN_DMA0_BASE 0x100 | |
130 | #define DCRN_DMA1_BASE 0x108 | |
131 | #define DCRN_DMA2_BASE 0x110 | |
132 | #define DCRN_DMA3_BASE 0x118 | |
133 | #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ | |
134 | #define DCRN_DMASR_BASE 0x120 | |
135 | #define DCRN_EBC_BASE 0x012 | |
136 | #define DCRN_DCP0_BASE 0x014 | |
137 | #define DCRN_MAL_BASE 0x180 | |
138 | #define DCRN_OCM0_BASE 0x018 | |
139 | #define DCRN_PLB0_BASE 0x084 | |
140 | #define DCRN_PLLMR_BASE 0x0B0 | |
141 | #define DCRN_POB0_BASE 0x0A0 | |
142 | #define DCRN_SDRAM0_BASE 0x010 | |
143 | #define DCRN_UIC0_BASE 0x0C0 | |
144 | #define UIC0 DCRN_UIC0_BASE | |
145 | ||
146 | #include <asm/ibm405.h> | |
147 | ||
148 | #endif /* __ASM_IBM405GPR_H__ */ | |
149 | #endif /* __KERNEL__ */ |