[deliverable/linux.git] / arch / ppc / platforms / 4xx / ibmstbx25.h

/*
 * Author: Armin Kuster <akuster@mvista.com>
 *
 * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#ifdef __KERNEL__
#ifndef __ASM_IBMSTBX25_H__
#define __ASM_IBMSTBX25_H__

#include <linux/config.h>

/* serial port defines */
#define STBx25xx_IO_BASE	((uint)0xe0000000)
#define PPC4xx_ONB_IO_PADDR	STBx25xx_IO_BASE
#define PPC4xx_ONB_IO_VADDR	((uint)0xe0000000)
#define PPC4xx_ONB_IO_SIZE	((uint)14*64*1024)

/*
 * map STBxxxx internal i/o address (0x400x00xx) to an address
 * which is below the 2GB limit...
 *
 * 4000 000x	uart1		-> 0xe000 000x
 * 4001 00xx	uart2
 * 4002 00xx	smart card
 * 4003 000x	iic
 * 4004 000x	uart0
 * 4005 0xxx	timer
 * 4006 00xx	gpio
 * 4007 00xx	smart card
 * 400b 000x	iic
 * 400c 000x	scp
 * 400d 000x	modem
 * 400e 000x	uart2
*/
#define STBx25xx_MAP_IO_ADDR(a)	(((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000))

#define RS_TABLE_SIZE	3

#define OPB_BASE_START	0x40000000
#define EBIU_BASE_START	0xF0100000
#define DCR_BASE_START  0x0000

#ifdef __BOOTER__
#define UART1_IO_BASE	0x40000000
#define UART2_IO_BASE	0x40010000
#else
#define UART1_IO_BASE	0xe0000000
#define UART2_IO_BASE	0xe0010000
#endif
#define SC0_BASE	0x40020000	/* smart card #0 */
#define IIC0_BASE	0x40030000
#ifdef __BOOTER__
#define UART0_IO_BASE	0x40040000
#else
#define UART0_IO_BASE	0xe0040000
#endif
#define SCC0_BASE	0x40040000	/* Serial 0 controller IrdA */
#define GPT0_BASE	0x40050000	/* General purpose timers */
#define GPIO0_BASE	0x40060000
#define SC1_BASE	0x40070000	/* smart card #1 */
#define SCP0_BASE	0x400C0000	/* Serial Controller Port */
#define SSP0_BASE	0x400D0000	/* Sync serial port */

#define IDE0_BASE		0xf0100000
#define REDWOOD_IDE_CTRL	0xf1100000

#define RTCFPC_IRQ	0
#define XPORT_IRQ	1
#define AUD_IRQ		2
#define AID_IRQ		3
#define DMA0		4
#define DMA1_IRQ	5
#define DMA2_IRQ	6
#define DMA3_IRQ	7
#define SC0_IRQ		8
#define IIC0_IRQ	9
#define IIR0_IRQ	10
#define GPT0_IRQ	11
#define GPT1_IRQ	12
#define SCP0_IRQ	13
#define SSP0_IRQ	14
#define GPT2_IRQ	15	/* count down timer */
#define SC1_IRQ		16
/* IRQ 17 - 19  external */
#define UART0_INT	20
#define UART1_INT	21
#define UART2_INT	22
#define XPTDMA_IRQ	23
#define DCRIDE_IRQ	24
/* IRQ 25 - 30 external */
#define IDE0_IRQ	26

#define IIC_NUMS	1
#define UART_NUMS	3
#define IIC_OWN		0x55
#define IIC_CLOCK	50

#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]

#define STD_UART_OP(num)					\
	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
		iomem_base: (u8 *)UART##num##_IO_BASE,		\
		io_type: SERIAL_IO_MEM},

#if defined(CONFIG_UART0_TTYS0)
#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
#define SERIAL_PORT_DFNS	\
	STD_UART_OP(0)		\
	STD_UART_OP(1)		\
	STD_UART_OP(2)
#endif

#if defined(CONFIG_UART0_TTYS1)
#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
#define SERIAL_PORT_DFNS	\
	STD_UART_OP(1)		\
	STD_UART_OP(0)		\
	STD_UART_OP(2)
#endif

#if defined(CONFIG_UART0_TTYS2)
#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
#define SERIAL_PORT_DFNS	\
	STD_UART_OP(2)		\
	STD_UART_OP(0)		\
	STD_UART_OP(1)
#endif

#define DCRN_BE_BASE		0x090
#define DCRN_DMA0_BASE		0x0C0
#define DCRN_DMA1_BASE		0x0C8
#define DCRN_DMA2_BASE		0x0D0
#define DCRN_DMA3_BASE		0x0D8
#define DCRNCAP_DMA_CC		1	/* have DMA chained count capability */
#define DCRN_DMASR_BASE		0x0E0
#define DCRN_PLB0_BASE		0x054
#define DCRN_PLB1_BASE		0x064
#define DCRN_POB0_BASE		0x0B0
#define DCRN_SCCR_BASE		0x120
#define DCRN_UIC0_BASE		0x040
#define DCRN_BE_BASE		0x090
#define DCRN_DMA0_BASE		0x0C0
#define DCRN_DMA1_BASE		0x0C8
#define DCRN_DMA2_BASE		0x0D0
#define DCRN_DMA3_BASE		0x0D8
#define DCRN_CIC_BASE 		0x030
#define DCRN_DMASR_BASE		0x0E0
#define DCRN_EBIMC_BASE		0x070
#define DCRN_DCRX_BASE		0x020
#define DCRN_CPMFR_BASE		0x102
#define DCRN_SCCR_BASE		0x120
#define DCRN_RTCFP_BASE		0x310

#define UIC0 DCRN_UIC0_BASE

#define IBM_CPM_IIC0	0x80000000	/* IIC 0 interface */
#define IBM_CPM_CPU	0x10000000	/* PPC405B3 clock control */
#define IBM_CPM_AUD	0x08000000	/* Audio Decoder */
#define IBM_CPM_EBIU	0x04000000	/* External Bus Interface Unit */
#define IBM_CPM_IRR	0x02000000	/* Infrared receiver */
#define IBM_CPM_DMA	0x01000000	/* DMA controller */
#define IBM_CPM_UART2	0x00200000	/* Serial Control Port */
#define IBM_CPM_UART1	0x00100000	/* Serial 1 / Infrared */
#define IBM_CPM_UART0	0x00080000	/* Serial 0 / 16550 */
#define IBM_PM_DCRIDE	0x00040000	/* DCR timeout & IDE line Mode clock */
#define IBM_CPM_SC0	0x00020000	/* Smart Card 0 */
#define IBM_CPM_VID	0x00010000	/* reserved */
#define IBM_CPM_SC1	0x00008000	/* Smart Card 0 */
#define IBM_CPM_XPT0	0x00002000	/* Transport - 54 Mhz */
#define IBM_CPM_CBS	0x00001000	/* Cross Bar Switch */
#define IBM_CPM_GPT	0x00000800	/* GPTPWM */
#define IBM_CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
#define IBM_CPM_DENC	0x00000200	/* Digital video Encoder */
#define IBM_CPM_C405T	0x00000100	/* CPU timers */
#define IBM_CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
#define IBM_CPM_UIC	0x00000040	/* Universal Interrupt Controller */
#define IBM_CPM_RTCFPC	0x00000020	/* Realtime clock and front panel */
#define IBM_CPM_SSP	0x00000010	/* Modem Serial Interface (SSP) */
#define IBM_CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
#define DFLT_IBM4xx_PM	~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA	\
			| IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T 	\
			| IBM_CPM_XPT27 | IBM_CPM_UIC)

#define DCRN_BEAR	(DCRN_BE_BASE + 0x0)	/* Bus Error Address Register */
#define DCRN_BESR	(DCRN_BE_BASE + 0x1)	/* Bus Error Syndrome Register */
/* DCRN_BESR */
#define BESR_DSES	0x80000000	/* Data-Side Error Status */
#define BESR_DMES	0x40000000	/* DMA Error Status */
#define BESR_RWS	0x20000000	/* Read/Write Status */
#define BESR_ETMASK	0x1C000000	/* Error Type */
#define ET_PROT		0
#define ET_PARITY	1
#define ET_NCFG		2
#define ET_BUSERR	4
#define ET_BUSTO	6

#define CHR1_CETE	0x00800000	/* CPU external timer enable */
#define CHR1_PCIPW	0x00008000	/* PCI Int enable/Peripheral Write enable */

#define DCRN_CICCR	(DCRN_CIC_BASE + 0x0)	/* CIC Control Register */
#define DCRN_DMAS1	(DCRN_CIC_BASE + 0x1)	/* DMA Select1 Register */
#define DCRN_DMAS2	(DCRN_CIC_BASE + 0x2)	/* DMA Select2 Register */
#define DCRN_CICVCR	(DCRN_CIC_BASE + 0x3)	/* CIC Video COntro Register */
#define DCRN_CICSEL3	(DCRN_CIC_BASE + 0x5)	/* CIC Select 3 Register */
#define DCRN_SGPO	(DCRN_CIC_BASE + 0x6)	/* CIC GPIO Output Register */
#define DCRN_SGPOD	(DCRN_CIC_BASE + 0x7)	/* CIC GPIO OD Register */
#define DCRN_SGPTC	(DCRN_CIC_BASE + 0x8)	/* CIC GPIO Tristate Ctrl Reg */
#define DCRN_SGPI	(DCRN_CIC_BASE + 0x9)	/* CIC GPIO Input Reg */

#define DCRN_DCRXICR	(DCRN_DCRX_BASE + 0x0)	/* Internal Control Register */
#define DCRN_DCRXISR	(DCRN_DCRX_BASE + 0x1)	/* Internal Status Register */
#define DCRN_DCRXECR	(DCRN_DCRX_BASE + 0x2)	/* External Control Register */
#define DCRN_DCRXESR	(DCRN_DCRX_BASE + 0x3)	/* External Status Register */
#define DCRN_DCRXTAR	(DCRN_DCRX_BASE + 0x4)	/* Target Address Register */
#define DCRN_DCRXTDR	(DCRN_DCRX_BASE + 0x5)	/* Target Data Register */
#define DCRN_DCRXIGR	(DCRN_DCRX_BASE + 0x6)	/* Interrupt Generation Register */
#define DCRN_DCRXBCR	(DCRN_DCRX_BASE + 0x7)	/* Line Buffer Control Register */

#define DCRN_BRCRH0	(DCRN_EBIMC_BASE + 0x0)	/* Bus Region Config High 0 */
#define DCRN_BRCRH1	(DCRN_EBIMC_BASE + 0x1)	/* Bus Region Config High 1 */
#define DCRN_BRCRH2	(DCRN_EBIMC_BASE + 0x2)	/* Bus Region Config High 2 */
#define DCRN_BRCRH3	(DCRN_EBIMC_BASE + 0x3)	/* Bus Region Config High 3 */
#define DCRN_BRCRH4	(DCRN_EBIMC_BASE + 0x4)	/* Bus Region Config High 4 */
#define DCRN_BRCRH5	(DCRN_EBIMC_BASE + 0x5)	/* Bus Region Config High 5 */
#define DCRN_BRCRH6	(DCRN_EBIMC_BASE + 0x6)	/* Bus Region Config High 6 */
#define DCRN_BRCRH7	(DCRN_EBIMC_BASE + 0x7)	/* Bus Region Config High 7 */
#define DCRN_BRCR0	(DCRN_EBIMC_BASE + 0x10)	/* BRC 0 */
#define DCRN_BRCR1	(DCRN_EBIMC_BASE + 0x11)	/* BRC 1 */
#define DCRN_BRCR2	(DCRN_EBIMC_BASE + 0x12)	/* BRC 2 */
#define DCRN_BRCR3	(DCRN_EBIMC_BASE + 0x13)	/* BRC 3 */
#define DCRN_BRCR4	(DCRN_EBIMC_BASE + 0x14)	/* BRC 4 */
#define DCRN_BRCR5	(DCRN_EBIMC_BASE + 0x15)	/* BRC 5 */
#define DCRN_BRCR6	(DCRN_EBIMC_BASE + 0x16)	/* BRC 6 */
#define DCRN_BRCR7	(DCRN_EBIMC_BASE + 0x17)	/* BRC 7 */
#define DCRN_BEAR0	(DCRN_EBIMC_BASE + 0x20)	/* Bus Error Address Register */
#define DCRN_BESR0	(DCRN_EBIMC_BASE + 0x21)	/* Bus Error Status Register */
#define DCRN_BIUCR	(DCRN_EBIMC_BASE + 0x2A)	/* Bus Interfac Unit Ctrl Reg */

#define DCRN_RTC_FPC0_CNTL 	(DCRN_RTCFP_BASE + 0x00)	/* RTC cntl */
#define DCRN_RTC_FPC0_INT 	(DCRN_RTCFP_BASE + 0x01)	/* RTC Interrupt */
#define DCRN_RTC_FPC0_TIME 	(DCRN_RTCFP_BASE + 0x02)	/* RTC time reg */
#define DCRN_RTC_FPC0_ALRM 	(DCRN_RTCFP_BASE + 0x03)	/* RTC Alarm reg */
#define DCRN_RTC_FPC0_D1 	(DCRN_RTCFP_BASE + 0x04)	/* LED Data 1 */
#define DCRN_RTC_FPC0_D2 	(DCRN_RTCFP_BASE + 0x05)	/* LED Data 2 */
#define DCRN_RTC_FPC0_D3 	(DCRN_RTCFP_BASE + 0x06)	/* LED Data 3 */
#define DCRN_RTC_FPC0_D4 	(DCRN_RTCFP_BASE + 0x07)	/* LED Data 4 */
#define DCRN_RTC_FPC0_D5 	(DCRN_RTCFP_BASE + 0x08)	/* LED Data 5 */
#define DCRN_RTC_FPC0_FCNTL 	(DCRN_RTCFP_BASE + 0x09)	/* LED control */
#define DCRN_RTC_FPC0_BRT 	(DCRN_RTCFP_BASE + 0x0A)	/* Brightness cntl */

#include <asm/ibm405.h>

#endif				/* __ASM_IBMSTBX25_H__ */
#endif				/* __KERNEL__ */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Author: Armin Kuster <akuster@mvista.com>
	3	*
	4	* 2002 (c) MontaVista, Software, Inc. This file is licensed under
	5	* the terms of the GNU General Public License version 2. This program
	6	* is licensed "as is" without any warranty of any kind, whether express
	7	* or implied.
	8	*/
	9
	10	#ifdef __KERNEL__
	11	#ifndef __ASM_IBMSTBX25_H__
	12	#define __ASM_IBMSTBX25_H__
	13
	14	#include <linux/config.h>
	15
	16	/* serial port defines */
	17	#define STBx25xx_IO_BASE ((uint)0xe0000000)
	18	#define PPC4xx_ONB_IO_PADDR STBx25xx_IO_BASE
	19	#define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000)
	20	#define PPC4xx_ONB_IO_SIZE ((uint)14641024)
	21
	22	/*
	23	* map STBxxxx internal i/o address (0x400x00xx) to an address
	24	* which is below the 2GB limit...
	25	*
	26	* 4000 000x uart1 -> 0xe000 000x
	27	* 4001 00xx uart2
	28	* 4002 00xx smart card
	29	* 4003 000x iic
	30	* 4004 000x uart0
	31	* 4005 0xxx timer
	32	* 4006 00xx gpio
	33	* 4007 00xx smart card
	34	* 400b 000x iic
	35	* 400c 000x scp
	36	* 400d 000x modem
	37	* 400e 000x uart2
	38	*/
	39	#define STBx25xx_MAP_IO_ADDR(a) (((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000))
	40
	41	#define RS_TABLE_SIZE 3
	42
	43	#define OPB_BASE_START 0x40000000
	44	#define EBIU_BASE_START 0xF0100000
	45	#define DCR_BASE_START 0x0000
	46
	47	#ifdef __BOOTER__
	48	#define UART1_IO_BASE 0x40000000
	49	#define UART2_IO_BASE 0x40010000
	50	#else
	51	#define UART1_IO_BASE 0xe0000000
	52	#define UART2_IO_BASE 0xe0010000
	53	#endif
	54	#define SC0_BASE 0x40020000 /* smart card #0 */
	55	#define IIC0_BASE 0x40030000
	56	#ifdef __BOOTER__
	57	#define UART0_IO_BASE 0x40040000
	58	#else
	59	#define UART0_IO_BASE 0xe0040000
	60	#endif
	61	#define SCC0_BASE 0x40040000 /* Serial 0 controller IrdA */
	62	#define GPT0_BASE 0x40050000 /* General purpose timers */
	63	#define GPIO0_BASE 0x40060000
	64	#define SC1_BASE 0x40070000 /* smart card #1 */
	65	#define SCP0_BASE 0x400C0000 /* Serial Controller Port */
66	#define SSP0_BASE 0x400D0000 /* Sync serial port */
67
68	#define IDE0_BASE 0xf0100000
69	#define REDWOOD_IDE_CTRL 0xf1100000
70
71	#define RTCFPC_IRQ 0
72	#define XPORT_IRQ 1
73	#define AUD_IRQ 2
74	#define AID_IRQ 3
75	#define DMA0 4
76	#define DMA1_IRQ 5
77	#define DMA2_IRQ 6
78	#define DMA3_IRQ 7
79	#define SC0_IRQ 8
80	#define IIC0_IRQ 9
81	#define IIR0_IRQ 10
82	#define GPT0_IRQ 11
83	#define GPT1_IRQ 12
84	#define SCP0_IRQ 13
85	#define SSP0_IRQ 14
86	#define GPT2_IRQ 15 /* count down timer */
87	#define SC1_IRQ 16
88	/* IRQ 17 - 19 external */
89	#define UART0_INT 20
90	#define UART1_INT 21
91	#define UART2_INT 22
92	#define XPTDMA_IRQ 23
93	#define DCRIDE_IRQ 24
94	/* IRQ 25 - 30 external */
95	#define IDE0_IRQ 26
96
97	#define IIC_NUMS 1
98	#define UART_NUMS 3
99	#define IIC_OWN 0x55
100	#define IIC_CLOCK 50
101
102	#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
103
104	#define STD_UART_OP(num) \
105	{ 0, BASE_BAUD, 0, UART##num##_INT, \
106	(ASYNC_BOOT_AUTOCONF \| ASYNC_SKIP_TEST), \
107	iomem_base: (u8 *)UART##num##_IO_BASE, \
108	io_type: SERIAL_IO_MEM},
109
110	#if defined(CONFIG_UART0_TTYS0)
111	#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
112	#define SERIAL_PORT_DFNS \
113	STD_UART_OP(0) \
114	STD_UART_OP(1) \
115	STD_UART_OP(2)
116	#endif
117
118	#if defined(CONFIG_UART0_TTYS1)
119	#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
120	#define SERIAL_PORT_DFNS \
121	STD_UART_OP(1) \
122	STD_UART_OP(0) \
123	STD_UART_OP(2)
124	#endif
125
126	#if defined(CONFIG_UART0_TTYS2)
127	#define SERIAL_DEBUG_IO_BASE UART2_IO_BASE
128	#define SERIAL_PORT_DFNS \
129	STD_UART_OP(2) \
130	STD_UART_OP(0) \
131	STD_UART_OP(1)
132	#endif
133
134	#define DCRN_BE_BASE 0x090
135	#define DCRN_DMA0_BASE 0x0C0
136	#define DCRN_DMA1_BASE 0x0C8
137	#define DCRN_DMA2_BASE 0x0D0
138	#define DCRN_DMA3_BASE 0x0D8
139	#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
140	#define DCRN_DMASR_BASE 0x0E0
141	#define DCRN_PLB0_BASE 0x054
142	#define DCRN_PLB1_BASE 0x064
143	#define DCRN_POB0_BASE 0x0B0
144	#define DCRN_SCCR_BASE 0x120
145	#define DCRN_UIC0_BASE 0x040
146	#define DCRN_BE_BASE 0x090
147	#define DCRN_DMA0_BASE 0x0C0
148	#define DCRN_DMA1_BASE 0x0C8
149	#define DCRN_DMA2_BASE 0x0D0
150	#define DCRN_DMA3_BASE 0x0D8
151	#define DCRN_CIC_BASE 0x030
152	#define DCRN_DMASR_BASE 0x0E0
153	#define DCRN_EBIMC_BASE 0x070
154	#define DCRN_DCRX_BASE 0x020
155	#define DCRN_CPMFR_BASE 0x102
156	#define DCRN_SCCR_BASE 0x120
157	#define DCRN_RTCFP_BASE 0x310
158
159	#define UIC0 DCRN_UIC0_BASE
160
161	#define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */
162	#define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */
163	#define IBM_CPM_AUD 0x08000000 /* Audio Decoder */
164	#define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */
165	#define IBM_CPM_IRR 0x02000000 /* Infrared receiver */
166	#define IBM_CPM_DMA 0x01000000 /* DMA controller */
167	#define IBM_CPM_UART2 0x00200000 /* Serial Control Port */
168	#define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */
169	#define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */
170	#define IBM_PM_DCRIDE 0x00040000 /* DCR timeout & IDE line Mode clock */
171	#define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */
172	#define IBM_CPM_VID 0x00010000 /* reserved */
173	#define IBM_CPM_SC1 0x00008000 /* Smart Card 0 */
174	#define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */
175	#define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */
176	#define IBM_CPM_GPT 0x00000800 /* GPTPWM */
177	#define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */
178	#define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */
179	#define IBM_CPM_C405T 0x00000100 /* CPU timers */
180	#define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */
181	#define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */
182	#define IBM_CPM_RTCFPC 0x00000020 /* Realtime clock and front panel */
183	#define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */
184	#define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */
185	#define DFLT_IBM4xx_PM ~(IBM_CPM_CPU \| IBM_CPM_EBIU \| IBM_CPM_DMA \
186	\| IBM_CPM_CBS \| IBM_CPM_XPT0 \| IBM_CPM_C405T \
187	\| IBM_CPM_XPT27 \| IBM_CPM_UIC)
188
189	#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
190	#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
191	/* DCRN_BESR */
192	#define BESR_DSES 0x80000000 /* Data-Side Error Status */
193	#define BESR_DMES 0x40000000 /* DMA Error Status */
194	#define BESR_RWS 0x20000000 /* Read/Write Status */
195	#define BESR_ETMASK 0x1C000000 /* Error Type */
196	#define ET_PROT 0
197	#define ET_PARITY 1
198	#define ET_NCFG 2
199	#define ET_BUSERR 4
200	#define ET_BUSTO 6
201
202	#define CHR1_CETE 0x00800000 /* CPU external timer enable */
203	#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
204
205	#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
206	#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
207	#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
208	#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
209	#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
210	#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
211	#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
212	#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
213	#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
214
215	#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
216	#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
217	#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
218	#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
219	#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
220	#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
221	#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
222	#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
223
224	#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
225	#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
226	#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
227	#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
228	#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
229	#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
230	#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
231	#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
232	#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */
233	#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */
234	#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */
235	#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */
236	#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */
237	#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */
238	#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */
239	#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */
240	#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */
241	#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */
242	#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */
243
244	#define DCRN_RTC_FPC0_CNTL (DCRN_RTCFP_BASE + 0x00) /* RTC cntl */
245	#define DCRN_RTC_FPC0_INT (DCRN_RTCFP_BASE + 0x01) /* RTC Interrupt */
246	#define DCRN_RTC_FPC0_TIME (DCRN_RTCFP_BASE + 0x02) /* RTC time reg */
247	#define DCRN_RTC_FPC0_ALRM (DCRN_RTCFP_BASE + 0x03) /* RTC Alarm reg */
248	#define DCRN_RTC_FPC0_D1 (DCRN_RTCFP_BASE + 0x04) /* LED Data 1 */
249	#define DCRN_RTC_FPC0_D2 (DCRN_RTCFP_BASE + 0x05) /* LED Data 2 */
250	#define DCRN_RTC_FPC0_D3 (DCRN_RTCFP_BASE + 0x06) /* LED Data 3 */
251	#define DCRN_RTC_FPC0_D4 (DCRN_RTCFP_BASE + 0x07) /* LED Data 4 */
252	#define DCRN_RTC_FPC0_D5 (DCRN_RTCFP_BASE + 0x08) /* LED Data 5 */
253	#define DCRN_RTC_FPC0_FCNTL (DCRN_RTCFP_BASE + 0x09) /* LED control */
254	#define DCRN_RTC_FPC0_BRT (DCRN_RTCFP_BASE + 0x0A) /* Brightness cntl */
255
256	#include <asm/ibm405.h>
257
258	#endif /* __ASM_IBMSTBX25_H__ */
259	#endif /* __KERNEL__ */