Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Luan board specific routines |
3 | * | |
4 | * Matt Porter <mporter@kernel.crashing.org> | |
5 | * | |
6 | * Copyright 2004-2005 MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/config.h> | |
15 | #include <linux/stddef.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/reboot.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/kdev_t.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/major.h> | |
24 | #include <linux/blkdev.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/ide.h> | |
28 | #include <linux/initrd.h> | |
1da177e4 LT |
29 | #include <linux/seq_file.h> |
30 | #include <linux/root_dev.h> | |
31 | #include <linux/tty.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_core.h> | |
34 | ||
35 | #include <asm/system.h> | |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/page.h> | |
38 | #include <asm/dma.h> | |
39 | #include <asm/io.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/ocp.h> | |
42 | #include <asm/pci-bridge.h> | |
43 | #include <asm/time.h> | |
44 | #include <asm/todc.h> | |
45 | #include <asm/bootinfo.h> | |
46 | #include <asm/ppc4xx_pic.h> | |
47 | #include <asm/ppcboot.h> | |
48 | ||
49 | #include <syslib/ibm44x_common.h> | |
50 | #include <syslib/ibm440gx_common.h> | |
51 | #include <syslib/ibm440sp_common.h> | |
52 | ||
d5f7b06b | 53 | extern bd_t __res; |
1da177e4 LT |
54 | |
55 | static struct ibm44x_clocks clocks __initdata; | |
56 | ||
57 | static void __init | |
58 | luan_calibrate_decr(void) | |
59 | { | |
60 | unsigned int freq; | |
61 | ||
62 | if (mfspr(SPRN_CCR1) & CCR1_TCS) | |
63 | freq = LUAN_TMR_CLK; | |
64 | else | |
65 | freq = clocks.cpu; | |
66 | ||
67 | ibm44x_calibrate_decr(freq); | |
68 | } | |
69 | ||
70 | static int | |
71 | luan_show_cpuinfo(struct seq_file *m) | |
72 | { | |
73 | seq_printf(m, "vendor\t\t: IBM\n"); | |
74 | seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n"); | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | static inline int | |
80 | luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | |
81 | { | |
82 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); | |
83 | ||
84 | /* PCIX0 in adapter mode, no host interrupt routing */ | |
85 | ||
86 | /* PCIX1 */ | |
87 | if (hose->index == 0) { | |
88 | static char pci_irq_table[][4] = | |
89 | /* | |
90 | * PCI IDSEL/INTPIN->INTLINE | |
91 | * A B C D | |
92 | */ | |
93 | { | |
94 | { 49, 49, 49, 49 }, /* IDSEL 1 - PCIX1 Slot 0 */ | |
95 | { 49, 49, 49, 49 }, /* IDSEL 2 - PCIX1 Slot 1 */ | |
96 | { 49, 49, 49, 49 }, /* IDSEL 3 - PCIX1 Slot 2 */ | |
97 | { 49, 49, 49, 49 }, /* IDSEL 4 - PCIX1 Slot 3 */ | |
98 | }; | |
99 | const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; | |
100 | return PCI_IRQ_TABLE_LOOKUP; | |
101 | /* PCIX2 */ | |
102 | } else if (hose->index == 1) { | |
103 | static char pci_irq_table[][4] = | |
104 | /* | |
105 | * PCI IDSEL/INTPIN->INTLINE | |
106 | * A B C D | |
107 | */ | |
108 | { | |
109 | { 50, 50, 50, 50 }, /* IDSEL 1 - PCIX2 Slot 0 */ | |
110 | { 50, 50, 50, 50 }, /* IDSEL 2 - PCIX2 Slot 1 */ | |
111 | { 50, 50, 50, 50 }, /* IDSEL 3 - PCIX2 Slot 2 */ | |
112 | { 50, 50, 50, 50 }, /* IDSEL 4 - PCIX2 Slot 3 */ | |
113 | }; | |
114 | const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; | |
115 | return PCI_IRQ_TABLE_LOOKUP; | |
116 | } | |
117 | return -1; | |
118 | } | |
119 | ||
120 | static void __init luan_set_emacdata(void) | |
121 | { | |
122 | struct ocp_def *def; | |
123 | struct ocp_func_emac_data *emacdata; | |
124 | ||
125 | /* Set phy_map, phy_mode, and mac_addr for the EMAC */ | |
126 | def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); | |
127 | emacdata = def->additions; | |
128 | emacdata->phy_map = 0x00000001; /* Skip 0x00 */ | |
129 | emacdata->phy_mode = PHY_MODE_GMII; | |
130 | memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); | |
131 | } | |
132 | ||
133 | #define PCIX_READW(offset) \ | |
134 | (readw((void *)((u32)pcix_reg_base+offset))) | |
135 | ||
136 | #define PCIX_WRITEW(value, offset) \ | |
137 | (writew(value, (void *)((u32)pcix_reg_base+offset))) | |
138 | ||
139 | #define PCIX_WRITEL(value, offset) \ | |
140 | (writel(value, (void *)((u32)pcix_reg_base+offset))) | |
141 | ||
142 | static void __init | |
143 | luan_setup_pcix(void) | |
144 | { | |
145 | int i; | |
146 | void *pcix_reg_base; | |
147 | ||
148 | for (i=0;i<3;i++) { | |
149 | pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE); | |
150 | ||
151 | /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ | |
152 | PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); | |
153 | ||
154 | /* Disable all windows */ | |
155 | PCIX_WRITEL(0, PCIX0_POM0SA); | |
156 | PCIX_WRITEL(0, PCIX0_POM1SA); | |
157 | PCIX_WRITEL(0, PCIX0_POM2SA); | |
158 | PCIX_WRITEL(0, PCIX0_PIM0SA); | |
159 | PCIX_WRITEL(0, PCIX0_PIM0SAH); | |
160 | PCIX_WRITEL(0, PCIX0_PIM1SA); | |
161 | PCIX_WRITEL(0, PCIX0_PIM2SA); | |
162 | PCIX_WRITEL(0, PCIX0_PIM2SAH); | |
163 | ||
164 | /* | |
165 | * Setup 512MB PLB->PCI outbound mem window | |
166 | * (a_n000_0000->0_n000_0000) | |
167 | * */ | |
168 | PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH); | |
169 | PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL); | |
170 | PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); | |
171 | PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL); | |
172 | PCIX_WRITEL(0xe0000001, PCIX0_POM0SA); | |
173 | ||
174 | /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ | |
175 | PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); | |
176 | PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); | |
177 | PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); | |
178 | PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH); | |
179 | ||
180 | iounmap(pcix_reg_base); | |
181 | } | |
182 | ||
183 | eieio(); | |
184 | } | |
185 | ||
186 | static void __init | |
187 | luan_setup_hose(struct pci_controller *hose, | |
188 | int lower_mem, | |
189 | int upper_mem, | |
190 | int cfga, | |
191 | int cfgd, | |
192 | u64 pcix_io_base) | |
193 | { | |
194 | char name[20]; | |
195 | ||
196 | sprintf(name, "PCIX%d host bridge", hose->index); | |
197 | ||
198 | hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET; | |
199 | ||
200 | pci_init_resource(&hose->io_resource, | |
201 | LUAN_PCIX_LOWER_IO, | |
202 | LUAN_PCIX_UPPER_IO, | |
203 | IORESOURCE_IO, | |
204 | name); | |
205 | ||
206 | pci_init_resource(&hose->mem_resources[0], | |
207 | lower_mem, | |
208 | upper_mem, | |
209 | IORESOURCE_MEM, | |
210 | name); | |
211 | ||
212 | hose->io_space.start = LUAN_PCIX_LOWER_IO; | |
213 | hose->io_space.end = LUAN_PCIX_UPPER_IO; | |
214 | hose->mem_space.start = lower_mem; | |
215 | hose->mem_space.end = upper_mem; | |
92a11f9e AV |
216 | hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE); |
217 | isa_io_base = (unsigned long) hose->io_base_virt; | |
1da177e4 LT |
218 | |
219 | setup_indirect_pci(hose, cfga, cfgd); | |
220 | hose->set_cfg_type = 1; | |
221 | } | |
222 | ||
223 | static void __init | |
224 | luan_setup_hoses(void) | |
225 | { | |
226 | struct pci_controller *hose1, *hose2; | |
227 | ||
228 | /* Configure windows on the PCI-X host bridge */ | |
229 | luan_setup_pcix(); | |
230 | ||
231 | /* Allocate hoses for PCIX1 and PCIX2 */ | |
232 | hose1 = pcibios_alloc_controller(); | |
233 | hose2 = pcibios_alloc_controller(); | |
234 | if (!hose1 || !hose2) | |
235 | return; | |
236 | ||
237 | /* Setup PCIX1 */ | |
238 | hose1->first_busno = 0; | |
239 | hose1->last_busno = 0xff; | |
240 | ||
241 | luan_setup_hose(hose1, | |
242 | LUAN_PCIX1_LOWER_MEM, | |
243 | LUAN_PCIX1_UPPER_MEM, | |
244 | PCIX1_CFGA, | |
245 | PCIX1_CFGD, | |
246 | PCIX1_IO_BASE); | |
247 | ||
248 | hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); | |
249 | ||
250 | /* Setup PCIX2 */ | |
251 | hose2->first_busno = hose1->last_busno + 1; | |
252 | hose2->last_busno = 0xff; | |
253 | ||
254 | luan_setup_hose(hose2, | |
255 | LUAN_PCIX2_LOWER_MEM, | |
256 | LUAN_PCIX2_UPPER_MEM, | |
257 | PCIX2_CFGA, | |
258 | PCIX2_CFGD, | |
259 | PCIX2_IO_BASE); | |
260 | ||
261 | hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); | |
262 | ||
263 | ppc_md.pci_swizzle = common_swizzle; | |
264 | ppc_md.pci_map_irq = luan_map_irq; | |
265 | } | |
266 | ||
267 | TODC_ALLOC(); | |
268 | ||
269 | static void __init | |
270 | luan_early_serial_map(void) | |
271 | { | |
272 | struct uart_port port; | |
273 | ||
274 | /* Setup ioremapped serial port access */ | |
275 | memset(&port, 0, sizeof(port)); | |
276 | port.membase = ioremap64(PPC440SP_UART0_ADDR, 8); | |
277 | port.irq = UART0_INT; | |
278 | port.uartclk = clocks.uart0; | |
279 | port.regshift = 0; | |
9b4a1617 | 280 | port.iotype = UPIO_MEM; |
59a675b2 | 281 | port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; |
1da177e4 LT |
282 | port.line = 0; |
283 | ||
284 | if (early_serial_setup(&port) != 0) { | |
285 | printk("Early serial init of port 0 failed\n"); | |
286 | } | |
287 | ||
288 | port.membase = ioremap64(PPC440SP_UART1_ADDR, 8); | |
289 | port.irq = UART1_INT; | |
290 | port.uartclk = clocks.uart1; | |
291 | port.line = 1; | |
292 | ||
293 | if (early_serial_setup(&port) != 0) { | |
294 | printk("Early serial init of port 1 failed\n"); | |
295 | } | |
296 | ||
297 | port.membase = ioremap64(PPC440SP_UART2_ADDR, 8); | |
298 | port.irq = UART2_INT; | |
299 | port.uartclk = BASE_BAUD; | |
300 | port.line = 2; | |
301 | ||
302 | if (early_serial_setup(&port) != 0) { | |
303 | printk("Early serial init of port 2 failed\n"); | |
304 | } | |
305 | } | |
306 | ||
307 | static void __init | |
308 | luan_setup_arch(void) | |
309 | { | |
310 | luan_set_emacdata(); | |
311 | ||
312 | #if !defined(CONFIG_BDI_SWITCH) | |
313 | /* | |
314 | * The Abatron BDI JTAG debugger does not tolerate others | |
315 | * mucking with the debug registers. | |
316 | */ | |
317 | mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); | |
318 | #endif | |
319 | ||
320 | /* | |
321 | * Determine various clocks. | |
322 | * To be completely correct we should get SysClk | |
323 | * from FPGA, because it can be changed by on-board switches | |
324 | * --ebs | |
325 | */ | |
326 | /* 440GX and 440SP clocking is the same -mdp */ | |
327 | ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); | |
328 | ocp_sys_info.opb_bus_freq = clocks.opb; | |
329 | ||
330 | /* init to some ~sane value until calibrate_delay() runs */ | |
331 | loops_per_jiffy = 50000000/HZ; | |
332 | ||
333 | /* Setup PCIXn host bridges */ | |
334 | luan_setup_hoses(); | |
335 | ||
336 | #ifdef CONFIG_BLK_DEV_INITRD | |
337 | if (initrd_start) | |
338 | ROOT_DEV = Root_RAM0; | |
339 | else | |
340 | #endif | |
341 | #ifdef CONFIG_ROOT_NFS | |
342 | ROOT_DEV = Root_NFS; | |
343 | #else | |
344 | ROOT_DEV = Root_HDA1; | |
345 | #endif | |
346 | ||
347 | luan_early_serial_map(); | |
348 | ||
349 | /* Identify the system */ | |
350 | printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n"); | |
351 | } | |
352 | ||
353 | void __init platform_init(unsigned long r3, unsigned long r4, | |
354 | unsigned long r5, unsigned long r6, unsigned long r7) | |
355 | { | |
d5f7b06b | 356 | ibm44x_platform_init(r3, r4, r5, r6, r7); |
1da177e4 LT |
357 | |
358 | ppc_md.setup_arch = luan_setup_arch; | |
359 | ppc_md.show_cpuinfo = luan_show_cpuinfo; | |
360 | ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory; | |
361 | ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ | |
362 | ||
363 | ppc_md.calibrate_decr = luan_calibrate_decr; | |
364 | #ifdef CONFIG_KGDB | |
365 | ppc_md.early_serial_map = luan_early_serial_map; | |
366 | #endif | |
367 | } |