projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 1da177e4 LT |
2 | * Ocotea board definitions |
| 3 | * | |
| 4 | * Matt Porter <mporter@kernel.crashing.org> | |
| 5 | * | |
| 6 | * Copyright 2003-2005 MontaVista Software Inc. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify it | |
| 9 | * under the terms of the GNU General Public License as published by the | |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 11 | * option) any later version. | |
| 12 | * | |
| 13 | */ | |
| 14 | ||
| 15 | #ifdef __KERNEL__ | |
| 16 | #ifndef __ASM_OCOTEA_H__ | |
| 17 | #define __ASM_OCOTEA_H__ | |
| 18 | ||
| 19 | #include <linux/config.h> | |
| 20 | #include <platforms/4xx/ibm440gx.h> | |
| 21 | ||
| 22 | /* F/W TLB mapping used in bootloader glue to reset EMAC */ | |
| 23 | #define PPC44x_EMAC0_MR0 0xe0000800 | |
| 24 | ||
| 25 | /* Location of MAC addresses in PIBS image */ | |
| 26 | #define PIBS_FLASH_BASE 0xfff00000 | |
| 27 | #define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xb0500) | |
| 28 | #define PIBS_MAC_SIZE 0x200 | |
| 29 | #define PIBS_MAC_OFFSET 0x100 | |
| 30 | ||
| 31 | /* External timer clock frequency */ | |
| 32 | #define OCOTEA_TMR_CLK 25000000 | |
| 33 | ||
| 34 | /* RTC/NVRAM location */ | |
| 35 | #define OCOTEA_RTC_ADDR 0x0000000148000000ULL | |
| 36 | #define OCOTEA_RTC_SIZE 0x2000 | |
| 37 | ||
| 38 | /* Flash */ | |
| 39 | #define OCOTEA_FPGA_REG_0 0x0000000148300000ULL | |
| 40 | #define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40) | |
| 41 | #define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL | |
| 42 | #define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL | |
| 43 | #define OCOTEA_SMALL_FLASH_SIZE 0x100000 | |
| 44 | #define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL | |
| 45 | #define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL | |
| 46 | #define OCOTEA_LARGE_FLASH_SIZE 0x400000 | |
| 47 | ||
| 48 | /* FPGA_REG_3 (Ethernet Groups) */ | |
| 49 | #define OCOTEA_FPGA_REG_3 0x0000000148300003ULL | |
| 50 | ||
| 51 | /* | |
| 52 | * Serial port defines | |
| 53 | */ | |
| 54 | #define RS_TABLE_SIZE 2 | |
| 55 | ||
| 5ce17b18 ES |
56 | #if defined(__BOOTER__) |
| 57 | /* OpenBIOS defined UART mappings, used by bootloader shim */ | |
| 1da177e4 LT |
58 | #define UART0_IO_BASE 0xE0000200 |
| 59 | #define UART1_IO_BASE 0xE0000300 | |
| 5ce17b18 ES |
60 | #else |
| 61 | /* head_44x.S created UART mapping, used before early_serial_setup. | |
| 62 | * We cannot use default OpenBIOS UART mappings because they | |
| 63 | * don't work for configurations with more than 512M RAM. --ebs | |
| 64 | */ | |
| 65 | #define UART0_IO_BASE 0xF0000200 | |
| 66 | #define UART1_IO_BASE 0xF0000300 | |
| 67 | #endif | |
| 1da177e4 LT |
68 | |
| 69 | #define BASE_BAUD 11059200/16 | |
| 70 | #define STD_UART_OP(num) \ | |
| 71 | { 0, BASE_BAUD, 0, UART##num##_INT, \ | |
| 72 | (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ | |
| 5ce17b18 | 73 | iomem_base: (void*)UART##num##_IO_BASE, \ |
| 1da177e4 LT |
74 | io_type: SERIAL_IO_MEM}, |
| 75 | ||
| 76 | #define SERIAL_PORT_DFNS \ | |
| 77 | STD_UART_OP(0) \ | |
| 78 | STD_UART_OP(1) | |
| 79 | ||
| 80 | /* PCI support */ | |
| 81 | #define OCOTEA_PCI_LOWER_IO 0x00000000 | |
| 82 | #define OCOTEA_PCI_UPPER_IO 0x0000ffff | |
| 83 | #define OCOTEA_PCI_LOWER_MEM 0x80000000 | |
| 84 | #define OCOTEA_PCI_UPPER_MEM 0xffffefff | |
| 85 | ||
| 86 | #define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL | |
| 87 | #define OCOTEA_PCI_CFGA_PLB32 0x0ec00000 | |
| 88 | #define OCOTEA_PCI_CFGD_PLB32 0x0ec00004 | |
| 89 | ||
| 90 | #define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL | |
| 91 | #define OCOTEA_PCI_IO_SIZE 0x00010000 | |
| 92 | #define OCOTEA_PCI_MEM_OFFSET 0x00000000 | |
| 93 | ||
| 94 | #endif /* __ASM_OCOTEA_H__ */ | |
| 95 | #endif /* __KERNEL__ */ |