projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b0f7b8bc | 1 | /* |
| b0f7b8bc RD |
2 | * PPC440SPe definitions |
| 3 | * | |
| 4 | * Roland Dreier <rolandd@cisco.com> | |
| 5 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
| 6 | * | |
| 7 | * Matt Porter <mporter@kernel.crashing.org> | |
| 8 | * Copyright 2004-2005 MontaVista Software, Inc. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify it | |
| 11 | * under the terms of the GNU General Public License as published by the | |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 13 | * option) any later version. | |
| 14 | */ | |
| 15 | ||
| 16 | #ifdef __KERNEL__ | |
| 17 | #ifndef __PPC_PLATFORMS_PPC440SPE_H | |
| 18 | #define __PPC_PLATFORMS_PPC440SPE_H | |
| 19 | ||
| 20 | #include <linux/config.h> | |
| 21 | ||
| 22 | #include <asm/ibm44x.h> | |
| 23 | ||
| 24 | /* UART */ | |
| 25 | #define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL | |
| 26 | #define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL | |
| 27 | #define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL | |
| 28 | #define UART0_INT 0 | |
| 29 | #define UART1_INT 1 | |
| 30 | #define UART2_INT 37 | |
| 31 | ||
| 32 | /* Clock and Power Management */ | |
| 33 | #define IBM_CPM_IIC0 0x80000000 /* IIC interface */ | |
| 34 | #define IBM_CPM_IIC1 0x40000000 /* IIC interface */ | |
| 35 | #define IBM_CPM_PCI 0x20000000 /* PCI bridge */ | |
| 36 | #define IBM_CPM_CPU 0x02000000 /* processor core */ | |
| 37 | #define IBM_CPM_DMA 0x01000000 /* DMA controller */ | |
| 38 | #define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ | |
| 39 | #define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ | |
| 40 | #define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ | |
| 41 | #define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ | |
| 42 | #define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ | |
| 43 | #define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ | |
| 44 | #define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ | |
| 45 | #define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ | |
| 46 | #define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ | |
| 47 | #define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ | |
| 48 | #define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ | |
| 49 | #define IBM_CPM_UART0 0x00000200 /* serial port 0 */ | |
| 50 | #define IBM_CPM_UART1 0x00000100 /* serial port 1 */ | |
| 51 | #define IBM_CPM_UART2 0x00000100 /* serial port 1 */ | |
| 52 | #define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ | |
| 53 | #define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ | |
| 54 | #define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ | |
| 55 | ||
| 56 | #define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ | |
| 57 | | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ | |
| 58 | | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ | |
| 59 | | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ | |
| 60 | | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ | |
| 61 | | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ | |
| 62 | | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) | |
| 63 | #endif /* __PPC_PLATFORMS_PPC440SP_H */ | |
| 64 | #endif /* __KERNEL__ */ |