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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * STx GP3 board definitions |
3 | * | |
4 | * Dan Malek (dan@embeddededge.com) | |
5 | * Copyright 2004 Embedded Edge, LLC | |
6 | * | |
7 | * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org> | |
8 | * Copyright 2004-2005 MontaVista Software, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef __MACH_STX_GP3_H | |
18 | #define __MACH_STX_GP3_H | |
19 | ||
20 | #include <linux/config.h> | |
21 | #include <linux/init.h> | |
1da177e4 LT |
22 | #include <asm/ppcboot.h> |
23 | ||
24 | #define BOARD_CCSRBAR ((uint)0xe0000000) | |
25 | #define CCSRBAR_SIZE ((uint)1024*1024) | |
26 | ||
27 | #define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET) | |
28 | ||
29 | #define BCSR_ADDR ((uint)0xfc000000) | |
30 | #define BCSR_SIZE ((uint)(16 * 1024)) | |
31 | ||
32 | #define BCSR_TSEC1_RESET 0x00000080 | |
33 | #define BCSR_TSEC2_RESET 0x00000040 | |
34 | #define BCSR_LED1 0x00000008 | |
35 | #define BCSR_LED2 0x00000004 | |
36 | #define BCSR_LED3 0x00000002 | |
37 | #define BCSR_LED4 0x00000001 | |
38 | ||
39 | extern void mpc85xx_setup_hose(void) __init; | |
40 | extern void mpc85xx_restart(char *cmd); | |
41 | extern void mpc85xx_power_off(void); | |
42 | extern void mpc85xx_halt(void); | |
1da177e4 LT |
43 | extern void mpc85xx_init_IRQ(void) __init; |
44 | extern unsigned long mpc85xx_find_end_of_memory(void) __init; | |
45 | extern void mpc85xx_calibrate_decr(void) __init; | |
46 | ||
47 | #define PCI_CFG_ADDR_OFFSET (0x8000) | |
48 | #define PCI_CFG_DATA_OFFSET (0x8004) | |
49 | ||
50 | /* PCI interrupt controller */ | |
51 | #define PIRQA MPC85xx_IRQ_EXT1 | |
52 | #define PIRQB MPC85xx_IRQ_EXT2 | |
53 | #define PIRQC MPC85xx_IRQ_EXT3 | |
54 | #define PIRQD MPC85xx_IRQ_EXT4 | |
55 | #define PCI_MIN_IDSEL 16 | |
56 | #define PCI_MAX_IDSEL 19 | |
57 | #define PCI_IRQ_SLOT 4 | |
58 | ||
59 | #define MPC85XX_PCI1_LOWER_IO 0x00000000 | |
60 | #define MPC85XX_PCI1_UPPER_IO 0x00ffffff | |
61 | ||
62 | #define MPC85XX_PCI1_LOWER_MEM 0x80000000 | |
63 | #define MPC85XX_PCI1_UPPER_MEM 0x9fffffff | |
64 | ||
65 | #define MPC85XX_PCI1_IO_BASE 0xe2000000 | |
66 | #define MPC85XX_PCI1_MEM_OFFSET 0x00000000 | |
67 | ||
68 | #define MPC85XX_PCI1_IO_SIZE 0x01000000 | |
69 | ||
70 | #endif /* __MACH_STX_GP3_H */ |