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[PATCH] powerpc: trivial: modify comments to refer to new location of files
[deliverable/linux.git] / arch / ppc / platforms / 85xx / tqm85xx.c
CommitLineData
a819f8ba 1/*
a819f8ba
KG		 2 * TQM85xx (40/41/55/60) board specific routines
3 *
4 * Copyright (c) 2005 DENX Software Engineering
5 * Stefan Roese <sr@denx.de>
6 *
7 * Based on original work by
8 * Kumar Gala <galak@kernel.crashing.org>
9 * Copyright 2004 Freescale Semiconductor Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/config.h>
18#include <linux/stddef.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/errno.h>
22#include <linux/reboot.h>
23#include <linux/pci.h>
24#include <linux/kdev_t.h>
25#include <linux/major.h>
26#include <linux/console.h>
27#include <linux/delay.h>
28#include <linux/seq_file.h>
29#include <linux/root_dev.h>
30#include <linux/serial.h>
31#include <linux/tty.h> /* for linux/serial_core.h */
32#include <linux/serial_core.h>
33#include <linux/initrd.h>
34#include <linux/module.h>
35#include <linux/fsl_devices.h>
36
37#include <asm/system.h>
38#include <asm/pgtable.h>
39#include <asm/page.h>
40#include <asm/atomic.h>
41#include <asm/time.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/open_pic.h>
45#include <asm/bootinfo.h>
46#include <asm/pci-bridge.h>
47#include <asm/mpc85xx.h>
48#include <asm/irq.h>
49#include <asm/immap_85xx.h>
50#include <asm/kgdb.h>
51#include <asm/ppc_sys.h>
52#include <asm/cpm2.h>
53#include <mm/mmu_decl.h>
54
55#include <syslib/ppc85xx_setup.h>
56#include <syslib/cpm2_pic.h>
57#include <syslib/ppc85xx_common.h>
58#include <syslib/ppc85xx_rio.h>
59
60#ifndef CONFIG_PCI
61unsigned long isa_io_base = 0;
62unsigned long isa_mem_base = 0;
63#endif
64
65
66extern unsigned long total_memory; /* in mm/init */
67
68unsigned char __res[sizeof (bd_t)];
69
70/* Internal interrupts are all Level Sensitive, and Positive Polarity */
71static u_char tqm85xx_openpic_initsenses[] __initdata = {
72 MPC85XX_INTERNAL_IRQ_SENSES,
73 0x0, /* External 0: */
74 0x0, /* External 1: */
75#if defined(CONFIG_PCI)
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI INTA */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI INTB */
78#else
79 0x0, /* External 2: */
80 0x0, /* External 3: */
81#endif
82 0x0, /* External 4: */
83 0x0, /* External 5: */
84 0x0, /* External 6: */
85 0x0, /* External 7: */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: PHY */
87 0x0, /* External 9: */
88 0x0, /* External 10: */
89 0x0, /* External 11: */
90};
91
a819f8ba
KG		 92/* ************************************************************************
93 *
94 * Setup the architecture
95 *
96 */
97static void __init
98tqm85xx_setup_arch(void)
99{
100 bd_t *binfo = (bd_t *) __res;
101 unsigned int freq;
102 struct gianfar_platform_data *pdata;
103 struct gianfar_mdio_data *mdata;
104
105#ifdef CONFIG_MPC8560
106 cpm2_reset();
107#endif
108
109 /* get the core frequency */
110 freq = binfo->bi_intfreq;
111
112 if (ppc_md.progress)
113 ppc_md.progress("tqm85xx_setup_arch()", 0);
114
115 /* Set loops_per_jiffy to a half-way reasonable value,
116 for use until calibrate_delay gets called. */
117 loops_per_jiffy = freq / HZ;
118
119#ifdef CONFIG_PCI
120 /* setup PCI host bridges */
121 mpc85xx_setup_hose();
122#endif
123
124#ifndef CONFIG_MPC8560
125#if defined(CONFIG_SERIAL_8250)
126 mpc85xx_early_serial_map();
127#endif
128
129#ifdef CONFIG_SERIAL_TEXT_DEBUG
130 /* Invalidate the entry we stole earlier the serial ports
131 * should be properly mapped */
132 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
133#endif
134#endif /* CONFIG_MPC8560 */
135
136 /* setup the board related info for the MDIO bus */
137 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
138
139 mdata->irq[0] = MPC85xx_IRQ_EXT8;
140 mdata->irq[1] = MPC85xx_IRQ_EXT8;
141 mdata->irq[2] = -1;
142 mdata->irq[3] = MPC85xx_IRQ_EXT8;
143 mdata->irq[31] = -1;
a819f8ba
KG		 144
145 /* setup the board related information for the enet controllers */
146 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
147 if (pdata) {
148 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
7e78e5e5
KG		 149 pdata->bus_id = 0;
150 pdata->phy_id = 2;
a819f8ba
KG		 151 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
152 }
153
154 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
155 if (pdata) {
156 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
7e78e5e5
KG		 157 pdata->bus_id = 0;
158 pdata->phy_id = 1;
a819f8ba
KG		 159 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
160 }
161
162#ifdef CONFIG_MPC8540
163 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
164 if (pdata) {
165 pdata->board_flags = 0;
7e78e5e5
KG		 166 pdata->bus_id = 0;
167 pdata->phy_id = 3;
a819f8ba
KG		 168 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
169 }
170#endif
171
172#ifdef CONFIG_BLK_DEV_INITRD
173 if (initrd_start)
174 ROOT_DEV = Root_RAM0;
175 else
176#endif
177#ifdef CONFIG_ROOT_NFS
178 ROOT_DEV = Root_NFS;
179#else
180 ROOT_DEV = Root_HDA1;
181#endif
182}
183
184#ifdef CONFIG_MPC8560
185static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
186{
187 while ((irq = cpm2_get_irq(regs)) >= 0)
188 __do_IRQ(irq, regs);
189 return IRQ_HANDLED;
190}
191
192static struct irqaction cpm2_irqaction = {
193 .handler = cpm2_cascade,
194 .flags = SA_INTERRUPT,
195 .mask = CPU_MASK_NONE,
196 .name = "cpm2_cascade",
197};
198#endif /* CONFIG_MPC8560 */
199
200void __init
201tqm85xx_init_IRQ(void)
202{
203 bd_t *binfo = (bd_t *) __res;
204
205 /* Determine the Physical Address of the OpenPIC regs */
206 phys_addr_t OpenPIC_PAddr =
207 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
208 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
209 OpenPIC_InitSenses = tqm85xx_openpic_initsenses;
210 OpenPIC_NumInitSenses = sizeof (tqm85xx_openpic_initsenses);
211
212 /* Skip reserved space and internal sources */
213 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
214
215 /* Map PIC IRQs 0-11 */
216 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
217
218 /* we let openpic interrupts starting from an offset, to
219 * leave space for cascading interrupts underneath.
220 */
221 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
222
223#ifdef CONFIG_MPC8560
224 /* Setup CPM2 PIC */
225 cpm2_init_IRQ();
226
227 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
228#endif /* CONFIG_MPC8560 */
229
230 return;
231}
232
233int tqm85xx_show_cpuinfo(struct seq_file *m)
234{
235 uint pvid, svid, phid1;
236 uint memsize = total_memory;
237 bd_t *binfo = (bd_t *) __res;
238 unsigned int freq;
239
240 /* get the core frequency */
241 freq = binfo->bi_intfreq;
242
243 pvid = mfspr(SPRN_PVR);
244 svid = mfspr(SPRN_SVR);
245
246 seq_printf(m, "Vendor\t\t: TQ Components\n");
247 seq_printf(m, "Machine\t\t: TQM%s\n", cur_ppc_sys_spec->ppc_sys_name);
248 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
249 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
250 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
251
252 /* Display cpu Pll setting */
253 phid1 = mfspr(SPRN_HID1);
254 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
255
256 /* Display the amount of memory */
257 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
258
259 return 0;
260}
261
262#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_DS1337)
263extern ulong ds1337_get_rtc_time(void);
264extern int ds1337_set_rtc_time(unsigned long nowtime);
265
266static int __init
267tqm85xx_rtc_hookup(void)
268{
269 struct timespec tv;
270
271 ppc_md.set_rtc_time = ds1337_set_rtc_time;
272 ppc_md.get_rtc_time = ds1337_get_rtc_time;
273
274 tv.tv_nsec = 0;
275 tv.tv_sec = (ppc_md.get_rtc_time)();
276 do_settimeofday(&tv);
277
278 return 0;
279}
280late_initcall(tqm85xx_rtc_hookup);
281#endif
282
283#ifdef CONFIG_PCI
284/*
285 * interrupt routing
286 */
287int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
288{
289 static char pci_irq_table[][4] =
290 /*
291 * PCI IDSEL/INTPIN->INTLINE
292 * A B C D
293 */
294 {
295 {PIRQA, PIRQB, 0, 0},
296 };
297
298 const long min_idsel = 0x1c, max_idsel = 0x1c, irqs_per_slot = 4;
299 return PCI_IRQ_TABLE_LOOKUP;
300}
301
302int mpc85xx_exclude_device(u_char bus, u_char devfn)
303{
304 if (bus == 0 && PCI_SLOT(devfn) == 0)
305 return PCIBIOS_DEVICE_NOT_FOUND;
306 else
307 return PCIBIOS_SUCCESSFUL;
308}
309
310#endif /* CONFIG_PCI */
311
312#ifdef CONFIG_RAPIDIO
313void platform_rio_init(void)
314{
315 /* 512MB RIO LAW at 0xc0000000 */
316 mpc85xx_rio_setup(0xc0000000, 0x20000000);
317}
318#endif /* CONFIG_RAPIDIO */
319
320/* ************************************************************************ */
321void __init
322platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
323 unsigned long r6, unsigned long r7)
324{
325 /* parse_bootinfo must always be called first */
326 parse_bootinfo(find_bootinfo());
327
328 /*
329 * If we were passed in a board information, copy it into the
330 * residual data area.
331 */
332 if (r3) {
333 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
334 sizeof (bd_t));
335 }
336
337#if defined(CONFIG_SERIAL_TEXT_DEBUG) && !defined(CONFIG_MPC8560)
338 {
339 bd_t *binfo = (bd_t *) __res;
340 struct uart_port p;
341
342 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
343 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
344 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
345
346 memset(&p, 0, sizeof (p));
9b4a1617 347 p.iotype = UPIO_MEM;
a819f8ba
KG		 348 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
349 p.uartclk = binfo->bi_busfreq;
350
351 gen550_init(0, &p);
352
353 memset(&p, 0, sizeof (p));
9b4a1617 354 p.iotype = UPIO_MEM;
a819f8ba
KG		 355 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
356 p.uartclk = binfo->bi_busfreq;
357
358 gen550_init(1, &p);
359 }
360#endif
361
362#if defined(CONFIG_BLK_DEV_INITRD)
363 /*
364 * If the init RAM disk has been configured in, and there's a valid
365 * starting address for it, set it up.
366 */
367 if (r4) {
368 initrd_start = r4 + KERNELBASE;
369 initrd_end = r5 + KERNELBASE;
370 }
371#endif /* CONFIG_BLK_DEV_INITRD */
372
373 /* Copy the kernel command line arguments to a safe place. */
374
375 if (r6) {
376 *(char *) (r7 + KERNELBASE) = 0;
377 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
378 }
379
380 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
381
382 /* setup the PowerPC module struct */
383 ppc_md.setup_arch = tqm85xx_setup_arch;
384 ppc_md.show_cpuinfo = tqm85xx_show_cpuinfo;
385
386 ppc_md.init_IRQ = tqm85xx_init_IRQ;
387 ppc_md.get_irq = openpic_get_irq;
388
389 ppc_md.restart = mpc85xx_restart;
390 ppc_md.power_off = mpc85xx_power_off;
391 ppc_md.halt = mpc85xx_halt;
392
393 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
394
395 ppc_md.time_init = NULL;
396 ppc_md.set_rtc_time = NULL;
397 ppc_md.get_rtc_time = NULL;
398 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
399
400#ifndef CONFIG_MPC8560
401#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
402 ppc_md.progress = gen550_progress;
403#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
404#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
405 ppc_md.early_serial_map = mpc85xx_early_serial_map;
406#endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
407#endif /* CONFIG_MPC8560 */
408
409 if (ppc_md.progress)
410 ppc_md.progress("tqm85xx_init(): exit", 0);
411
412 return;
413}
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