projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 1da177e4 LT |
2 | * Definitions for Force CPCI690 |
| 3 | * | |
| 4 | * Author: Mark A. Greer <mgreer@mvista.com> | |
| 5 | * | |
| 6 | * 2003 (c) MontaVista, Software, Inc. This file is licensed under | |
| 7 | * the terms of the GNU General Public License version 2. This program | |
| 8 | * is licensed "as is" without any warranty of any kind, whether express | |
| 9 | * or implied. | |
| 10 | */ | |
| 11 | ||
| 12 | /* | |
| 13 | * The GT64260 has 2 PCI buses each with 1 window from the CPU bus to | |
| 14 | * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. | |
| 15 | */ | |
| 16 | ||
| 17 | #ifndef __PPC_PLATFORMS_CPCI690_H | |
| 18 | #define __PPC_PLATFORMS_CPCI690_H | |
| 19 | ||
| 20 | /* | |
| 21 | * Define bd_t to pass in the MAC addresses used by the GT64260's enet ctlrs. | |
| 22 | */ | |
| 23 | #define CPCI690_BI_MAGIC 0xFE8765DC | |
| 24 | ||
| 25 | typedef struct board_info { | |
| 26 | u32 bi_magic; | |
| 27 | u8 bi_enetaddr[3][6]; | |
| 28 | } bd_t; | |
| 29 | ||
| 30 | /* PCI bus Resource setup */ | |
| 31 | #define CPCI690_PCI0_MEM_START_PROC_ADDR 0x80000000 | |
| 32 | #define CPCI690_PCI0_MEM_START_PCI_HI_ADDR 0x00000000 | |
| 33 | #define CPCI690_PCI0_MEM_START_PCI_LO_ADDR 0x80000000 | |
| 34 | #define CPCI690_PCI0_MEM_SIZE 0x10000000 | |
| 35 | #define CPCI690_PCI0_IO_START_PROC_ADDR 0xa0000000 | |
| 36 | #define CPCI690_PCI0_IO_START_PCI_ADDR 0x00000000 | |
| 37 | #define CPCI690_PCI0_IO_SIZE 0x01000000 | |
| 38 | ||
| 39 | #define CPCI690_PCI1_MEM_START_PROC_ADDR 0x90000000 | |
| 40 | #define CPCI690_PCI1_MEM_START_PCI_HI_ADDR 0x00000000 | |
| 41 | #define CPCI690_PCI1_MEM_START_PCI_LO_ADDR 0x90000000 | |
| 42 | #define CPCI690_PCI1_MEM_SIZE 0x10000000 | |
| 43 | #define CPCI690_PCI1_IO_START_PROC_ADDR 0xa1000000 | |
| 44 | #define CPCI690_PCI1_IO_START_PCI_ADDR 0x01000000 | |
| 45 | #define CPCI690_PCI1_IO_SIZE 0x01000000 | |
| 46 | ||
| 47 | /* Board Registers */ | |
| 48 | #define CPCI690_BR_BASE 0xf0000000 | |
| 49 | #define CPCI690_BR_SIZE_ACTUAL 0x8 | |
| 50 | #define CPCI690_BR_SIZE max(GT64260_WINDOW_SIZE_MIN, \ | |
| 51 | CPCI690_BR_SIZE_ACTUAL) | |
| 52 | #define CPCI690_BR_LED_CNTL 0x00 | |
| 53 | #define CPCI690_BR_SW_RESET 0x01 | |
| 54 | #define CPCI690_BR_MISC_STATUS 0x02 | |
| 55 | #define CPCI690_BR_SWITCH_STATUS 0x03 | |
| 56 | #define CPCI690_BR_MEM_CTLR 0x04 | |
| 57 | #define CPCI690_BR_LAST_RESET_1 0x05 | |
| 58 | #define CPCI690_BR_LAST_RESET_2 0x06 | |
| 59 | ||
| 60 | #define CPCI690_TODC_BASE 0xf0100000 | |
| 61 | #define CPCI690_TODC_SIZE_ACTUAL 0x8000 /* Size or NVRAM + RTC */ | |
| 62 | #define CPCI690_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \ | |
| 63 | CPCI690_TODC_SIZE_ACTUAL) | |
| 64 | #define CPCI690_MAC_OFFSET 0x7c10 /* MAC in RTC NVRAM */ | |
| 65 | ||
| 66 | #define CPCI690_IPMI_BASE 0xf0200000 | |
| 67 | #define CPCI690_IPMI_SIZE_ACTUAL 0x10 /* 16 bytes of IPMI */ | |
| 68 | #define CPCI690_IPMI_SIZE max(GT64260_WINDOW_SIZE_MIN, \ | |
| 69 | CPCI690_IPMI_SIZE_ACTUAL) | |
| 70 | ||
| 71 | #define CPCI690_MPSC_BAUD 9600 | |
| 72 | #define CPCI690_MPSC_CLK_SRC 8 /* TCLK */ | |
| 73 | ||
| 1da177e4 | 74 | #endif /* __PPC_PLATFORMS_CPCI690_H */ |