[deliverable/linux.git] / arch / ppc / platforms / ev64360.c

/*
 * Board setup routines for the Marvell EV-64360-BP Evaluation Board.
 *
 * Author: Lee Nicks <allinux@gmail.com>
 *
 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/console.h>
#include <linux/initrd.h>
#include <linux/root_dev.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/bootmem.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
#ifdef CONFIG_BOOTIMG
#include <linux/bootimg.h>
#endif
#include <asm/page.h>
#include <asm/time.h>
#include <asm/smp.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/ppcboot.h>
#include <asm/mv64x60.h>
#include <asm/machdep.h>
#include <platforms/ev64360.h>

#define BOARD_VENDOR    "Marvell"
#define BOARD_MACHINE   "EV-64360-BP"

static struct		mv64x60_handle bh;
static void __iomem	*sram_base;

static u32		ev64360_flash_size_0;
static u32		ev64360_flash_size_1;

static u32		ev64360_bus_frequency;

unsigned char	__res[sizeof(bd_t)];

TODC_ALLOC();

static int __init
ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
	return 0;
}

static void __init
ev64360_setup_bridge(void)
{
	struct mv64x60_setup_info si;
	int i;

	memset(&si, 0, sizeof(si));

	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;

	#ifdef CONFIG_PCI
	si.pci_1.enable_bus = 1;
	si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
	si.pci_1.pci_io.pci_base_hi = 0;
	si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
	si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
	si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
	si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
	si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	si.pci_1.pci_cmd_bits = 0;
	si.pci_1.latency_timer = 0x80;
	#else
	si.pci_0.enable_bus = 0;
	si.pci_1.enable_bus = 0;
	#endif

	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;

		si.pci_1.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
		si.cpu_prot_options[i] = 0;
		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */

		si.pci_1.acc_cntl_options[i] =
		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
	}

	if (mv64x60_init(&bh, &si))
		printk(KERN_WARNING "Bridge initialization failed.\n");

	#ifdef CONFIG_PCI
	pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = ev64360_map_irq;
	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;

	mv64x60_set_bus(&bh, 1, 0);
	bh.hose_b->first_busno = 0;
	bh.hose_b->last_busno = 0xff;
	#endif
}

/* Bridge & platform setup routines */
void __init
ev64360_intr_setup(void)
{
	/* MPP 8, 9, and 10 */
	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);

	/*
	 * Define GPP 8,9,and 10 interrupt polarity as active low
	 * input signal and level triggered
	 */
	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);

	/* Config GPP intr ctlr to respond to level trigger */
	mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));

	/* Erranum FEr PCI-#8 */
	mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
	mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));

	/*
	 * Dismiss and then enable interrupt on GPP interrupt cause
	 * for CPU #0
	 */
	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);

	/*
	 * Dismiss and then enable interrupt on CPU #0 high cause reg
	 * BIT25 summarizes GPP interrupts 8-15
	 */
	mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
}

void __init
ev64360_setup_peripherals(void)
{
	u32 base;

	/* Set up window for boot CS */
	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
		 EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);

	/* We only use the 32-bit flash */
	mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
		&ev64360_flash_size_0);
	ev64360_flash_size_1 = 0;

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
		 EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);

	TODC_INIT(TODC_TYPE_DS1501, 0, 0,
		ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);

	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
		 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
	sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);

	/* Set up Enet->SRAM window */
	mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
		EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
	bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);

	/* Give enet r/w access to memory region */
	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));

	mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
			 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));

#if defined(CONFIG_NOT_COHERENT_CACHE)
	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
#else
	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif

	/*
	 * Setting the SRAM to 0. Note that this generates parity errors on
	 * internal data path in SRAM since it's first time accessing it
	 * while after reset it's not configured.
	 */
	memset(sram_base, 0, MV64360_SRAM_SIZE);

	/* set up PCI interrupt controller */
	ev64360_intr_setup();
}

static void __init
ev64360_setup_arch(void)
{
	if (ppc_md.progress)
		ppc_md.progress("ev64360_setup_arch: enter", 0);

	set_tb(0, 0);

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start)
		ROOT_DEV = Root_RAM0;
	else
#endif
#ifdef   CONFIG_ROOT_NFS
		ROOT_DEV = Root_NFS;
#else
		ROOT_DEV = Root_SDA2;
#endif

	/*
	 * Set up the L2CR register.
	 */
	_set_L2CR(L2CR_L2E | L2CR_L2PE);

	if (ppc_md.progress)
		ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);

	ev64360_setup_bridge();
	ev64360_setup_peripherals();
	ev64360_bus_frequency = ev64360_bus_freq();

	printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
		"(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
	if (ppc_md.progress)
		ppc_md.progress("ev64360_setup_arch: exit", 0);
}

/* Platform device data fixup routines. */
#if defined(CONFIG_SERIAL_MPSC)
static void __init
ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
{
	struct mpsc_pdata *pdata;

	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;

	pdata->max_idle = 40;
	pdata->default_baud = EV64360_DEFAULT_BAUD;
	pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
	/*
	 * TCLK (not SysCLk) is routed to BRG, then to the MPSC.  On most parts,
	 * TCLK == SysCLK but on 64460, they are separate pins.
	 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
	 */
	pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
}
#endif

#if defined(CONFIG_MV643XX_ETH)
static void __init
ev64360_fixup_eth_pdata(struct platform_device *pdev)
{
	struct mv643xx_eth_platform_data *eth_pd;
	static u16 phy_addr[] = {
		EV64360_ETH0_PHY_ADDR,
		EV64360_ETH1_PHY_ADDR,
		EV64360_ETH2_PHY_ADDR,
	};

	eth_pd = pdev->dev.platform_data;
	eth_pd->force_phy_addr = 1;
	eth_pd->phy_addr = phy_addr[pdev->id];
	eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
	eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
}
#endif

static int __init
ev64360_platform_notify(struct device *dev)
{
	static struct {
		char	*bus_id;
		void	((*rtn)(struct platform_device *pdev));
	} dev_map[] = {
#if defined(CONFIG_SERIAL_MPSC)
		{ MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
		{ MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
#endif
#if defined(CONFIG_MV643XX_ETH)
		{ MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
		{ MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
		{ MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
#endif
	};
	struct platform_device	*pdev;
	int	i;

	if (dev && dev->bus_id)
		for (i=0; i<ARRAY_SIZE(dev_map); i++)
			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
				BUS_ID_SIZE)) {

				pdev = container_of(dev,
					struct platform_device, dev);
				dev_map[i].rtn(pdev);
			}

	return 0;
}

#ifdef CONFIG_MTD_PHYSMAP

#ifndef MB
#define MB	(1 << 20)
#endif

/*
 * MTD Layout.
 *
 * FLASH Amount:	0xff000000 - 0xffffffff
 * -------------	-----------------------
 * Reserved:		0xff000000 - 0xff03ffff
 * JFFS2 file system:	0xff040000 - 0xffefffff
 * U-boot:		0xfff00000 - 0xffffffff
 */
static int __init
ev64360_setup_mtd(void)
{
	u32	size;
	int	ptbl_entries;
	static struct mtd_partition	*ptbl;

	size = ev64360_flash_size_0 + ev64360_flash_size_1;
	if (!size)
		return -ENOMEM;

	ptbl_entries = 3;

	if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
		GFP_KERNEL)) == NULL) {

		printk(KERN_WARNING "Can't alloc MTD partition table\n");
		return -ENOMEM;
	}
	memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));

	ptbl[0].name = "reserved";
	ptbl[0].offset = 0;
	ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
	ptbl[1].name = "jffs2";
	ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
	ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
	ptbl[2].name = "U-BOOT";
	ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
	ptbl[2].size = EV64360_MTD_UBOOT_SIZE;

	physmap_map.size = size;
	physmap_set_partitions(ptbl, ptbl_entries);
	return 0;
}

arch_initcall(ev64360_setup_mtd);
#endif

static void
ev64360_restart(char *cmd)
{
	ulong	i = 0xffffffff;
	volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);

	/* issue hard reset */
	rtc_base[0xf] = 0x80;
	rtc_base[0xc] = 0x00;
	rtc_base[0xd] = 0x01;
	rtc_base[0xf] = 0x83;

	while (i-- > 0) ;
	panic("restart failed\n");
}

static void
ev64360_halt(void)
{
	while (1) ;
	/* NOTREACHED */
}

static void
ev64360_power_off(void)
{
	ev64360_halt();
	/* NOTREACHED */
}

static int
ev64360_show_cpuinfo(struct seq_file *m)
{
	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
	seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);

	return 0;
}

static void __init
ev64360_calibrate_decr(void)
{
	u32 freq;

	freq = ev64360_bus_frequency / 4;

	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
	       (long)freq / 1000000, (long)freq % 1000000);

	tb_ticks_per_jiffy = freq / HZ;
	tb_to_us = mulhwu_scale_factor(freq, 1000000);
}

unsigned long __init
ev64360_find_end_of_memory(void)
{
	return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
		MV64x60_TYPE_MV64360);
}

static inline void
ev64360_set_bat(void)
{
	mb();
	mtspr(SPRN_DBAT2U, 0xf0001ffe);
	mtspr(SPRN_DBAT2L, 0xf000002a);
	mb();
}

#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
static void __init
ev64360_map_io(void)
{
	io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
			 CONFIG_MV64X60_NEW_BASE, \
			 0x00020000, _PAGE_IO);
}
#endif

void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
	      unsigned long r6, unsigned long r7)
{
	parse_bootinfo(find_bootinfo());

	/* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
	 * are non-zero, then we should use the board info from the bd_t
	 * structure and the cmdline pointed to by r6 instead of the
	 * information from birecs, if any.  Otherwise, use the information
	 * from birecs as discovered by the preceeding call to
	 * parse_bootinfo().  This rule should work with both PPCBoot, which
	 * uses a bd_t board info structure, and the kernel boot wrapper,
	 * which uses birecs.
	 */
	if (r3 && r6) {
		/* copy board info structure */
		memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
		/* copy command line */
		*(char *)(r7+KERNELBASE) = 0;
		strcpy(cmd_line, (char *)(r6+KERNELBASE));
	}
	#ifdef CONFIG_ISA
	isa_mem_base = 0;
	#endif

	ppc_md.setup_arch = ev64360_setup_arch;
	ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
	ppc_md.init_IRQ = mv64360_init_irq;
	ppc_md.get_irq = mv64360_get_irq;
	ppc_md.restart = ev64360_restart;
	ppc_md.power_off = ev64360_power_off;
	ppc_md.halt = ev64360_halt;
	ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
	ppc_md.init = NULL;

	ppc_md.time_init = todc_time_init;
	ppc_md.set_rtc_time = todc_set_rtc_time;
	ppc_md.get_rtc_time = todc_get_rtc_time;
	ppc_md.nvram_read_val = todc_direct_read_val;
	ppc_md.nvram_write_val = todc_direct_write_val;
	ppc_md.calibrate_decr = ev64360_calibrate_decr;

#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
	ppc_md.setup_io_mappings = ev64360_map_io;
	ppc_md.progress = mv64x60_mpsc_progress;
	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
#endif

#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
	platform_notify = ev64360_platform_notify;
#endif

	ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
}
Commit	Line	Data
3acb2344	1	/*
3acb2344 LN	2	* Board setup routines for the Marvell EV-64360-BP Evaluation Board.
	3	*
	4	* Author: Lee Nicks <allinux@gmail.com>
	5	*
	6	* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
	7	* Based on code done by - Mark A. Greer <mgreer@mvista.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14	#include <linux/config.h>
	15	#include <linux/kernel.h>
	16	#include <linux/pci.h>
	17	#include <linux/kdev_t.h>
	18	#include <linux/console.h>
	19	#include <linux/initrd.h>
	20	#include <linux/root_dev.h>
	21	#include <linux/delay.h>
	22	#include <linux/seq_file.h>
	23	#include <linux/bootmem.h>
	24	#include <linux/mtd/physmap.h>
	25	#include <linux/mv643xx.h>
d052d1be	26	#include <linux/platform_device.h>
3acb2344 LN	27	#ifdef CONFIG_BOOTIMG
	28	#include <linux/bootimg.h>
	29	#endif
	30	#include <asm/page.h>
	31	#include <asm/time.h>
	32	#include <asm/smp.h>
	33	#include <asm/todc.h>
	34	#include <asm/bootinfo.h>
	35	#include <asm/ppcboot.h>
	36	#include <asm/mv64x60.h>
fd582ec8	37	#include <asm/machdep.h>
3acb2344 LN	38	#include <platforms/ev64360.h>
	39
	40	#define BOARD_VENDOR "Marvell"
	41	#define BOARD_MACHINE "EV-64360-BP"
	42
	43	static struct mv64x60_handle bh;
	44	static void __iomem *sram_base;
	45
	46	static u32 ev64360_flash_size_0;
	47	static u32 ev64360_flash_size_1;
	48
	49	static u32 ev64360_bus_frequency;
	50
	51	unsigned char __res[sizeof(bd_t)];
	52
2104da90 LN	53	TODC_ALLOC();
2104da90 LN	54
3acb2344 LN	55	static int __init
	56	ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
	57	{
	58	return 0;
	59	}
	60
	61	static void __init
	62	ev64360_setup_bridge(void)
	63	{
	64	struct mv64x60_setup_info si;
	65	int i;
	66
	67	memset(&si, 0, sizeof(si));
	68
	69	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
	70
	71	#ifdef CONFIG_PCI
	72	si.pci_1.enable_bus = 1;
	73	si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
	74	si.pci_1.pci_io.pci_base_hi = 0;
	75	si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
	76	si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
	77	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
	78	si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
	79	si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
	80	si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
	81	si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
	82	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
	83	si.pci_1.pci_cmd_bits = 0;
	84	si.pci_1.latency_timer = 0x80;
	85	#else
	86	si.pci_0.enable_bus = 0;
	87	si.pci_1.enable_bus = 0;
	88	#endif
	89
	90	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
	91	#if defined(CONFIG_NOT_COHERENT_CACHE)
	92	si.cpu_prot_options[i] = 0;
	93	si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
	94	si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
	95	si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
	96
	97	si.pci_1.acc_cntl_options[i] =
	98	MV64360_PCI_ACC_CNTL_SNOOP_NONE \|
	99	MV64360_PCI_ACC_CNTL_SWAP_NONE \|
	100	MV64360_PCI_ACC_CNTL_MBURST_128_BYTES \|
	101	MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
	102	#else
	103	si.cpu_prot_options[i] = 0;
	104	si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
	105	si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
	106	si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
	107
	108	si.pci_1.acc_cntl_options[i] =
	109	MV64360_PCI_ACC_CNTL_SNOOP_WB \|
	110	MV64360_PCI_ACC_CNTL_SWAP_NONE \|
	111	MV64360_PCI_ACC_CNTL_MBURST_32_BYTES \|
	112	MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
	113	#endif
	114	}
	115
	116	if (mv64x60_init(&bh, &si))
	117	printk(KERN_WARNING "Bridge initialization failed.\n");
	118
119	#ifdef CONFIG_PCI
120	pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
121	ppc_md.pci_swizzle = common_swizzle;
122	ppc_md.pci_map_irq = ev64360_map_irq;
123	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
124
125	mv64x60_set_bus(&bh, 1, 0);
126	bh.hose_b->first_busno = 0;
127	bh.hose_b->last_busno = 0xff;
128	#endif
129	}
130
131	/* Bridge & platform setup routines */
132	void __init
133	ev64360_intr_setup(void)
134	{
135	/* MPP 8, 9, and 10 */
136	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
137
138	/*
139	* Define GPP 8,9,and 10 interrupt polarity as active low
140	* input signal and level triggered
141	*/
142	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
143	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
144
145	/* Config GPP intr ctlr to respond to level trigger */
146	mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
147
148	/* Erranum FEr PCI-#8 */
149	mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) \| (1<<9));
150	mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) \| (1<<9));
151
152	/*
153	* Dismiss and then enable interrupt on GPP interrupt cause
154	* for CPU #0
155	*/
156	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
157	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
158
159	/*
160	* Dismiss and then enable interrupt on CPU #0 high cause reg
161	* BIT25 summarizes GPP interrupts 8-15
162	*/
163	mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
164	}
165
166	void __init
167	ev64360_setup_peripherals(void)
168	{
169	u32 base;
170
171	/* Set up window for boot CS */
172	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
173	EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
174	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
175
176	/* We only use the 32-bit flash */
177	mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
178	&ev64360_flash_size_0);
179	ev64360_flash_size_1 = 0;
180
181	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
182	EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
183	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
184
2104da90 LN	185	TODC_INIT(TODC_TYPE_DS1501, 0, 0,
	186	ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);
	187
3acb2344 LN	188	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
	189	EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
	190	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
	191	sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
	192
	193	/* Set up Enet->SRAM window */
	194	mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
	195	EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
	196	bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
	197
	198	/* Give enet r/w access to memory region */
	199	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
	200	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
	201	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
	202
	203	mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
	204	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
	205	((1 << 0) \| (1 << 8) \| (1 << 16) \| (1 << 24)));
	206
	207	#if defined(CONFIG_NOT_COHERENT_CACHE)
	208	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
	209	#else
	210	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
	211	#endif
	212
	213	/*
	214	* Setting the SRAM to 0. Note that this generates parity errors on
	215	* internal data path in SRAM since it's first time accessing it
	216	* while after reset it's not configured.
	217	*/
	218	memset(sram_base, 0, MV64360_SRAM_SIZE);
	219
	220	/* set up PCI interrupt controller */
	221	ev64360_intr_setup();
	222	}
	223
	224	static void __init
	225	ev64360_setup_arch(void)
	226	{
	227	if (ppc_md.progress)
	228	ppc_md.progress("ev64360_setup_arch: enter", 0);
	229
	230	set_tb(0, 0);
	231
	232	#ifdef CONFIG_BLK_DEV_INITRD
	233	if (initrd_start)
	234	ROOT_DEV = Root_RAM0;
	235	else
	236	#endif
	237	#ifdef CONFIG_ROOT_NFS
	238	ROOT_DEV = Root_NFS;
	239	#else
	240	ROOT_DEV = Root_SDA2;
	241	#endif
	242
	243	/*
	244	* Set up the L2CR register.
	245	*/
	246	_set_L2CR(L2CR_L2E \| L2CR_L2PE);
	247
	248	if (ppc_md.progress)
	249	ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);
	250
	251	ev64360_setup_bridge();
252	ev64360_setup_peripherals();
253	ev64360_bus_frequency = ev64360_bus_freq();
254
255	printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
256	"(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
257	if (ppc_md.progress)
258	ppc_md.progress("ev64360_setup_arch: exit", 0);
259	}
260
261	/* Platform device data fixup routines. */
262	#if defined(CONFIG_SERIAL_MPSC)
263	static void __init
264	ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
265	{
266	struct mpsc_pdata *pdata;
267
268	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
269
270	pdata->max_idle = 40;
271	pdata->default_baud = EV64360_DEFAULT_BAUD;
272	pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
273	/*
274	* TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
275	* TCLK == SysCLK but on 64460, they are separate pins.
276	* SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
277	*/
278	pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
279	}
280	#endif
281
282	#if defined(CONFIG_MV643XX_ETH)
283	static void __init
284	ev64360_fixup_eth_pdata(struct platform_device *pdev)
285	{
286	struct mv643xx_eth_platform_data *eth_pd;
287	static u16 phy_addr[] = {
288	EV64360_ETH0_PHY_ADDR,
289	EV64360_ETH1_PHY_ADDR,
290	EV64360_ETH2_PHY_ADDR,
291	};
292
293	eth_pd = pdev->dev.platform_data;
294	eth_pd->force_phy_addr = 1;
295	eth_pd->phy_addr = phy_addr[pdev->id];
296	eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
297	eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
298	}
299	#endif
300
301	static int __init
302	ev64360_platform_notify(struct device *dev)
303	{
304	static struct {
305	char *bus_id;
306	void ((rtn)(struct platform_device pdev));
307	} dev_map[] = {
308	#if defined(CONFIG_SERIAL_MPSC)
309	{ MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
310	{ MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
311	#endif
312	#if defined(CONFIG_MV643XX_ETH)
313	{ MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
314	{ MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
315	{ MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
316	#endif
317	};
318	struct platform_device *pdev;
319	int i;
320
321	if (dev && dev->bus_id)
322	for (i=0; i<ARRAY_SIZE(dev_map); i++)
323	if (!strncmp(dev->bus_id, dev_map[i].bus_id,
324	BUS_ID_SIZE)) {
325
326	pdev = container_of(dev,
327	struct platform_device, dev);
328	dev_map[i].rtn(pdev);
329	}
330
331	return 0;
332	}
333
334	#ifdef CONFIG_MTD_PHYSMAP
335
336	#ifndef MB
337	#define MB (1 << 20)
338	#endif
339
340	/*
341	* MTD Layout.
342	*
343	* FLASH Amount: 0xff000000 - 0xffffffff
344	* ------------- -----------------------
345	* Reserved: 0xff000000 - 0xff03ffff
346	* JFFS2 file system: 0xff040000 - 0xffefffff
347	* U-boot: 0xfff00000 - 0xffffffff
348	*/
349	static int __init
350	ev64360_setup_mtd(void)
351	{
352	u32 size;
353	int ptbl_entries;
354	static struct mtd_partition *ptbl;
355
356	size = ev64360_flash_size_0 + ev64360_flash_size_1;
357	if (!size)
358	return -ENOMEM;
359
360	ptbl_entries = 3;
361
362	if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
363	GFP_KERNEL)) == NULL) {
364
365	printk(KERN_WARNING "Can't alloc MTD partition table\n");
366	return -ENOMEM;
367	}
368	memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
369
370	ptbl[0].name = "reserved";
371	ptbl[0].offset = 0;
372	ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
373	ptbl[1].name = "jffs2";
374	ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
375	ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
376	ptbl[2].name = "U-BOOT";
377	ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
378	ptbl[2].size = EV64360_MTD_UBOOT_SIZE;
379
380	physmap_map.size = size;
381	physmap_set_partitions(ptbl, ptbl_entries);
382	return 0;
383	}
384
385	arch_initcall(ev64360_setup_mtd);
386	#endif
387
388	static void
389	ev64360_restart(char *cmd)
390	{
391	ulong i = 0xffffffff;
392	volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);
393
394	/* issue hard reset */
395	rtc_base[0xf] = 0x80;
396	rtc_base[0xc] = 0x00;
397	rtc_base[0xd] = 0x01;
398	rtc_base[0xf] = 0x83;
399
400	while (i-- > 0) ;
401	panic("restart failed\n");
402	}
403
404	static void
405	ev64360_halt(void)
406	{
407	while (1) ;
408	/* NOTREACHED */
409	}
410
411	static void
412	ev64360_power_off(void)
413	{
414	ev64360_halt();
415	/* NOTREACHED */
416	}
417
418	static int
419	ev64360_show_cpuinfo(struct seq_file *m)
420	{
421	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
422	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
423	seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);
424
425	return 0;
426	}
427
428	static void __init
429	ev64360_calibrate_decr(void)
430	{
431	u32 freq;
432
433	freq = ev64360_bus_frequency / 4;
434
435	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
436	(long)freq / 1000000, (long)freq % 1000000);
437
438	tb_ticks_per_jiffy = freq / HZ;
439	tb_to_us = mulhwu_scale_factor(freq, 1000000);
440	}
441
442	unsigned long __init
443	ev64360_find_end_of_memory(void)
444	{
445	return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
446	MV64x60_TYPE_MV64360);
447	}
448
449	static inline void
450	ev64360_set_bat(void)
451	{
452	mb();
453	mtspr(SPRN_DBAT2U, 0xf0001ffe);
454	mtspr(SPRN_DBAT2L, 0xf000002a);
455	mb();
456	}
457
458	#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
459	static void __init
460	ev64360_map_io(void)
461	{
462	io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
463	CONFIG_MV64X60_NEW_BASE, \
464	0x00020000, _PAGE_IO);
465	}
466	#endif
467
468	void __init
469	platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
470	unsigned long r6, unsigned long r7)
471	{
472	parse_bootinfo(find_bootinfo());
473
474	/* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
475	* are non-zero, then we should use the board info from the bd_t
476	* structure and the cmdline pointed to by r6 instead of the
477	* information from birecs, if any. Otherwise, use the information
478	* from birecs as discovered by the preceeding call to
479	* parse_bootinfo(). This rule should work with both PPCBoot, which
480	* uses a bd_t board info structure, and the kernel boot wrapper,
481	* which uses birecs.
482	*/
483	if (r3 && r6) {
484	/* copy board info structure */
485	memcpy( (void )__res,(void )(r3+KERNELBASE), sizeof(bd_t) );
486	/* copy command line */
487	(char )(r7+KERNELBASE) = 0;
488	strcpy(cmd_line, (char *)(r6+KERNELBASE));
489	}
490	#ifdef CONFIG_ISA
491	isa_mem_base = 0;
492	#endif
493
494	ppc_md.setup_arch = ev64360_setup_arch;
495	ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
496	ppc_md.init_IRQ = mv64360_init_irq;
497	ppc_md.get_irq = mv64360_get_irq;
498	ppc_md.restart = ev64360_restart;
499	ppc_md.power_off = ev64360_power_off;
500	ppc_md.halt = ev64360_halt;
501	ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
2104da90 LN	502	ppc_md.init = NULL;
	503
	504	ppc_md.time_init = todc_time_init;
	505	ppc_md.set_rtc_time = todc_set_rtc_time;
	506	ppc_md.get_rtc_time = todc_get_rtc_time;
	507	ppc_md.nvram_read_val = todc_direct_read_val;
	508	ppc_md.nvram_write_val = todc_direct_write_val;
3acb2344 LN	509	ppc_md.calibrate_decr = ev64360_calibrate_decr;
	510
	511	#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
	512	ppc_md.setup_io_mappings = ev64360_map_io;
	513	ppc_md.progress = mv64x60_mpsc_progress;
	514	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
	515	#endif
	516
	517	#if defined(CONFIG_SERIAL_MPSC) \|\| defined(CONFIG_MV643XX_ETH)
	518	platform_notify = ev64360_platform_notify;
	519	#endif
	520
	521	ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
	522	}