projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 1da177e4 LT |
2 | * Definitions for Sky Computers HDPU board. |
| 3 | * | |
| 4 | * Brian Waite <waite@skycomputers.com> | |
| 5 | * | |
| 6 | * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il | |
| 7 | * Based on code done by Mark A. Greer <mgreer@mvista.com> | |
| 8 | * Based on code done by Tim Montgomery <timm@artesyncp.com> | |
| 9 | * | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify it | |
| 12 | * under the terms of the GNU General Public License as published by the | |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 14 | * option) any later version. | |
| 15 | */ | |
| 16 | ||
| 17 | /* | |
| 18 | * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to | |
| 19 | * PCI I/O space and 4 windows from the CPU bus to PCI MEM space. | |
| 20 | * We'll only use one PCI MEM window on each PCI bus. | |
| 21 | * | |
| 22 | * This is the CPU physical memory map (windows must be at least 64K and start | |
| 23 | * on a boundary that is a multiple of the window size): | |
| 24 | * | |
| 25 | * 0x80000000-0x8fffffff - PCI 0 MEM | |
| 26 | * 0xa0000000-0xafffffff - PCI 1 MEM | |
| 27 | * 0xc0000000-0xc0ffffff - PCI 0 I/O | |
| 28 | * 0xc1000000-0xc1ffffff - PCI 1 I/O | |
| 29 | ||
| 30 | * 0xf1000000-0xf100ffff - MV64360 Registers | |
| 31 | * 0xf1010000-0xfb9fffff - HOLE | |
| 32 | * 0xfbfa0000-0xfbfaffff - TBEN | |
| 33 | * 0xfbf00000-0xfbfbffff - NEXUS | |
| 34 | * 0xfbfc0000-0xfbffffff - Internal SRAM | |
| 35 | * 0xfc000000-0xffffffff - Boot window | |
| 36 | */ | |
| 37 | ||
| 38 | #ifndef __PPC_PLATFORMS_HDPU_H | |
| 39 | #define __PPC_PLATFORMS_HDPU_H | |
| 40 | ||
| 41 | /* CPU Physical Memory Map setup. */ | |
| 42 | #define HDPU_BRIDGE_REG_BASE 0xf1000000 | |
| 43 | ||
| 44 | #define HDPU_TBEN_BASE 0xfbfa0000 | |
| 45 | #define HDPU_TBEN_SIZE 0x00010000 | |
| 46 | #define HDPU_NEXUS_ID_BASE 0xfbfb0000 | |
| 47 | #define HDPU_NEXUS_ID_SIZE 0x00010000 | |
| 48 | #define HDPU_INTERNAL_SRAM_BASE 0xfbfc0000 | |
| 49 | #define HDPU_INTERNAL_SRAM_SIZE 0x00040000 | |
| 50 | #define HDPU_EMB_FLASH_BASE 0xfc000000 | |
| 51 | #define HDPU_EMB_FLASH_SIZE 0x04000000 | |
| 52 | ||
| 53 | /* PCI Mappings */ | |
| 54 | ||
| 55 | #define HDPU_PCI0_MEM_START_PROC_ADDR 0x80000000 | |
| 56 | #define HDPU_PCI0_MEM_START_PCI_HI_ADDR 0x00000000 | |
| 57 | #define HDPU_PCI0_MEM_START_PCI_LO_ADDR HDPU_PCI0_MEM_START_PROC_ADDR | |
| 58 | #define HDPU_PCI0_MEM_SIZE 0x10000000 | |
| 59 | ||
| 60 | #define HDPU_PCI1_MEM_START_PROC_ADDR 0xc0000000 | |
| 61 | #define HDPU_PCI1_MEM_START_PCI_HI_ADDR 0x00000000 | |
| 62 | #define HDPU_PCI1_MEM_START_PCI_LO_ADDR HDPU_PCI1_MEM_START_PROC_ADDR | |
| 63 | #define HDPU_PCI1_MEM_SIZE 0x20000000 | |
| 64 | ||
| 65 | #define HDPU_PCI0_IO_START_PROC_ADDR 0xc0000000 | |
| 66 | #define HDPU_PCI0_IO_START_PCI_ADDR 0x00000000 | |
| 67 | #define HDPU_PCI0_IO_SIZE 0x01000000 | |
| 68 | ||
| 69 | #define HDPU_PCI1_IO_START_PROC_ADDR 0xc1000000 | |
| 70 | #define HDPU_PCI1_IO_START_PCI_ADDR 0x01000000 | |
| 71 | #define HDPU_PCI1_IO_SIZE 0x01000000 | |
| 72 | ||
| 73 | #define HDPU_DEFAULT_BAUD 115200 | |
| 74 | #define HDPU_MPSC_CLK_SRC 8 /* TCLK */ | |
| 75 | #define HDPU_MPSC_CLK_FREQ 133000000 /* 133 Mhz */ | |
| 76 | ||
| 77 | #define HDPU_PCI_0_IRQ (8+64) | |
| 78 | #define HDPU_PCI_1_IRQ (13+64) | |
| 79 | ||
| 80 | #endif /* __PPC_PLATFORMS_HDPU_H */ |