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[PATCH] powerpc: trivial: modify comments to refer to new location of files
[deliverable/linux.git] / arch / ppc / platforms / pplus.c
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1da177e4 1/*
1da177e4
LT		 2 * Board and PCI setup routines for MCG PowerPlus
3 *
4 * Author: Randy Vinson <rvinson@mvista.com>
5 *
6 * Derived from original PowerPlus PReP work by
7 * Cort Dougan, Johnnie Peters, Matt Porter, and
8 * Troy Benjegerdes.
9 *
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#include <linux/config.h>
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20#include <linux/ioport.h>
21#include <linux/console.h>
22#include <linux/pci.h>
1da177e4
LT		 23#include <linux/ide.h>
24#include <linux/seq_file.h>
25#include <linux/root_dev.h>
26
27#include <asm/system.h>
28#include <asm/io.h>
29#include <asm/pgtable.h>
30#include <asm/dma.h>
31#include <asm/machdep.h>
32#include <asm/prep_nvram.h>
33#include <asm/vga.h>
34#include <asm/i8259.h>
35#include <asm/open_pic.h>
36#include <asm/hawk.h>
37#include <asm/todc.h>
38#include <asm/bootinfo.h>
39#include <asm/kgdb.h>
40#include <asm/reg.h>
41
42#include "pplus.h"
43
44#undef DUMP_DBATS
45
46TODC_ALLOC();
47
48extern void pplus_setup_hose(void);
49extern void pplus_set_VIA_IDE_native(void);
50
51extern unsigned long loops_per_jiffy;
52unsigned char *Motherboard_map_name;
53
54/* Tables for known hardware */
55
56/* Motorola Mesquite */
57static inline int
58mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
59{
60 static char pci_irq_table[][4] =
61 /*
62 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
63 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
64 * PCI IDSEL/INTPIN->INTLINE
65 * A B C D
66 */
67 {
68 {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
69 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
70 {19, 19, 19, 19}, /* IDSEL 16 - PMC Slot 1 */
71 { 0, 0, 0, 0}, /* IDSEL 17 - unused */
72 { 0, 0, 0, 0}, /* IDSEL 18 - unused */
73 { 0, 0, 0, 0}, /* IDSEL 19 - unused */
74 {24, 25, 26, 27}, /* IDSEL 20 - P2P bridge (to cPCI 1) */
75 { 0, 0, 0, 0}, /* IDSEL 21 - unused */
76 {28, 29, 30, 31} /* IDSEL 22 - P2P bridge (to cPCI 2) */
77 };
78
79 const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
80 return PCI_IRQ_TABLE_LOOKUP;
81}
82
83/* Motorola Sitka */
84static inline int
85sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
86{
87 static char pci_irq_table[][4] =
88 /*
89 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
90 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
91 * PCI IDSEL/INTPIN->INTLINE
92 * A B C D
93 */
94 {
95 {18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
96 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
97 {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
98 {28, 25, 26, 27}, /* IDSEL 17 - PMC Slot 2 */
99 { 0, 0, 0, 0}, /* IDSEL 18 - unused */
100 { 0, 0, 0, 0}, /* IDSEL 19 - unused */
101 {20, 0, 0, 0} /* IDSEL 20 - P2P bridge (to cPCI) */
102 };
103
104 const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4;
105 return PCI_IRQ_TABLE_LOOKUP;
106}
107
108/* Motorola MTX */
109static inline int
110MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
111{
112 static char pci_irq_table[][4] =
113 /*
114 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
115 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
116 * PCI IDSEL/INTPIN->INTLINE
117 * A B C D
118 */
119 {
120 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
121 { 0, 0, 0, 0}, /* IDSEL 13 - unused */
122 {18, 0, 0, 0}, /* IDSEL 14 - Enet */
123 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
124 {25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
125 {26, 27, 28, 25}, /* IDSEL 17 - PMC Slot 2 */
126 {27, 28, 25, 26} /* IDSEL 18 - PCI Slot 3 */
127 };
128
129 const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4;
130 return PCI_IRQ_TABLE_LOOKUP;
131}
132
133/* Motorola MTX Plus */
134/* Secondary bus interrupt routing is not supported yet */
135static inline int
136MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
137{
138 static char pci_irq_table[][4] =
139 /*
140 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
141 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
142 * PCI IDSEL/INTPIN->INTLINE
143 * A B C D
144 */
145 {
146 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
147 { 0, 0, 0, 0}, /* IDSEL 13 - unused */
148 {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
149 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
150 {25, 26, 27, 28}, /* IDSEL 16 - PCI Slot 1P */
151 {26, 27, 28, 25}, /* IDSEL 17 - PCI Slot 2P */
152 {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
153 {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
154 { 0, 0, 0, 0} /* IDSEL 20 - P2P Bridge */
155 };
156
157 const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
158 return PCI_IRQ_TABLE_LOOKUP;
159}
160
161static inline int
162Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
163{
164 /* 2600
165 * Raven 31
166 * ISA 11
167 * SCSI 12 - IRQ3
168 * Univ 13
169 * eth 14 - IRQ2
170 * VGA 15 - IRQ4
171 * PMC1 16 - IRQ9,10,11,12 = PMC1 A-D
172 * PMC2 17 - IRQ12,9,10,11 = A-D
173 * SCSI2 18 - IRQ11
174 * eth2 19 - IRQ10
175 * PCIX 20 - IRQ9,10,11,12 = PCI A-D
176 */
177
178 /* 2400
179 * Hawk 31
180 * ISA 11
181 * Univ 13
182 * eth 14 - IRQ2
183 * PMC1 16 - IRQ9,10,11,12 = PMC A-D
184 * PMC2 17 - IRQ12,9,10,11 = PMC A-D
185 * PCIX 20 - IRQ9,10,11,12 = PMC A-D
186 */
187
188 /* 2300
189 * Raven 31
190 * ISA 11
191 * Univ 13
192 * eth 14 - IRQ2
193 * PMC1 16 - 9,10,11,12 = A-D
194 * PMC2 17 - 9,10,11,12 = B,C,D,A
195 */
196
197 static char pci_irq_table[][4] =
198 /*
199 * MPIC interrupts for various IDSEL values (MPIC IRQ0 =
200 * Linux IRQ16 (to leave room for ISA IRQs at 0-15).
201 * PCI IDSEL/INTPIN->INTLINE
202 * A B C D
203 */
204 {
205 {19, 0, 0, 0}, /* IDSEL 12 - SCSI */
206 { 0, 0, 0, 0}, /* IDSEL 13 - Universe PCI - VME */
207 {18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
208 { 0, 0, 0, 0}, /* IDSEL 15 - unused */
209 {25, 26, 27, 28}, /* IDSEL 16 - PCI/PMC Slot 1P */
210 {28, 25, 26, 27}, /* IDSEL 17 - PCI/PMC Slot 2P */
211 {27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
212 {26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
213 {25, 26, 27, 28} /* IDSEL 20 - P2P Bridge */
214 };
215
216 const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
217 return PCI_IRQ_TABLE_LOOKUP;
218}
219
220#define MOTOROLA_CPUTYPE_REG 0x800
221#define MOTOROLA_BASETYPE_REG 0x803
222#define MPIC_RAVEN_ID 0x48010000
223#define MPIC_HAWK_ID 0x48030000
224#define MOT_PROC2_BIT 0x800
225
226static u_char pplus_openpic_initsenses[] __initdata = {
227 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
228 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */
229 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */
230 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
231 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */
232 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
233 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
234 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
235 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
236 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
237 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
238 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
239 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
240 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
241 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
242 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),
243};
244
245int mot_entry = -1;
246int prep_keybd_present = 1;
247int mot_multi = 0;
248
249struct brd_info {
250 /* 0x100 mask assumes for Raven and Hawk boards that the level/edge
251 * are set */
252 int cpu_type;
253 /* 0x200 if this board has a Hawk chip. */
254 int base_type;
255 /* or'ed with 0x80 if this board should be checked for multi CPU */
256 int max_cpu;
257 const char *name;
258 int (*map_irq) (struct pci_dev *, unsigned char, unsigned char);
259};
260struct brd_info mot_info[] = {
261 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq},
262 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", mesquite_map_irq},
263 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", sitka_map_irq},
264 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", mesquite_map_irq},
265 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_map_irq},
266 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_map_irq},
267 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_map_irq},
268 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_map_irq},
269 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_map_irq},
270 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_map_irq},
271 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_map_irq},
272 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_map_irq},
273 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_map_irq},
274 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_map_irq},
275 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_map_irq},
276 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_map_irq},
277 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_map_irq},
278 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_map_irq},
279 {0x000, 0x00, 0x00, "", NULL}
280};
281
282void __init pplus_set_board_type(void)
283{
284 unsigned char cpu_type;
285 unsigned char base_mod;
286 int entry;
287 unsigned short devid;
288 unsigned long *ProcInfo = NULL;
289
290 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
291 base_mod = inb(MOTOROLA_BASETYPE_REG);
292 early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
293
294 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
295 /* Check for Hawk chip */
296 if (mot_info[entry].cpu_type & 0x200) {
297 if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
298 continue;
299 } else {
300 /* store the system config register for later use. */
301 ProcInfo =
302 (unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
303
304 /* Check non hawk boards */
305 if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
306 continue;
307
308 if (mot_info[entry].base_type == 0) {
309 mot_entry = entry;
310 break;
311 }
312
313 if (mot_info[entry].base_type != base_mod)
314 continue;
315 }
316
317 if (!(mot_info[entry].max_cpu & 0x80)) {
318 mot_entry = entry;
319 break;
320 }
321
322 /* processor 1 not present and max processor zero indicated */
323 if ((*ProcInfo & MOT_PROC2_BIT)
324 && !(mot_info[entry].max_cpu & 0x7f)) {
325 mot_entry = entry;
326 break;
327 }
328
329 /* processor 1 present and max processor zero indicated */
330 if (!(*ProcInfo & MOT_PROC2_BIT)
331 && (mot_info[entry].max_cpu & 0x7f)) {
332 mot_entry = entry;
333 break;
334 }
335
336 /* Indicate to system if this is a multiprocessor board */
337 if (!(*ProcInfo & MOT_PROC2_BIT))
338 mot_multi = 1;
339 }
340
341 if (mot_entry == -1)
342 /* No particular cpu type found - assume Mesquite (MCP750) */
343 mot_entry = 1;
344
345 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
346 ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
347}
348void __init pplus_pib_init(void)
349{
350 unsigned char reg;
351 unsigned short short_reg;
352
353 struct pci_dev *dev = NULL;
354
355 /*
356 * Perform specific configuration for the Via Tech or
357 * or Winbond PCI-ISA-Bridge part.
358 */
359 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
360 PCI_DEVICE_ID_VIA_82C586_1, dev))) {
361 /*
362 * PPCBUG does not set the enable bits
363 * for the IDE device. Force them on here.
364 */
365 pci_read_config_byte(dev, 0x40, &reg);
366
367 reg |= 0x03; /* IDE: Chip Enable Bits */
368 pci_write_config_byte(dev, 0x40, reg);
369 }
370
371 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
372 PCI_DEVICE_ID_VIA_82C586_2,
373 dev)) && (dev->devfn = 0x5a)) {
374 /* Force correct USB interrupt */
375 dev->irq = 11;
376 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
377 }
378
379 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
380 PCI_DEVICE_ID_WINBOND_83C553, dev))) {
381 /* Clear PCI Interrupt Routing Control Register. */
382 short_reg = 0x0000;
383 pci_write_config_word(dev, 0x44, short_reg);
384 /* Route IDE interrupts to IRQ 14 */
385 reg = 0xEE;
386 pci_write_config_byte(dev, 0x43, reg);
387 }
388
389 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
390 PCI_DEVICE_ID_WINBOND_82C105, dev))) {
391 /*
392 * Disable LEGIRQ mode so PCI INTS are routed
393 * directly to the 8259 and enable both channels
394 */
395 pci_write_config_dword(dev, 0x40, 0x10ff0033);
396
397 /* Force correct IDE interrupt */
398 dev->irq = 14;
399 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
400 }
401 pci_dev_put(dev);
402}
403
404void __init pplus_set_VIA_IDE_legacy(void)
405{
406 unsigned short vend, dev;
407
408 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
409 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
410
411 if ((vend == PCI_VENDOR_ID_VIA) &&
412 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
413 unsigned char temp;
414
415 /* put back original "standard" port base addresses */
416 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
417 PCI_BASE_ADDRESS_0, 0x1f1);
418 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
419 PCI_BASE_ADDRESS_1, 0x3f5);
420 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
421 PCI_BASE_ADDRESS_2, 0x171);
422 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
423 PCI_BASE_ADDRESS_3, 0x375);
424 early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
425 PCI_BASE_ADDRESS_4, 0xcc01);
426
427 /* put into legacy mode */
428 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
429 &temp);
430 temp &= ~0x05;
431 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
432 temp);
433 }
434}
435
436void pplus_set_VIA_IDE_native(void)
437{
438 unsigned short vend, dev;
439
440 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
441 early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
442
443 if ((vend == PCI_VENDOR_ID_VIA) &&
444 (dev == PCI_DEVICE_ID_VIA_82C586_1)) {
445 unsigned char temp;
446
447 /* put into native mode */
448 early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
449 &temp);
450 temp |= 0x05;
451 early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
452 temp);
453 }
454}
455
456void __init pplus_pcibios_fixup(void)
457{
458
459 unsigned char reg;
460 unsigned short devid;
461 unsigned char base_mod;
462
463 printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
464 Motherboard_map_name);
465
466 /* Setup the Winbond or Via PIB */
467 pplus_pib_init();
468
469 /* Set up floppy in PS/2 mode */
470 outb(0x09, SIO_CONFIG_RA);
471 reg = inb(SIO_CONFIG_RD);
472 reg = (reg & 0x3F) | 0x40;
473 outb(reg, SIO_CONFIG_RD);
474 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
475
476 /* This is a hack. If this is a 2300 or 2400 mot board then there is
477 * no keyboard controller and we have to indicate that.
478 */
479
480 early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
481 base_mod = inb(MOTOROLA_BASETYPE_REG);
482 if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
483 (base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
484 prep_keybd_present = 0;
485}
486
487void __init pplus_find_bridges(void)
488{
489 struct pci_controller *hose;
490
491 hose = pcibios_alloc_controller();
492 if (!hose)
493 return;
494
495 hose->first_busno = 0;
496 hose->last_busno = 0xff;
497
498 hose->pci_mem_offset = PREP_ISA_MEM_BASE;
499 hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
500
501 pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START,
502 PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge");
503 pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START,
504 PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM,
505 "PCI host bridge");
506
507 hose->io_space.start = PPLUS_PCI_IO_START;
508 hose->io_space.end = PPLUS_PCI_IO_END;
509 hose->mem_space.start = PPLUS_PCI_MEM_START;
510 hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
511
512 if (hawk_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
513 PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
514 PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
515 PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
516 != 0) {
517 printk(KERN_CRIT "Could not initialize host bridge\n");
518
519 }
520
521 pplus_set_VIA_IDE_legacy();
522
523 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
524
525 ppc_md.pcibios_fixup = pplus_pcibios_fixup;
526 ppc_md.pci_swizzle = common_swizzle;
527}
528
529static int pplus_show_cpuinfo(struct seq_file *m)
530{
531 seq_printf(m, "vendor\t\t: Motorola MCG\n");
532 seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
533
534 return 0;
535}
536
537static void __init pplus_setup_arch(void)
538{
539 struct pci_controller *hose;
540
541 if (ppc_md.progress)
542 ppc_md.progress("pplus_setup_arch: enter", 0);
543
544 /* init to some ~sane value until calibrate_delay() runs */
545 loops_per_jiffy = 50000000;
546
547 if (ppc_md.progress)
548 ppc_md.progress("pplus_setup_arch: find_bridges", 0);
549
550 /* Setup PCI host bridge */
551 pplus_find_bridges();
552
553 hose = pci_bus_to_hose(0);
554 isa_io_base = (ulong) hose->io_base_virt;
555
556 if (ppc_md.progress)
557 ppc_md.progress("pplus_setup_arch: set_board_type", 0);
558
559 pplus_set_board_type();
560
561 /* Enable L2. Assume we don't need to flush -- Cort */
562 *(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3;
563
564#ifdef CONFIG_BLK_DEV_INITRD
565 if (initrd_start)
566 ROOT_DEV = Root_RAM0;
567 else
568#endif
569#ifdef CONFIG_ROOT_NFS
570 ROOT_DEV = Root_NFS;
571#else
572 ROOT_DEV = Root_SDA2;
573#endif
574
575 printk(KERN_INFO "Motorola PowerPlus Platform\n");
576 printk(KERN_INFO
577 "Port by MontaVista Software, Inc. (source@mvista.com)\n");
578
579#ifdef CONFIG_VGA_CONSOLE
580 /* remap the VGA memory */
581 vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE,
582 0x08000000);
583 conswitchp = &vga_con;
584#endif
585#ifdef CONFIG_PPCBUG_NVRAM
586 /* Read in NVRAM data */
587 init_prep_nvram();
588
589 /* if no bootargs, look in NVRAM */
590 if (cmd_line[0] == '\0') {
591 char *bootargs;
592 bootargs = prep_nvram_get_var("bootargs");
593 if (bootargs != NULL) {
594 strcpy(cmd_line, bootargs);
595 /* again.. */
596 strcpy(saved_command_line, cmd_line);
597 }
598 }
599#endif
600 if (ppc_md.progress)
601 ppc_md.progress("pplus_setup_arch: exit", 0);
602}
603
604static void pplus_restart(char *cmd)
605{
606 unsigned long i = 10000;
607
608 local_irq_disable();
609
610 /* set VIA IDE controller into native mode */
611 pplus_set_VIA_IDE_native();
612
613 /* set exception prefix high - to the prom */
614 _nmask_and_or_msr(0, MSR_IP);
615
616 /* make sure bit 0 (reset) is a 0 */
617 outb(inb(0x92) & ~1L, 0x92);
618 /* signal a reset to system control port A - soft reset */
619 outb(inb(0x92) | 1, 0x92);
620
621 while (i != 0)
622 i++;
623 panic("restart failed\n");
624}
625
626static void pplus_halt(void)
627{
628 /* set exception prefix high - to the prom */
629 _nmask_and_or_msr(MSR_EE, MSR_IP);
630
631 /* make sure bit 0 (reset) is a 0 */
632 outb(inb(0x92) & ~1L, 0x92);
633 /* signal a reset to system control port A - soft reset */
634 outb(inb(0x92) | 1, 0x92);
635
636 while (1) ;
637 /*
638 * Not reached
639 */
640}
641
642static void pplus_power_off(void)
643{
644 pplus_halt();
645}
646
1da177e4
LT		 647static void __init pplus_init_IRQ(void)
648{
649 int i;
650
651 if (ppc_md.progress)
652 ppc_md.progress("init_irq: enter", 0);
653
654 OpenPIC_InitSenses = pplus_openpic_initsenses;
655 OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
656
657 if (OpenPIC_Addr != NULL) {
658
659 openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
660 openpic_init(NUM_8259_INTERRUPTS);
661 openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
662 i8259_irq);
663 ppc_md.get_irq = openpic_get_irq;
664 }
665
f9bd170a 666 i8259_init(0, 0);
1da177e4
LT		 667
668 if (ppc_md.progress)
669 ppc_md.progress("init_irq: exit", 0);
670}
671
672#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
673/*
674 * IDE stuff.
675 */
676static int pplus_ide_default_irq(unsigned long base)
677{
678 switch (base) {
679 case 0x1f0:
680 return 14;
681 case 0x170:
682 return 15;
683 default:
684 return 0;
685 }
686}
687
688static unsigned long pplus_ide_default_io_base(int index)
689{
690 switch (index) {
691 case 0:
692 return 0x1f0;
693 case 1:
694 return 0x170;
695 default:
696 return 0;
697 }
698}
699
700static void __init
701pplus_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
702 unsigned long ctrl_port, int *irq)
703{
704 unsigned long reg = data_port;
705 int i;
706
707 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
708 hw->io_ports[i] = reg;
709 reg += 1;
710 }
711
712 if (ctrl_port)
713 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
714 else
715 hw->io_ports[IDE_CONTROL_OFFSET] =
716 hw->io_ports[IDE_DATA_OFFSET] + 0x206;
717
718 if (irq != NULL)
719 *irq = pplus_ide_default_irq(data_port);
720}
721#endif
722
723#ifdef CONFIG_SMP
724/* PowerPlus (MTX) support */
725static int __init smp_pplus_probe(void)
726{
727 extern int mot_multi;
728
729 if (mot_multi) {
730 openpic_request_IPIs();
731 smp_hw_index[1] = 1;
732 return 2;
733 }
734
735 return 1;
736}
737
738static void __init smp_pplus_kick_cpu(int nr)
739{
740 *(unsigned long *)KERNELBASE = nr;
741 asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
742 printk(KERN_INFO "CPU1 reset, waiting\n");
743}
744
745static void __init smp_pplus_setup_cpu(int cpu_nr)
746{
747 if (OpenPIC_Addr)
748 do_openpic_setup_cpu();
749}
750
751static struct smp_ops_t pplus_smp_ops = {
752 smp_openpic_message_pass,
753 smp_pplus_probe,
754 smp_pplus_kick_cpu,
755 smp_pplus_setup_cpu,
756 .give_timebase = smp_generic_give_timebase,
757 .take_timebase = smp_generic_take_timebase,
758};
759#endif /* CONFIG_SMP */
760
761#ifdef DUMP_DBATS
762static void print_dbat(int idx, u32 bat)
763{
764
765 char str[64];
766
767 sprintf(str, "DBAT%c%c = 0x%08x\n",
768 (char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat);
769 ppc_md.progress(str, 0);
770}
771
772#define DUMP_DBAT(x) \
773 do { \
774 u32 __temp = mfspr(x);\
775 print_dbat(x, __temp); \
776 } while (0)
777
778static void dump_dbats(void)
779{
780 if (ppc_md.progress) {
781 DUMP_DBAT(DBAT0U);
782 DUMP_DBAT(DBAT0L);
783 DUMP_DBAT(DBAT1U);
784 DUMP_DBAT(DBAT1L);
785 DUMP_DBAT(DBAT2U);
786 DUMP_DBAT(DBAT2L);
787 DUMP_DBAT(DBAT3U);
788 DUMP_DBAT(DBAT3L);
789 }
790}
791#endif
792
793static unsigned long __init pplus_find_end_of_memory(void)
794{
795 unsigned long total;
796
797 if (ppc_md.progress)
798 ppc_md.progress("pplus_find_end_of_memory", 0);
799
800#ifdef DUMP_DBATS
801 dump_dbats();
802#endif
803
804 total = hawk_get_mem_size(PPLUS_HAWK_SMC_BASE);
805 return (total);
806}
807
808static void __init pplus_map_io(void)
809{
810 io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
811 _PAGE_IO);
812 io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
813}
814
815static void __init pplus_init2(void)
816{
817#ifdef CONFIG_NVRAM
818 request_region(PREP_NVRAM_AS0, 0x8, "nvram");
819#endif
820 request_region(0x20, 0x20, "pic1");
821 request_region(0xa0, 0x20, "pic2");
822 request_region(0x00, 0x20, "dma1");
823 request_region(0x40, 0x20, "timer");
824 request_region(0x80, 0x10, "dma page reg");
825 request_region(0xc0, 0x20, "dma2");
826}
827
828/*
829 * Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
830 * to 0xf0000000 to access Falcon/Raven or Hawk registers
831 */
832static __inline__ void pplus_set_bat(void)
833{
834 /* wait for all outstanding memory accesses to complete */
835 mb();
836
837 /* setup DBATs */
838 mtspr(SPRN_DBAT2U, 0x80001ffe);
839 mtspr(SPRN_DBAT2L, 0x8000002a);
840 mtspr(SPRN_DBAT3U, 0xf0001ffe);
841 mtspr(SPRN_DBAT3L, 0xf000002a);
842
843 /* wait for updates */
844 mb();
845}
846
847void __init
848platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
849 unsigned long r6, unsigned long r7)
850{
851 parse_bootinfo(find_bootinfo());
852
853 /* Map in board regs, etc. */
854 pplus_set_bat();
855
856 isa_io_base = PREP_ISA_IO_BASE;
857 isa_mem_base = PREP_ISA_MEM_BASE;
858 pci_dram_offset = PREP_PCI_DRAM_OFFSET;
859 ISA_DMA_THRESHOLD = 0x00ffffff;
860 DMA_MODE_READ = 0x44;
861 DMA_MODE_WRITE = 0x48;
35d81a4b 862 ppc_do_canonicalize_irqs = 1;
1da177e4
LT		 863
864 ppc_md.setup_arch = pplus_setup_arch;
865 ppc_md.show_cpuinfo = pplus_show_cpuinfo;
1da177e4
LT		 866 ppc_md.init_IRQ = pplus_init_IRQ;
867 /* this gets changed later on if we have an OpenPIC -- Cort */
868 ppc_md.get_irq = i8259_irq;
869 ppc_md.init = pplus_init2;
870
871 ppc_md.restart = pplus_restart;
872 ppc_md.power_off = pplus_power_off;
873 ppc_md.halt = pplus_halt;
874
875 TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
876 PREP_NVRAM_DATA, 8);
877
878 ppc_md.time_init = todc_time_init;
879 ppc_md.set_rtc_time = todc_set_rtc_time;
880 ppc_md.get_rtc_time = todc_get_rtc_time;
881 ppc_md.calibrate_decr = todc_calibrate_decr;
882 ppc_md.nvram_read_val = todc_m48txx_read_val;
883 ppc_md.nvram_write_val = todc_m48txx_write_val;
884
885 ppc_md.find_end_of_memory = pplus_find_end_of_memory;
886 ppc_md.setup_io_mappings = pplus_map_io;
887
888#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
889 ppc_ide_md.default_irq = pplus_ide_default_irq;
890 ppc_ide_md.default_io_base = pplus_ide_default_io_base;
891 ppc_ide_md.ide_init_hwif = pplus_ide_init_hwif_ports;
892#endif
893
894#ifdef CONFIG_SERIAL_TEXT_DEBUG
895 ppc_md.progress = gen550_progress;
896#endif /* CONFIG_SERIAL_TEXT_DEBUG */
897#ifdef CONFIG_KGDB
898 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
899#endif
900#ifdef CONFIG_SMP
7ed476d1 901 smp_ops = &pplus_smp_ops;
1da177e4
LT		 902#endif /* CONFIG_SMP */
903}
Linux kernel - Deliverables
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