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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Interrupt controller support for Marvell's MV64360. |
3 | * | |
4 | * Author: Rabeeh Khoury <rabeeh@galileo.co.il> | |
5 | * Based on MV64360 PIC written by | |
6 | * Chris Zankel <chris@mvista.com> | |
7 | * Mark A. Greer <mgreer@mvista.com> | |
8 | * | |
9 | * Copyright 2004 MontaVista Software, Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * This file contains the specific functions to support the MV64360 | |
19 | * interrupt controller. | |
20 | * | |
21 | * The MV64360 has two main interrupt registers (high and low) that | |
22 | * summarizes the interrupts generated by the units of the MV64360. | |
23 | * Each bit is assigned to an interrupt number, where the low register | |
24 | * are assigned from IRQ0 to IRQ31 and the high cause register | |
25 | * from IRQ32 to IRQ63 | |
26 | * The GPP (General Purpose Pins) interrupts are assigned from IRQ64 (GPP0) | |
27 | * to IRQ95 (GPP31). | |
28 | * get_irq() returns the lowest interrupt number that is currently asserted. | |
29 | * | |
30 | * Note: | |
31 | * - This driver does not initialize the GPP when used as an interrupt | |
32 | * input. | |
33 | */ | |
34 | ||
35 | #include <linux/stddef.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/sched.h> | |
38 | #include <linux/signal.h> | |
39 | #include <linux/stddef.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/irq.h> | |
42 | #include <linux/interrupt.h> | |
43 | ||
44 | #include <asm/io.h> | |
45 | #include <asm/processor.h> | |
46 | #include <asm/system.h> | |
47 | #include <asm/irq.h> | |
48 | #include <asm/mv64x60.h> | |
fd582ec8 | 49 | #include <asm/machdep.h> |
1da177e4 LT |
50 | |
51 | #ifdef CONFIG_IRQ_ALL_CPUS | |
52 | #error "The mv64360 does not support distribution of IRQs on all CPUs" | |
53 | #endif | |
54 | /* ========================== forward declaration ========================== */ | |
55 | ||
56 | static void mv64360_unmask_irq(unsigned int); | |
57 | static void mv64360_mask_irq(unsigned int); | |
58 | static irqreturn_t mv64360_cpu_error_int_handler(int, void *, struct pt_regs *); | |
59 | static irqreturn_t mv64360_sram_error_int_handler(int, void *, | |
60 | struct pt_regs *); | |
61 | static irqreturn_t mv64360_pci_error_int_handler(int, void *, struct pt_regs *); | |
62 | ||
63 | /* ========================== local declarations =========================== */ | |
64 | ||
65 | struct hw_interrupt_type mv64360_pic = { | |
66 | .typename = " mv64360 ", | |
67 | .enable = mv64360_unmask_irq, | |
68 | .disable = mv64360_mask_irq, | |
69 | .ack = mv64360_mask_irq, | |
70 | .end = mv64360_unmask_irq, | |
71 | }; | |
72 | ||
73 | #define CPU_INTR_STR "mv64360 cpu interface error" | |
74 | #define SRAM_INTR_STR "mv64360 internal sram error" | |
75 | #define PCI0_INTR_STR "mv64360 pci 0 error" | |
76 | #define PCI1_INTR_STR "mv64360 pci 1 error" | |
77 | ||
78 | static struct mv64x60_handle bh; | |
79 | ||
80 | u32 mv64360_irq_base = 0; /* MV64360 handles the next 96 IRQs from here */ | |
81 | ||
82 | /* mv64360_init_irq() | |
83 | * | |
84 | * This function initializes the interrupt controller. It assigns | |
85 | * all interrupts from IRQ0 to IRQ95 to the mv64360 interrupt controller. | |
86 | * | |
87 | * Input Variable(s): | |
88 | * None. | |
89 | * | |
90 | * Outpu. Variable(s): | |
91 | * None. | |
92 | * | |
93 | * Returns: | |
94 | * void | |
95 | * | |
96 | * Note: | |
97 | * We register all GPP inputs as interrupt source, but disable them. | |
98 | */ | |
99 | void __init | |
100 | mv64360_init_irq(void) | |
101 | { | |
102 | int i; | |
103 | ||
104 | if (ppc_md.progress) | |
105 | ppc_md.progress("mv64360_init_irq: enter", 0x0); | |
106 | ||
107 | bh.v_base = mv64x60_get_bridge_vbase(); | |
108 | ||
109 | ppc_cached_irq_mask[0] = 0; | |
110 | ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */ | |
111 | ppc_cached_irq_mask[2] = 0; | |
112 | ||
113 | /* disable all interrupts and clear current interrupts */ | |
114 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, 0); | |
115 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]); | |
116 | mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,ppc_cached_irq_mask[0]); | |
117 | mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,ppc_cached_irq_mask[1]); | |
118 | ||
119 | /* All interrupts are level interrupts */ | |
120 | for (i = mv64360_irq_base; i < (mv64360_irq_base + 96); i++) { | |
121 | irq_desc[i].status |= IRQ_LEVEL; | |
122 | irq_desc[i].handler = &mv64360_pic; | |
123 | } | |
124 | ||
125 | if (ppc_md.progress) | |
126 | ppc_md.progress("mv64360_init_irq: exit", 0x0); | |
127 | } | |
128 | ||
129 | /* mv64360_get_irq() | |
130 | * | |
131 | * This function returns the lowest interrupt number of all interrupts that | |
132 | * are currently asserted. | |
133 | * | |
134 | * Input Variable(s): | |
135 | * struct pt_regs* not used | |
136 | * | |
137 | * Output Variable(s): | |
138 | * None. | |
139 | * | |
140 | * Returns: | |
141 | * int <interrupt number> or -2 (bogus interrupt) | |
142 | * | |
143 | */ | |
144 | int | |
145 | mv64360_get_irq(struct pt_regs *regs) | |
146 | { | |
147 | int irq; | |
148 | int irq_gpp; | |
149 | ||
150 | #ifdef CONFIG_SMP | |
151 | /* | |
152 | * Second CPU gets only doorbell (message) interrupts. | |
153 | * The doorbell interrupt is BIT28 in the main interrupt low cause reg. | |
154 | */ | |
155 | int cpu_nr = smp_processor_id(); | |
156 | if (cpu_nr == 1) { | |
157 | if (!(mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO) & | |
158 | (1 << MV64x60_IRQ_DOORBELL))) | |
159 | return -1; | |
160 | return mv64360_irq_base + MV64x60_IRQ_DOORBELL; | |
161 | } | |
162 | #endif | |
163 | ||
164 | irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_LO); | |
165 | irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]); | |
166 | ||
167 | if (irq == -1) { | |
168 | irq = mv64x60_read(&bh, MV64360_IC_MAIN_CAUSE_HI); | |
169 | irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]); | |
170 | ||
171 | if (irq == -1) | |
172 | irq = -2; /* bogus interrupt, should never happen */ | |
173 | else { | |
174 | if ((irq >= 24) && (irq < MV64x60_IRQ_DOORBELL)) { | |
175 | irq_gpp = mv64x60_read(&bh, | |
176 | MV64x60_GPP_INTR_CAUSE); | |
177 | irq_gpp = __ilog2(irq_gpp & | |
178 | ppc_cached_irq_mask[2]); | |
179 | ||
180 | if (irq_gpp == -1) | |
181 | irq = -2; | |
182 | else { | |
183 | irq = irq_gpp + 64; | |
184 | mv64x60_write(&bh, | |
185 | MV64x60_GPP_INTR_CAUSE, | |
186 | ~(1 << (irq - 64))); | |
187 | } | |
188 | } | |
189 | else | |
190 | irq += 32; | |
191 | } | |
192 | } | |
193 | ||
194 | (void)mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE); | |
195 | ||
196 | if (irq < 0) | |
197 | return (irq); | |
198 | else | |
199 | return (mv64360_irq_base + irq); | |
200 | } | |
201 | ||
202 | /* mv64360_unmask_irq() | |
203 | * | |
204 | * This function enables an interrupt. | |
205 | * | |
206 | * Input Variable(s): | |
207 | * unsigned int interrupt number (IRQ0...IRQ95). | |
208 | * | |
209 | * Output Variable(s): | |
210 | * None. | |
211 | * | |
212 | * Returns: | |
213 | * void | |
214 | */ | |
215 | static void | |
216 | mv64360_unmask_irq(unsigned int irq) | |
217 | { | |
218 | #ifdef CONFIG_SMP | |
219 | /* second CPU gets only doorbell interrupts */ | |
220 | if ((irq - mv64360_irq_base) == MV64x60_IRQ_DOORBELL) { | |
221 | mv64x60_set_bits(&bh, MV64360_IC_CPU1_INTR_MASK_LO, | |
222 | (1 << MV64x60_IRQ_DOORBELL)); | |
223 | return; | |
224 | } | |
225 | #endif | |
226 | irq -= mv64360_irq_base; | |
227 | ||
228 | if (irq > 31) { | |
229 | if (irq > 63) /* unmask GPP irq */ | |
230 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, | |
231 | ppc_cached_irq_mask[2] |= (1 << (irq - 64))); | |
232 | else /* mask high interrupt register */ | |
233 | mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, | |
234 | ppc_cached_irq_mask[1] |= (1 << (irq - 32))); | |
235 | } | |
236 | else /* mask low interrupt register */ | |
237 | mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO, | |
238 | ppc_cached_irq_mask[0] |= (1 << irq)); | |
239 | ||
240 | (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); | |
241 | return; | |
242 | } | |
243 | ||
244 | /* mv64360_mask_irq() | |
245 | * | |
246 | * This function disables the requested interrupt. | |
247 | * | |
248 | * Input Variable(s): | |
249 | * unsigned int interrupt number (IRQ0...IRQ95). | |
250 | * | |
251 | * Output Variable(s): | |
252 | * None. | |
253 | * | |
254 | * Returns: | |
255 | * void | |
256 | */ | |
257 | static void | |
258 | mv64360_mask_irq(unsigned int irq) | |
259 | { | |
260 | #ifdef CONFIG_SMP | |
261 | if ((irq - mv64360_irq_base) == MV64x60_IRQ_DOORBELL) { | |
262 | mv64x60_clr_bits(&bh, MV64360_IC_CPU1_INTR_MASK_LO, | |
263 | (1 << MV64x60_IRQ_DOORBELL)); | |
264 | return; | |
265 | } | |
266 | #endif | |
267 | irq -= mv64360_irq_base; | |
268 | ||
269 | if (irq > 31) { | |
270 | if (irq > 63) /* mask GPP irq */ | |
271 | mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, | |
272 | ppc_cached_irq_mask[2] &= ~(1 << (irq - 64))); | |
273 | else /* mask high interrupt register */ | |
274 | mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, | |
275 | ppc_cached_irq_mask[1] &= ~(1 << (irq - 32))); | |
276 | } | |
277 | else /* mask low interrupt register */ | |
278 | mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO, | |
279 | ppc_cached_irq_mask[0] &= ~(1 << irq)); | |
280 | ||
281 | (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK); | |
282 | return; | |
283 | } | |
284 | ||
285 | static irqreturn_t | |
286 | mv64360_cpu_error_int_handler(int irq, void *dev_id, struct pt_regs *regs) | |
287 | { | |
288 | printk(KERN_ERR "mv64360_cpu_error_int_handler: %s 0x%08x\n", | |
289 | "Error on CPU interface - Cause regiser", | |
290 | mv64x60_read(&bh, MV64x60_CPU_ERR_CAUSE)); | |
291 | printk(KERN_ERR "\tCPU error register dump:\n"); | |
292 | printk(KERN_ERR "\tAddress low 0x%08x\n", | |
293 | mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_LO)); | |
294 | printk(KERN_ERR "\tAddress high 0x%08x\n", | |
295 | mv64x60_read(&bh, MV64x60_CPU_ERR_ADDR_HI)); | |
296 | printk(KERN_ERR "\tData low 0x%08x\n", | |
297 | mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_LO)); | |
298 | printk(KERN_ERR "\tData high 0x%08x\n", | |
299 | mv64x60_read(&bh, MV64x60_CPU_ERR_DATA_HI)); | |
300 | printk(KERN_ERR "\tParity 0x%08x\n", | |
301 | mv64x60_read(&bh, MV64x60_CPU_ERR_PARITY)); | |
302 | mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); | |
303 | return IRQ_HANDLED; | |
304 | } | |
305 | ||
306 | static irqreturn_t | |
307 | mv64360_sram_error_int_handler(int irq, void *dev_id, struct pt_regs *regs) | |
308 | { | |
309 | printk(KERN_ERR "mv64360_sram_error_int_handler: %s 0x%08x\n", | |
310 | "Error in internal SRAM - Cause register", | |
311 | mv64x60_read(&bh, MV64360_SRAM_ERR_CAUSE)); | |
312 | printk(KERN_ERR "\tSRAM error register dump:\n"); | |
313 | printk(KERN_ERR "\tAddress Low 0x%08x\n", | |
314 | mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_LO)); | |
315 | printk(KERN_ERR "\tAddress High 0x%08x\n", | |
316 | mv64x60_read(&bh, MV64360_SRAM_ERR_ADDR_HI)); | |
317 | printk(KERN_ERR "\tData Low 0x%08x\n", | |
318 | mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_LO)); | |
319 | printk(KERN_ERR "\tData High 0x%08x\n", | |
320 | mv64x60_read(&bh, MV64360_SRAM_ERR_DATA_HI)); | |
321 | printk(KERN_ERR "\tParity 0x%08x\n", | |
322 | mv64x60_read(&bh, MV64360_SRAM_ERR_PARITY)); | |
323 | mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0); | |
324 | return IRQ_HANDLED; | |
325 | } | |
326 | ||
327 | static irqreturn_t | |
328 | mv64360_pci_error_int_handler(int irq, void *dev_id, struct pt_regs *regs) | |
329 | { | |
330 | u32 val; | |
331 | unsigned int pci_bus = (unsigned int)dev_id; | |
332 | ||
333 | if (pci_bus == 0) { /* Error on PCI 0 */ | |
334 | val = mv64x60_read(&bh, MV64x60_PCI0_ERR_CAUSE); | |
335 | printk(KERN_ERR "%s: Error in PCI %d Interface\n", | |
336 | "mv64360_pci_error_int_handler", pci_bus); | |
337 | printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus); | |
338 | printk(KERN_ERR "\tCause register 0x%08x\n", val); | |
339 | printk(KERN_ERR "\tAddress Low 0x%08x\n", | |
340 | mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_LO)); | |
341 | printk(KERN_ERR "\tAddress High 0x%08x\n", | |
342 | mv64x60_read(&bh, MV64x60_PCI0_ERR_ADDR_HI)); | |
343 | printk(KERN_ERR "\tAttribute 0x%08x\n", | |
344 | mv64x60_read(&bh, MV64x60_PCI0_ERR_DATA_LO)); | |
345 | printk(KERN_ERR "\tCommand 0x%08x\n", | |
346 | mv64x60_read(&bh, MV64x60_PCI0_ERR_CMD)); | |
347 | mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, ~val); | |
348 | } | |
349 | if (pci_bus == 1) { /* Error on PCI 1 */ | |
350 | val = mv64x60_read(&bh, MV64x60_PCI1_ERR_CAUSE); | |
351 | printk(KERN_ERR "%s: Error in PCI %d Interface\n", | |
352 | "mv64360_pci_error_int_handler", pci_bus); | |
353 | printk(KERN_ERR "\tPCI %d error register dump:\n", pci_bus); | |
354 | printk(KERN_ERR "\tCause register 0x%08x\n", val); | |
355 | printk(KERN_ERR "\tAddress Low 0x%08x\n", | |
356 | mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_LO)); | |
357 | printk(KERN_ERR "\tAddress High 0x%08x\n", | |
358 | mv64x60_read(&bh, MV64x60_PCI1_ERR_ADDR_HI)); | |
359 | printk(KERN_ERR "\tAttribute 0x%08x\n", | |
360 | mv64x60_read(&bh, MV64x60_PCI1_ERR_DATA_LO)); | |
361 | printk(KERN_ERR "\tCommand 0x%08x\n", | |
362 | mv64x60_read(&bh, MV64x60_PCI1_ERR_CMD)); | |
363 | mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, ~val); | |
364 | } | |
365 | return IRQ_HANDLED; | |
366 | } | |
367 | ||
d01c08c9 MG |
368 | /* |
369 | * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of | |
370 | * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as | |
371 | * well. IOW, don't set bit 0. | |
372 | */ | |
373 | #define MV64360_PCI0_ERR_MASK_VAL 0x00a50c24 | |
374 | ||
1da177e4 LT |
375 | static int __init |
376 | mv64360_register_hdlrs(void) | |
377 | { | |
1da177e4 LT |
378 | int rc; |
379 | ||
380 | /* Clear old errors and register CPU interface error intr handler */ | |
381 | mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0); | |
382 | if ((rc = request_irq(MV64x60_IRQ_CPU_ERR + mv64360_irq_base, | |
383 | mv64360_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0))) | |
384 | printk(KERN_WARNING "Can't register cpu error handler: %d", rc); | |
385 | ||
386 | mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0); | |
387 | mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff); | |
388 | ||
389 | /* Clear old errors and register internal SRAM error intr handler */ | |
390 | mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0); | |
391 | if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR + mv64360_irq_base, | |
392 | mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0))) | |
393 | printk(KERN_WARNING "Can't register SRAM error handler: %d",rc); | |
394 | ||
1da177e4 LT |
395 | /* Clear old errors and register PCI 0 error intr handler */ |
396 | mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0); | |
397 | if ((rc = request_irq(MV64360_IRQ_PCI0 + mv64360_irq_base, | |
398 | mv64360_pci_error_int_handler, | |
399 | SA_INTERRUPT, PCI0_INTR_STR, (void *)0))) | |
400 | printk(KERN_WARNING "Can't register pci 0 error handler: %d", | |
401 | rc); | |
402 | ||
403 | mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0); | |
d01c08c9 MG |
404 | mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL); |
405 | ||
406 | /* Erratum FEr PCI-#16 says to clear bit 0 of PCI SERRn Mask reg. */ | |
407 | mv64x60_write(&bh, MV64x60_PCI0_ERR_SERR_MASK, | |
408 | mv64x60_read(&bh, MV64x60_PCI0_ERR_SERR_MASK) & ~0x1UL); | |
1da177e4 LT |
409 | |
410 | /* Clear old errors and register PCI 1 error intr handler */ | |
411 | mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0); | |
412 | if ((rc = request_irq(MV64360_IRQ_PCI1 + mv64360_irq_base, | |
413 | mv64360_pci_error_int_handler, | |
414 | SA_INTERRUPT, PCI1_INTR_STR, (void *)1))) | |
415 | printk(KERN_WARNING "Can't register pci 1 error handler: %d", | |
416 | rc); | |
417 | ||
418 | mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0); | |
d01c08c9 MG |
419 | mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, MV64360_PCI0_ERR_MASK_VAL); |
420 | ||
421 | /* Erratum FEr PCI-#16 says to clear bit 0 of PCI Intr Mask reg. */ | |
422 | mv64x60_write(&bh, MV64x60_PCI1_ERR_SERR_MASK, | |
423 | mv64x60_read(&bh, MV64x60_PCI1_ERR_SERR_MASK) & ~0x1UL); | |
1da177e4 LT |
424 | |
425 | return 0; | |
426 | } | |
427 | ||
428 | arch_initcall(mv64360_register_hdlrs); |