[deliverable/linux.git] / arch / ppc64 / kernel / cpu_setup_power4.S

/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <linux/config.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/ppc_asm.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/offsets.h>
#include <asm/cache.h>

_GLOBAL(__970_cpu_preinit)
	/*
	 * Do nothing if not running in HV mode
	 */
	mfmsr	r0
	rldicl.	r0,r0,4,63
	beqlr

	/*
	 * Deal only with PPC970 and PPC970FX.
	 */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	r0,0x39
	beq	1f
	cmpwi	r0,0x3c
	beq	1f
	cmpwi	r0,0x44
	bnelr
1:

	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
	 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
	 * HID5:DCBZ32_ill
	 */
	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	rldimi	r3,r0,2,61	/* clear bit 61 (lg_pg_en) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync
	mfspr	r3,SPRN_HID5
	rldimi	r3,r0,6,56	/* clear bits 56 & 57 (DCBZ*) */
	sync
	mtspr	SPRN_HID5,r3
	isync
	sync

	/* Setup some basic HID1 features */
	mfspr	r0,SPRN_HID1
	li	r3,0x1200		/* enable i-fetch cacheability */
	sldi	r3,r3,44		/* and prefetch */
	or	r0,r0,r3
	mtspr	SPRN_HID1,r0
	mtspr	SPRN_HID1,r0
	isync

	/* Clear HIOR */
	li	r0,0
	sync
	mtspr	SPRN_HIOR,0		/* Clear interrupt prefix */
	isync
	blr

_GLOBAL(__setup_cpu_power4)
	blr

_GLOBAL(__setup_cpu_be)
        /* Set large page sizes LP=0: 16MB, LP=1: 64KB */
        addi    r3, 0,  0
        ori     r3, r3, HID6_LB
        sldi    r3, r3, 32
        nor     r3, r3, r3
        mfspr   r4, SPRN_HID6
        and     r4, r4, r3
        addi    r3, 0, 0x02000
        sldi    r3, r3, 32
        or      r4, r4, r3
        mtspr   SPRN_HID6, r4
	blr

_GLOBAL(__setup_cpu_ppc970)
	mfspr	r0,SPRN_HID0
	li	r11,5			/* clear DOZE and SLEEP */
	rldimi	r0,r11,52,8		/* set NAP and DPM */
	mtspr	SPRN_HID0,r0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	sync
	isync
	blr

/* Definitions for the table use to save CPU states */
#define CS_HID0		0
#define CS_HID1		8
#define	CS_HID4		16
#define CS_HID5		24
#define CS_SIZE		32

	.data
	.balign	L1_CACHE_BYTES,0
cpu_state_storage:	
	.space	CS_SIZE
	.balign	L1_CACHE_BYTES,0
	.text
	
/* Called in normal context to backup CPU 0 state. This
 * does not include cache settings. This function is also
 * called for machine sleep. This does not include the MMU
 * setup, BATs, etc... but rather the "special" registers
 * like HID0, HID1, HID4, etc...
 */
_GLOBAL(__save_cpu_setup)
	/* Some CR fields are volatile, we back it up all */
	mfcr	r7

	/* Get storage ptr */
	LOADADDR(r5,cpu_state_storage)

	/* We only deal with 970 for now */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	r0,0x39
	beq	1f
	cmpwi	r0,0x3c
	beq	1f
	cmpwi	r0,0x44
	bne	2f

1:	/* Save HID0,1,4 and 5 */
	mfspr	r3,SPRN_HID0
	std	r3,CS_HID0(r5)
	mfspr	r3,SPRN_HID1
	std	r3,CS_HID1(r5)
	mfspr	r3,SPRN_HID4
	std	r3,CS_HID4(r5)
	mfspr	r3,SPRN_HID5
	std	r3,CS_HID5(r5)
	
2:
	mtcr	r7
	blr

/* Called with no MMU context (typically MSR:IR/DR off) to
 * restore CPU state as backed up by the previous
 * function. This does not include cache setting
 */
_GLOBAL(__restore_cpu_setup)
	/* Get storage ptr (FIXME when using anton reloc as we
	 * are running with translation disabled here
	 */
	LOADADDR(r5,cpu_state_storage)

	/* We only deal with 970 for now */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	r0,0x39
	beq	1f
	cmpwi	r0,0x3c
	beq	1f
	cmpwi	r0,0x44
	bnelr

1:	/* Before accessing memory, we make sure rm_ci is clear */
	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync

	/* Clear interrupt prefix */
	li	r0,0
	sync
	mtspr	SPRN_HIOR,0
	isync

	/* Restore HID0 */
	ld	r3,CS_HID0(r5)
	sync
	isync
	mtspr	SPRN_HID0,r3
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	sync
	isync

	/* Restore HID1 */
	ld	r3,CS_HID1(r5)
	sync
	isync
	mtspr	SPRN_HID1,r3
	mtspr	SPRN_HID1,r3
	sync
	isync
	
	/* Restore HID4 */
	ld	r3,CS_HID4(r5)
	sync
	isync
	mtspr	SPRN_HID4,r3
	sync
	isync

	/* Restore HID5 */
	ld	r3,CS_HID5(r5)
	sync
	isync
	mtspr	SPRN_HID5,r3
	sync
	isync
	blr
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains low level CPU setup functions.
	3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*
	10	*/
	11
	12	#include <linux/config.h>
	13	#include <asm/processor.h>
	14	#include <asm/page.h>
	15	#include <asm/ppc_asm.h>
	16	#include <asm/cputable.h>
	17	#include <asm/ppc_asm.h>
	18	#include <asm/offsets.h>
	19	#include <asm/cache.h>
	20
	21	_GLOBAL(__970_cpu_preinit)
	22	/*
	23	* Do nothing if not running in HV mode
	24	*/
	25	mfmsr r0
	26	rldicl. r0,r0,4,63
	27	beqlr
	28
	29	/*
	30	* Deal only with PPC970 and PPC970FX.
	31	*/
	32	mfspr r0,SPRN_PVR
	33	srwi r0,r0,16
f264cc28 OJ	34	cmpwi r0,0x39
	35	beq 1f
	36	cmpwi r0,0x3c
	37	beq 1f
	38	cmpwi r0,0x44
1da177e4	39	bnelr
f264cc28	40	1:
1da177e4 LT	41
	42	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
	43	* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
	44	* HID5:DCBZ32_ill
	45	*/
	46	li r0,0
	47	mfspr r3,SPRN_HID4
	48	rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
	49	rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
	50	sync
	51	mtspr SPRN_HID4,r3
	52	isync
	53	sync
	54	mfspr r3,SPRN_HID5
	55	rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ) /
	56	sync
	57	mtspr SPRN_HID5,r3
	58	isync
	59	sync
	60
	61	/* Setup some basic HID1 features */
	62	mfspr r0,SPRN_HID1
	63	li r3,0x1200 /* enable i-fetch cacheability */
	64	sldi r3,r3,44 /* and prefetch */
	65	or r0,r0,r3
	66	mtspr SPRN_HID1,r0
	67	mtspr SPRN_HID1,r0
	68	isync
	69
	70	/* Clear HIOR */
	71	li r0,0
	72	sync
	73	mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
	74	isync
	75	blr
	76
	77	_GLOBAL(__setup_cpu_power4)
	78	blr
fef1c772 AB	79
	80	_GLOBAL(__setup_cpu_be)
	81	/* Set large page sizes LP=0: 16MB, LP=1: 64KB */
	82	addi r3, 0, 0
	83	ori r3, r3, HID6_LB
	84	sldi r3, r3, 32
	85	nor r3, r3, r3
	86	mfspr r4, SPRN_HID6
	87	and r4, r4, r3
	88	addi r3, 0, 0x02000
	89	sldi r3, r3, 32
	90	or r4, r4, r3
	91	mtspr SPRN_HID6, r4
	92	blr
	93
1da177e4 LT	94	_GLOBAL(__setup_cpu_ppc970)
	95	mfspr r0,SPRN_HID0
	96	li r11,5 /* clear DOZE and SLEEP */
	97	rldimi r0,r11,52,8 /* set NAP and DPM */
	98	mtspr SPRN_HID0,r0
	99	mfspr r0,SPRN_HID0
	100	mfspr r0,SPRN_HID0
	101	mfspr r0,SPRN_HID0
	102	mfspr r0,SPRN_HID0
	103	mfspr r0,SPRN_HID0
	104	mfspr r0,SPRN_HID0
	105	sync
	106	isync
	107	blr
	108
	109	/* Definitions for the table use to save CPU states */
	110	#define CS_HID0 0
	111	#define CS_HID1 8
	112	#define CS_HID4 16
	113	#define CS_HID5 24
	114	#define CS_SIZE 32
	115
	116	.data
	117	.balign L1_CACHE_BYTES,0
	118	cpu_state_storage:
	119	.space CS_SIZE
	120	.balign L1_CACHE_BYTES,0
	121	.text
	122
	123	/* Called in normal context to backup CPU 0 state. This
	124	* does not include cache settings. This function is also
	125	* called for machine sleep. This does not include the MMU
	126	* setup, BATs, etc... but rather the "special" registers
	127	* like HID0, HID1, HID4, etc...
	128	*/
	129	_GLOBAL(__save_cpu_setup)
	130	/* Some CR fields are volatile, we back it up all */
	131	mfcr r7
	132
	133	/* Get storage ptr */
	134	LOADADDR(r5,cpu_state_storage)
	135
	136	/* We only deal with 970 for now */
	137	mfspr r0,SPRN_PVR
	138	srwi r0,r0,16
f264cc28 OJ	139	cmpwi r0,0x39
	140	beq 1f
	141	cmpwi r0,0x3c
	142	beq 1f
	143	cmpwi r0,0x44
	144	bne 2f
	145
	146	1: /* Save HID0,1,4 and 5 */
1da177e4 LT	147	mfspr r3,SPRN_HID0
	148	std r3,CS_HID0(r5)
	149	mfspr r3,SPRN_HID1
	150	std r3,CS_HID1(r5)
	151	mfspr r3,SPRN_HID4
	152	std r3,CS_HID4(r5)
	153	mfspr r3,SPRN_HID5
	154	std r3,CS_HID5(r5)
	155
f264cc28	156	2:
1da177e4 LT	157	mtcr r7
	158	blr
	159
	160	/* Called with no MMU context (typically MSR:IR/DR off) to
	161	* restore CPU state as backed up by the previous
	162	* function. This does not include cache setting
	163	*/
	164	_GLOBAL(__restore_cpu_setup)
	165	/* Get storage ptr (FIXME when using anton reloc as we
	166	* are running with translation disabled here
	167	*/
	168	LOADADDR(r5,cpu_state_storage)
	169
	170	/* We only deal with 970 for now */
	171	mfspr r0,SPRN_PVR
	172	srwi r0,r0,16
f264cc28 OJ	173	cmpwi r0,0x39
	174	beq 1f
	175	cmpwi r0,0x3c
	176	beq 1f
	177	cmpwi r0,0x44
	178	bnelr
1da177e4	179
f264cc28	180	1: /* Before accessing memory, we make sure rm_ci is clear */
1da177e4 LT	181	li r0,0
	182	mfspr r3,SPRN_HID4
	183	rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
	184	sync
	185	mtspr SPRN_HID4,r3
	186	isync
	187	sync
	188
	189	/* Clear interrupt prefix */
	190	li r0,0
	191	sync
	192	mtspr SPRN_HIOR,0
	193	isync
	194
	195	/* Restore HID0 */
	196	ld r3,CS_HID0(r5)
	197	sync
	198	isync
	199	mtspr SPRN_HID0,r3
	200	mfspr r3,SPRN_HID0
	201	mfspr r3,SPRN_HID0
	202	mfspr r3,SPRN_HID0
	203	mfspr r3,SPRN_HID0
	204	mfspr r3,SPRN_HID0
	205	mfspr r3,SPRN_HID0
	206	sync
	207	isync
	208
	209	/* Restore HID1 */
	210	ld r3,CS_HID1(r5)
	211	sync
	212	isync
	213	mtspr SPRN_HID1,r3
	214	mtspr SPRN_HID1,r3
	215	sync
	216	isync
	217
	218	/* Restore HID4 */
	219	ld r3,CS_HID4(r5)
	220	sync
	221	isync
	222	mtspr SPRN_HID4,r3
	223	sync
	224	isync
	225
	226	/* Restore HID5 */
	227	ld r3,CS_HID5(r5)
	228	sync
	229	isync
	230	mtspr SPRN_HID5,r3
	231	sync
	232	isync
1da177e4 LT	233	blr
1da177e4 LT	234