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Linux-2.6.12-rc2
[deliverable/linux.git] / arch / ppc64 / kernel / iSeries_pci.c
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1da177e4
LT		 1/*
2 * iSeries_pci.c
3 *
4 * Copyright (C) 2001 Allan Trautman, IBM Corporation
5 *
6 * iSeries specific routines for PCI.
7 *
8 * Based on code from pci.c and iSeries_pci.c 32bit
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24#include <linux/kernel.h>
25#include <linux/list.h>
26#include <linux/string.h>
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/ide.h>
30#include <linux/pci.h>
31
32#include <asm/io.h>
33#include <asm/irq.h>
34#include <asm/prom.h>
35#include <asm/machdep.h>
36#include <asm/pci-bridge.h>
37#include <asm/ppcdebug.h>
38#include <asm/iommu.h>
39
40#include <asm/iSeries/HvCallPci.h>
41#include <asm/iSeries/HvCallSm.h>
42#include <asm/iSeries/HvCallXm.h>
43#include <asm/iSeries/LparData.h>
44#include <asm/iSeries/iSeries_irq.h>
45#include <asm/iSeries/iSeries_pci.h>
46#include <asm/iSeries/mf.h>
47
48#include "pci.h"
49
50extern unsigned long io_page_mask;
51
52/*
53 * Forward declares of prototypes.
54 */
55static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn);
56static void scan_PHB_slots(struct pci_controller *Phb);
57static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel);
58static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info);
59
60LIST_HEAD(iSeries_Global_Device_List);
61
62static int DeviceCount;
63
64/* Counters and control flags. */
65static long Pci_Io_Read_Count;
66static long Pci_Io_Write_Count;
67#if 0
68static long Pci_Cfg_Read_Count;
69static long Pci_Cfg_Write_Count;
70#endif
71static long Pci_Error_Count;
72
73static int Pci_Retry_Max = 3; /* Only retry 3 times */
74static int Pci_Error_Flag = 1; /* Set Retry Error on. */
75
76static struct pci_ops iSeries_pci_ops;
77
78/*
79 * Table defines
80 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
81 */
82#define IOMM_TABLE_MAX_ENTRIES 1024
83#define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
84#define BASE_IO_MEMORY 0xE000000000000000UL
85
86static unsigned long max_io_memory = 0xE000000000000000UL;
87static long current_iomm_table_entry;
88
89/*
90 * Lookup Tables.
91 */
92static struct iSeries_Device_Node **iomm_table;
93static u8 *iobar_table;
94
95/*
96 * Static and Global variables
97 */
98static char *pci_io_text = "iSeries PCI I/O";
99static DEFINE_SPINLOCK(iomm_table_lock);
100
101/*
102 * iomm_table_initialize
103 *
104 * Allocates and initalizes the Address Translation Table and Bar
105 * Tables to get them ready for use. Must be called before any
106 * I/O space is handed out to the device BARs.
107 */
108static void iomm_table_initialize(void)
109{
110 spin_lock(&iomm_table_lock);
111 iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES,
112 GFP_KERNEL);
113 iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES,
114 GFP_KERNEL);
115 spin_unlock(&iomm_table_lock);
116 if ((iomm_table == NULL) || (iobar_table == NULL))
117 panic("PCI: I/O tables allocation failed.\n");
118}
119
120/*
121 * iomm_table_allocate_entry
122 *
123 * Adds pci_dev entry in address translation table
124 *
125 * - Allocates the number of entries required in table base on BAR
126 * size.
127 * - Allocates starting at BASE_IO_MEMORY and increases.
128 * - The size is round up to be a multiple of entry size.
129 * - CurrentIndex is incremented to keep track of the last entry.
130 * - Builds the resource entry for allocated BARs.
131 */
132static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
133{
134 struct resource *bar_res = &dev->resource[bar_num];
135 long bar_size = pci_resource_len(dev, bar_num);
136
137 /*
138 * No space to allocate, quick exit, skip Allocation.
139 */
140 if (bar_size == 0)
141 return;
142 /*
143 * Set Resource values.
144 */
145 spin_lock(&iomm_table_lock);
146 bar_res->name = pci_io_text;
147 bar_res->start =
148 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
149 bar_res->start += BASE_IO_MEMORY;
150 bar_res->end = bar_res->start + bar_size - 1;
151 /*
152 * Allocate the number of table entries needed for BAR.
153 */
154 while (bar_size > 0 ) {
155 iomm_table[current_iomm_table_entry] = dev->sysdata;
156 iobar_table[current_iomm_table_entry] = bar_num;
157 bar_size -= IOMM_TABLE_ENTRY_SIZE;
158 ++current_iomm_table_entry;
159 }
160 max_io_memory = BASE_IO_MEMORY +
161 (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry);
162 spin_unlock(&iomm_table_lock);
163}
164
165/*
166 * allocate_device_bars
167 *
168 * - Allocates ALL pci_dev BAR's and updates the resources with the
169 * BAR value. BARS with zero length will have the resources
170 * The HvCallPci_getBarParms is used to get the size of the BAR
171 * space. It calls iomm_table_allocate_entry to allocate
172 * each entry.
173 * - Loops through The Bar resources(0 - 5) including the ROM
174 * is resource(6).
175 */
176static void allocate_device_bars(struct pci_dev *dev)
177{
178 struct resource *bar_res;
179 int bar_num;
180
181 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) {
182 bar_res = &dev->resource[bar_num];
183 iomm_table_allocate_entry(dev, bar_num);
184 }
185}
186
187/*
188 * Log error information to system console.
189 * Filter out the device not there errors.
190 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
191 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
192 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
193 */
194static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
195 int AgentId, int HvRc)
196{
197 if (HvRc == 0x0302)
198 return;
199 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
200 Error_Text, Bus, SubBus, AgentId, HvRc);
201}
202
203/*
204 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
205 */
206static struct iSeries_Device_Node *build_device_node(HvBusNumber Bus,
207 HvSubBusNumber SubBus, int AgentId, int Function)
208{
209 struct iSeries_Device_Node *node;
210
211 PPCDBG(PPCDBG_BUSWALK,
212 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
213 Bus, SubBus, AgentId, Function);
214
215 node = kmalloc(sizeof(struct iSeries_Device_Node), GFP_KERNEL);
216 if (node == NULL)
217 return NULL;
218
219 memset(node, 0, sizeof(struct iSeries_Device_Node));
220 list_add_tail(&node->Device_List, &iSeries_Global_Device_List);
221#if 0
222 node->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32);
223#endif
224 node->DsaAddr.DsaAddr = 0;
225 node->DsaAddr.Dsa.busNumber = Bus;
226 node->DsaAddr.Dsa.subBusNumber = SubBus;
227 node->DsaAddr.Dsa.deviceId = 0x10;
228 node->AgentId = AgentId;
229 node->DevFn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
230 node->IoRetry = 0;
231 iSeries_Get_Location_Code(node);
232 return node;
233}
234
235/*
236 * unsigned long __init find_and_init_phbs(void)
237 *
238 * Description:
239 * This function checks for all possible system PCI host bridges that connect
240 * PCI buses. The system hypervisor is queried as to the guest partition
241 * ownership status. A pci_controller is built for any bus which is partially
242 * owned or fully owned by this guest partition.
243 */
244unsigned long __init find_and_init_phbs(void)
245{
246 struct pci_controller *phb;
247 HvBusNumber bus;
248
249 PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n");
250
251 /* Check all possible buses. */
252 for (bus = 0; bus < 256; bus++) {
253 int ret = HvCallXm_testBus(bus);
254 if (ret == 0) {
255 printk("bus %d appears to exist\n", bus);
256
257 phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
258 if (phb == NULL)
259 return -ENOMEM;
260 pci_setup_pci_controller(phb);
261
262 phb->pci_mem_offset = phb->local_number = bus;
263 phb->first_busno = bus;
264 phb->last_busno = bus;
265 phb->ops = &iSeries_pci_ops;
266
267 PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
268 phb, bus);
269
270 /* Find and connect the devices. */
271 scan_PHB_slots(phb);
272 }
273 /*
274 * Check for Unexpected Return code, a clue that something
275 * has gone wrong.
276 */
277 else if (ret != 0x0301)
278 printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
279 bus, ret);
280 }
281 return 0;
282}
283
284/*
285 * iSeries_pcibios_init
286 *
287 * Chance to initialize and structures or variable before PCI Bus walk.
288 */
289void iSeries_pcibios_init(void)
290{
291 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n");
292 iomm_table_initialize();
293 find_and_init_phbs();
294 io_page_mask = -1;
295 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n");
296}
297
298/*
299 * iSeries_pci_final_fixup(void)
300 */
301void __init iSeries_pci_final_fixup(void)
302{
303 struct pci_dev *pdev = NULL;
304 struct iSeries_Device_Node *node;
305 char Buffer[256];
306 int DeviceCount = 0;
307
308 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n");
309
310 /* Fix up at the device node and pci_dev relationship */
311 mf_display_src(0xC9000100);
312
313 printk("pcibios_final_fixup\n");
314 for_each_pci_dev(pdev) {
315 node = find_Device_Node(pdev->bus->number, pdev->devfn);
316 printk("pci dev %p (%x.%x), node %p\n", pdev,
317 pdev->bus->number, pdev->devfn, node);
318
319 if (node != NULL) {
320 ++DeviceCount;
321 pdev->sysdata = (void *)node;
322 node->PciDev = pdev;
323 PPCDBG(PPCDBG_BUSWALK,
324 "pdev 0x%p <==> DevNode 0x%p\n",
325 pdev, node);
326 allocate_device_bars(pdev);
327 iSeries_Device_Information(pdev, Buffer,
328 sizeof(Buffer));
329 printk("%d. %s\n", DeviceCount, Buffer);
330 iommu_devnode_init_iSeries(node);
331 } else
332 printk("PCI: Device Tree not found for 0x%016lX\n",
333 (unsigned long)pdev);
334 pdev->irq = node->Irq;
335 }
336 iSeries_activate_IRQs();
337 mf_display_src(0xC9000200);
338}
339
340void pcibios_fixup_bus(struct pci_bus *PciBus)
341{
342 PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
343 PciBus->number);
344}
345
346void pcibios_fixup_resources(struct pci_dev *pdev)
347{
348 PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev);
349}
350
351/*
352 * Loop through each node function to find usable EADs bridges.
353 */
354static void scan_PHB_slots(struct pci_controller *Phb)
355{
356 struct HvCallPci_DeviceInfo *DevInfo;
357 HvBusNumber bus = Phb->local_number; /* System Bus */
358 const HvSubBusNumber SubBus = 0; /* EADs is always 0. */
359 int HvRc = 0;
360 int IdSel;
361 const int MaxAgents = 8;
362
363 DevInfo = (struct HvCallPci_DeviceInfo*)
364 kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
365 if (DevInfo == NULL)
366 return;
367
368 /*
369 * Probe for EADs Bridges
370 */
371 for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
372 HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
373 ISERIES_HV_ADDR(DevInfo),
374 sizeof(struct HvCallPci_DeviceInfo));
375 if (HvRc == 0) {
376 if (DevInfo->deviceType == HvCallPci_NodeDevice)
377 scan_EADS_bridge(bus, SubBus, IdSel);
378 else
379 printk("PCI: Invalid System Configuration(0x%02X)"
380 " for bus 0x%02x id 0x%02x.\n",
381 DevInfo->deviceType, bus, IdSel);
382 }
383 else
384 pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
385 }
386 kfree(DevInfo);
387}
388
389static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus,
390 int IdSel)
391{
392 struct HvCallPci_BridgeInfo *BridgeInfo;
393 HvAgentId AgentId;
394 int Function;
395 int HvRc;
396
397 BridgeInfo = (struct HvCallPci_BridgeInfo *)
398 kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
399 if (BridgeInfo == NULL)
400 return;
401
402 /* Note: hvSubBus and irq is always be 0 at this level! */
403 for (Function = 0; Function < 8; ++Function) {
404 AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
405 HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
406 if (HvRc == 0) {
407 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
408 bus, IdSel, Function, AgentId);
409 /* Connect EADs: 0x18.00.12 = 0x00 */
410 PPCDBG(PPCDBG_BUSWALK,
411 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
412 bus, SubBus, AgentId);
413 HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
414 ISERIES_HV_ADDR(BridgeInfo),
415 sizeof(struct HvCallPci_BridgeInfo));
416 if (HvRc == 0) {
417 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
418 BridgeInfo->busUnitInfo.deviceType,
419 BridgeInfo->subBusNumber,
420 BridgeInfo->maxAgents,
421 BridgeInfo->maxSubBusNumber,
422 BridgeInfo->logicalSlotNumber);
423 PPCDBG(PPCDBG_BUSWALK,
424 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
425 BridgeInfo->busUnitInfo.deviceType,
426 BridgeInfo->subBusNumber,
427 BridgeInfo->maxAgents,
428 BridgeInfo->maxSubBusNumber,
429 BridgeInfo->logicalSlotNumber);
430
431 if (BridgeInfo->busUnitInfo.deviceType ==
432 HvCallPci_BridgeDevice) {
433 /* Scan_Bridge_Slot...: 0x18.00.12 */
434 scan_bridge_slot(bus, BridgeInfo);
435 } else
436 printk("PCI: Invalid Bridge Configuration(0x%02X)",
437 BridgeInfo->busUnitInfo.deviceType);
438 }
439 } else if (HvRc != 0x000B)
440 pci_Log_Error("EADs Connect",
441 bus, SubBus, AgentId, HvRc);
442 }
443 kfree(BridgeInfo);
444}
445
446/*
447 * This assumes that the node slot is always on the primary bus!
448 */
449static int scan_bridge_slot(HvBusNumber Bus,
450 struct HvCallPci_BridgeInfo *BridgeInfo)
451{
452 struct iSeries_Device_Node *node;
453 HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
454 u16 VendorId = 0;
455 int HvRc = 0;
456 u8 Irq = 0;
457 int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
458 int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
459 HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);
460
461 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
462 Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
463 PPCDBG(PPCDBG_BUSWALK,
464 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
465 Bus, 0, EADsIdSel, Irq);
466
467 /*
468 * Connect all functions of any device found.
469 */
470 for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
471 for (Function = 0; Function < 8; ++Function) {
472 HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
473 HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
474 AgentId, Irq);
475 if (HvRc != 0) {
476 pci_Log_Error("Connect Bus Unit",
477 Bus, SubBus, AgentId, HvRc);
478 continue;
479 }
480
481 HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
482 PCI_VENDOR_ID, &VendorId);
483 if (HvRc != 0) {
484 pci_Log_Error("Read Vendor",
485 Bus, SubBus, AgentId, HvRc);
486 continue;
487 }
488 printk("read vendor ID: %x\n", VendorId);
489
490 /* FoundDevice: 0x18.28.10 = 0x12AE */
491 PPCDBG(PPCDBG_BUSWALK,
492 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
493 Bus, SubBus, AgentId, VendorId, Irq);
494 HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
495 PCI_INTERRUPT_LINE, Irq);
496 if (HvRc != 0)
497 pci_Log_Error("PciCfgStore Irq Failed!",
498 Bus, SubBus, AgentId, HvRc);
499
500 ++DeviceCount;
501 node = build_device_node(Bus, SubBus, EADsIdSel, Function);
502 node->Vendor = VendorId;
503 node->Irq = Irq;
504 node->LogicalSlot = BridgeInfo->logicalSlotNumber;
505
506 } /* for (Function = 0; Function < 8; ++Function) */
507 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
508 return HvRc;
509}
510
511/*
512 * I/0 Memory copy MUST use mmio commands on iSeries
513 * To do; For performance, include the hv call directly
514 */
515void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
516{
517 u8 ByteValue = c;
518 long NumberOfBytes = Count;
519
520 while (NumberOfBytes > 0) {
521 iSeries_Write_Byte(ByteValue, dest++);
522 -- NumberOfBytes;
523 }
524}
525EXPORT_SYMBOL(iSeries_memset_io);
526
527void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
528{
529 char *src = source;
530 long NumberOfBytes = count;
531
532 while (NumberOfBytes > 0) {
533 iSeries_Write_Byte(*src++, dest++);
534 -- NumberOfBytes;
535 }
536}
537EXPORT_SYMBOL(iSeries_memcpy_toio);
538
539void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
540{
541 char *dst = dest;
542 long NumberOfBytes = count;
543
544 while (NumberOfBytes > 0) {
545 *dst++ = iSeries_Read_Byte(src++);
546 -- NumberOfBytes;
547 }
548}
549EXPORT_SYMBOL(iSeries_memcpy_fromio);
550
551/*
552 * Look down the chain to find the matching Device Device
553 */
554static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn)
555{
556 struct list_head *pos;
557
558 list_for_each(pos, &iSeries_Global_Device_List) {
559 struct iSeries_Device_Node *node =
560 list_entry(pos, struct iSeries_Device_Node, Device_List);
561
562 if ((bus == ISERIES_BUS(node)) && (devfn == node->DevFn))
563 return node;
564 }
565 return NULL;
566}
567
568#if 0
569/*
570 * Returns the device node for the passed pci_dev
571 * Sanity Check Node PciDev to passed pci_dev
572 * If none is found, returns a NULL which the client must handle.
573 */
574static struct iSeries_Device_Node *get_Device_Node(struct pci_dev *pdev)
575{
576 struct iSeries_Device_Node *node;
577
578 node = pdev->sysdata;
579 if (node == NULL || node->PciDev != pdev)
580 node = find_Device_Node(pdev->bus->number, pdev->devfn);
581 return node;
582}
583#endif
584
585/*
586 * Config space read and write functions.
587 * For now at least, we look for the device node for the bus and devfn
588 * that we are asked to access. It may be possible to translate the devfn
589 * to a subbus and deviceid more directly.
590 */
591static u64 hv_cfg_read_func[4] = {
592 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
593 HvCallPciConfigLoad32, HvCallPciConfigLoad32
594};
595
596static u64 hv_cfg_write_func[4] = {
597 HvCallPciConfigStore8, HvCallPciConfigStore16,
598 HvCallPciConfigStore32, HvCallPciConfigStore32
599};
600
601/*
602 * Read PCI config space
603 */
604static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
605 int offset, int size, u32 *val)
606{
607 struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
608 u64 fn;
609 struct HvCallPci_LoadReturn ret;
610
611 if (node == NULL)
612 return PCIBIOS_DEVICE_NOT_FOUND;
613 if (offset > 255) {
614 *val = ~0;
615 return PCIBIOS_BAD_REGISTER_NUMBER;
616 }
617
618 fn = hv_cfg_read_func[(size - 1) & 3];
619 HvCall3Ret16(fn, &ret, node->DsaAddr.DsaAddr, offset, 0);
620
621 if (ret.rc != 0) {
622 *val = ~0;
623 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
624 }
625
626 *val = ret.value;
627 return 0;
628}
629
630/*
631 * Write PCI config space
632 */
633
634static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
635 int offset, int size, u32 val)
636{
637 struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
638 u64 fn;
639 u64 ret;
640
641 if (node == NULL)
642 return PCIBIOS_DEVICE_NOT_FOUND;
643 if (offset > 255)
644 return PCIBIOS_BAD_REGISTER_NUMBER;
645
646 fn = hv_cfg_write_func[(size - 1) & 3];
647 ret = HvCall4(fn, node->DsaAddr.DsaAddr, offset, val, 0);
648
649 if (ret != 0)
650 return PCIBIOS_DEVICE_NOT_FOUND;
651
652 return 0;
653}
654
655static struct pci_ops iSeries_pci_ops = {
656 .read = iSeries_pci_read_config,
657 .write = iSeries_pci_write_config
658};
659
660/*
661 * Check Return Code
662 * -> On Failure, print and log information.
663 * Increment Retry Count, if exceeds max, panic partition.
664 * -> If in retry, print and log success
665 *
666 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
667 * PCI: Device 23.90 ReadL Retry( 1)
668 * PCI: Device 23.90 ReadL Retry Successful(1)
669 */
670static int CheckReturnCode(char *TextHdr, struct iSeries_Device_Node *DevNode,
671 u64 ret)
672{
673 if (ret != 0) {
674 ++Pci_Error_Count;
675 ++DevNode->IoRetry;
676 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
677 TextHdr, DevNode->DsaAddr.Dsa.busNumber, DevNode->DevFn,
678 DevNode->IoRetry, (int)ret);
679 /*
680 * Bump the retry and check for retry count exceeded.
681 * If, Exceeded, panic the system.
682 */
683 if ((DevNode->IoRetry > Pci_Retry_Max) &&
684 (Pci_Error_Flag > 0)) {
685 mf_display_src(0xB6000103);
686 panic_timeout = 0;
687 panic("PCI: Hardware I/O Error, SRC B6000103, "
688 "Automatic Reboot Disabled.\n");
689 }
690 return -1; /* Retry Try */
691 }
692 /* If retry was in progress, log success and rest retry count */
693 if (DevNode->IoRetry > 0)
694 DevNode->IoRetry = 0;
695 return 0;
696}
697
698/*
699 * Translate the I/O Address into a device node, bar, and bar offset.
700 * Note: Make sure the passed variable end up on the stack to avoid
701 * the exposure of being device global.
702 */
703static inline struct iSeries_Device_Node *xlate_iomm_address(
704 const volatile void __iomem *IoAddress,
705 u64 *dsaptr, u64 *BarOffsetPtr)
706{
707 unsigned long OrigIoAddr;
708 unsigned long BaseIoAddr;
709 unsigned long TableIndex;
710 struct iSeries_Device_Node *DevNode;
711
712 OrigIoAddr = (unsigned long __force)IoAddress;
713 if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
714 return NULL;
715 BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
716 TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
717 DevNode = iomm_table[TableIndex];
718
719 if (DevNode != NULL) {
720 int barnum = iobar_table[TableIndex];
721 *dsaptr = DevNode->DsaAddr.DsaAddr | (barnum << 24);
722 *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
723 } else
724 panic("PCI: Invalid PCI IoAddress detected!\n");
725 return DevNode;
726}
727
728/*
729 * Read MM I/O Instructions for the iSeries
730 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
731 * else, data is returned in big Endian format.
732 *
733 * iSeries_Read_Byte = Read Byte ( 8 bit)
734 * iSeries_Read_Word = Read Word (16 bit)
735 * iSeries_Read_Long = Read Long (32 bit)
736 */
737u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
738{
739 u64 BarOffset;
740 u64 dsa;
741 struct HvCallPci_LoadReturn ret;
742 struct iSeries_Device_Node *DevNode =
743 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
744
745 if (DevNode == NULL) {
746 static unsigned long last_jiffies;
747 static int num_printed;
748
749 if ((jiffies - last_jiffies) > 60 * HZ) {
750 last_jiffies = jiffies;
751 num_printed = 0;
752 }
753 if (num_printed++ < 10)
754 printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
755 return 0xff;
756 }
757 do {
758 ++Pci_Io_Read_Count;
759 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
760 } while (CheckReturnCode("RDB", DevNode, ret.rc) != 0);
761
762 return (u8)ret.value;
763}
764EXPORT_SYMBOL(iSeries_Read_Byte);
765
766u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
767{
768 u64 BarOffset;
769 u64 dsa;
770 struct HvCallPci_LoadReturn ret;
771 struct iSeries_Device_Node *DevNode =
772 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
773
774 if (DevNode == NULL) {
775 static unsigned long last_jiffies;
776 static int num_printed;
777
778 if ((jiffies - last_jiffies) > 60 * HZ) {
779 last_jiffies = jiffies;
780 num_printed = 0;
781 }
782 if (num_printed++ < 10)
783 printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
784 return 0xffff;
785 }
786 do {
787 ++Pci_Io_Read_Count;
788 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
789 BarOffset, 0);
790 } while (CheckReturnCode("RDW", DevNode, ret.rc) != 0);
791
792 return swab16((u16)ret.value);
793}
794EXPORT_SYMBOL(iSeries_Read_Word);
795
796u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
797{
798 u64 BarOffset;
799 u64 dsa;
800 struct HvCallPci_LoadReturn ret;
801 struct iSeries_Device_Node *DevNode =
802 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
803
804 if (DevNode == NULL) {
805 static unsigned long last_jiffies;
806 static int num_printed;
807
808 if ((jiffies - last_jiffies) > 60 * HZ) {
809 last_jiffies = jiffies;
810 num_printed = 0;
811 }
812 if (num_printed++ < 10)
813 printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
814 return 0xffffffff;
815 }
816 do {
817 ++Pci_Io_Read_Count;
818 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
819 BarOffset, 0);
820 } while (CheckReturnCode("RDL", DevNode, ret.rc) != 0);
821
822 return swab32((u32)ret.value);
823}
824EXPORT_SYMBOL(iSeries_Read_Long);
825
826/*
827 * Write MM I/O Instructions for the iSeries
828 *
829 * iSeries_Write_Byte = Write Byte (8 bit)
830 * iSeries_Write_Word = Write Word(16 bit)
831 * iSeries_Write_Long = Write Long(32 bit)
832 */
833void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
834{
835 u64 BarOffset;
836 u64 dsa;
837 u64 rc;
838 struct iSeries_Device_Node *DevNode =
839 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
840
841 if (DevNode == NULL) {
842 static unsigned long last_jiffies;
843 static int num_printed;
844
845 if ((jiffies - last_jiffies) > 60 * HZ) {
846 last_jiffies = jiffies;
847 num_printed = 0;
848 }
849 if (num_printed++ < 10)
850 printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
851 return;
852 }
853 do {
854 ++Pci_Io_Write_Count;
855 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
856 } while (CheckReturnCode("WWB", DevNode, rc) != 0);
857}
858EXPORT_SYMBOL(iSeries_Write_Byte);
859
860void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
861{
862 u64 BarOffset;
863 u64 dsa;
864 u64 rc;
865 struct iSeries_Device_Node *DevNode =
866 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
867
868 if (DevNode == NULL) {
869 static unsigned long last_jiffies;
870 static int num_printed;
871
872 if ((jiffies - last_jiffies) > 60 * HZ) {
873 last_jiffies = jiffies;
874 num_printed = 0;
875 }
876 if (num_printed++ < 10)
877 printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
878 return;
879 }
880 do {
881 ++Pci_Io_Write_Count;
882 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
883 } while (CheckReturnCode("WWW", DevNode, rc) != 0);
884}
885EXPORT_SYMBOL(iSeries_Write_Word);
886
887void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
888{
889 u64 BarOffset;
890 u64 dsa;
891 u64 rc;
892 struct iSeries_Device_Node *DevNode =
893 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
894
895 if (DevNode == NULL) {
896 static unsigned long last_jiffies;
897 static int num_printed;
898
899 if ((jiffies - last_jiffies) > 60 * HZ) {
900 last_jiffies = jiffies;
901 num_printed = 0;
902 }
903 if (num_printed++ < 10)
904 printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
905 return;
906 }
907 do {
908 ++Pci_Io_Write_Count;
909 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
910 } while (CheckReturnCode("WWL", DevNode, rc) != 0);
911}
912EXPORT_SYMBOL(iSeries_Write_Long);
Linux kernel - Deliverables
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