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[PATCH] ppc64: Remove PTRRELOC() from msChunks code
[deliverable/linux.git] / arch / ppc64 / kernel / iSeries_setup.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
4 *
5 * Module name: iSeries_setup.c
6 *
7 * Description:
8 * Architecture- / platform-specific boot-time initialization code for
9 * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and
10 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
11 * <dan@net4x.com>.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#undef DEBUG
20
21#include <linux/config.h>
22#include <linux/init.h>
23#include <linux/threads.h>
24#include <linux/smp.h>
25#include <linux/param.h>
26#include <linux/string.h>
1da177e4
LT		 27#include <linux/initrd.h>
28#include <linux/seq_file.h>
29#include <linux/kdev_t.h>
30#include <linux/major.h>
31#include <linux/root_dev.h>
32
33#include <asm/processor.h>
34#include <asm/machdep.h>
35#include <asm/page.h>
36#include <asm/mmu.h>
37#include <asm/pgtable.h>
38#include <asm/mmu_context.h>
39#include <asm/cputable.h>
40#include <asm/sections.h>
41#include <asm/iommu.h>
aed31351 42#include <asm/firmware.h>
1da177e4
LT		 43
44#include <asm/time.h>
45#include "iSeries_setup.h"
46#include <asm/naca.h>
47#include <asm/paca.h>
48#include <asm/cache.h>
49#include <asm/sections.h>
0bc0ffd5 50#include <asm/abs_addr.h>
1da177e4
LT		 51#include <asm/iSeries/HvCallHpt.h>
52#include <asm/iSeries/HvLpConfig.h>
53#include <asm/iSeries/HvCallEvent.h>
54#include <asm/iSeries/HvCallSm.h>
55#include <asm/iSeries/HvCallXm.h>
56#include <asm/iSeries/ItLpQueue.h>
57#include <asm/iSeries/IoHriMainStore.h>
1da177e4
LT		 58#include <asm/iSeries/mf.h>
59#include <asm/iSeries/HvLpEvent.h>
60#include <asm/iSeries/iSeries_irq.h>
0bc0ffd5
SR		 61#include <asm/iSeries/IoHriProcessorVpd.h>
62#include <asm/iSeries/ItVpdAreas.h>
63#include <asm/iSeries/LparMap.h>
1da177e4
LT		 64
65extern void hvlog(char *fmt, ...);
66
67#ifdef DEBUG
68#define DBG(fmt...) hvlog(fmt)
69#else
70#define DBG(fmt...)
71#endif
72
73/* Function Prototypes */
74extern void ppcdbg_initialize(void);
75
76static void build_iSeries_Memory_Map(void);
77static void setup_iSeries_cache_sizes(void);
78static void iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr);
145d01e4 79#ifdef CONFIG_PCI
1da177e4 80extern void iSeries_pci_final_fixup(void);
145d01e4
SR		 81#else
82static void iSeries_pci_final_fixup(void) { }
83#endif
1da177e4
LT		 84
85/* Global Variables */
86static unsigned long procFreqHz;
87static unsigned long procFreqMhz;
88static unsigned long procFreqMhzHundreths;
89
90static unsigned long tbFreqHz;
91static unsigned long tbFreqMhz;
92static unsigned long tbFreqMhzHundreths;
93
94int piranha_simulator;
95
96extern int rd_size; /* Defined in drivers/block/rd.c */
97extern unsigned long klimit;
98extern unsigned long embedded_sysmap_start;
99extern unsigned long embedded_sysmap_end;
100
101extern unsigned long iSeries_recal_tb;
102extern unsigned long iSeries_recal_titan;
103
104static int mf_initialized;
105
106struct MemoryBlock {
107 unsigned long absStart;
108 unsigned long absEnd;
109 unsigned long logicalStart;
110 unsigned long logicalEnd;
111};
112
113/*
114 * Process the main store vpd to determine where the holes in memory are
115 * and return the number of physical blocks and fill in the array of
116 * block data.
117 */
118static unsigned long iSeries_process_Condor_mainstore_vpd(
119 struct MemoryBlock *mb_array, unsigned long max_entries)
120{
121 unsigned long holeFirstChunk, holeSizeChunks;
122 unsigned long numMemoryBlocks = 1;
123 struct IoHriMainStoreSegment4 *msVpd =
124 (struct IoHriMainStoreSegment4 *)xMsVpd;
125 unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr;
126 unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr;
127 unsigned long holeSize = holeEnd - holeStart;
128
129 printk("Mainstore_VPD: Condor\n");
130 /*
131 * Determine if absolute memory has any
132 * holes so that we can interpret the
133 * access map we get back from the hypervisor
134 * correctly.
135 */
136 mb_array[0].logicalStart = 0;
137 mb_array[0].logicalEnd = 0x100000000;
138 mb_array[0].absStart = 0;
139 mb_array[0].absEnd = 0x100000000;
140
141 if (holeSize) {
142 numMemoryBlocks = 2;
143 holeStart = holeStart & 0x000fffffffffffff;
144 holeStart = addr_to_chunk(holeStart);
145 holeFirstChunk = holeStart;
146 holeSize = addr_to_chunk(holeSize);
147 holeSizeChunks = holeSize;
148 printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n",
149 holeFirstChunk, holeSizeChunks );
150 mb_array[0].logicalEnd = holeFirstChunk;
151 mb_array[0].absEnd = holeFirstChunk;
152 mb_array[1].logicalStart = holeFirstChunk;
153 mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks;
154 mb_array[1].absStart = holeFirstChunk + holeSizeChunks;
155 mb_array[1].absEnd = 0x100000000;
156 }
157 return numMemoryBlocks;
158}
159
160#define MaxSegmentAreas 32
161#define MaxSegmentAdrRangeBlocks 128
162#define MaxAreaRangeBlocks 4
163
164static unsigned long iSeries_process_Regatta_mainstore_vpd(
165 struct MemoryBlock *mb_array, unsigned long max_entries)
166{
167 struct IoHriMainStoreSegment5 *msVpdP =
168 (struct IoHriMainStoreSegment5 *)xMsVpd;
169 unsigned long numSegmentBlocks = 0;
170 u32 existsBits = msVpdP->msAreaExists;
171 unsigned long area_num;
172
173 printk("Mainstore_VPD: Regatta\n");
174
175 for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) {
176 unsigned long numAreaBlocks;
177 struct IoHriMainStoreArea4 *currentArea;
178
179 if (existsBits & 0x80000000) {
180 unsigned long block_num;
181
182 currentArea = &msVpdP->msAreaArray[area_num];
183 numAreaBlocks = currentArea->numAdrRangeBlocks;
184 printk("ms_vpd: processing area %2ld blocks=%ld",
185 area_num, numAreaBlocks);
186 for (block_num = 0; block_num < numAreaBlocks;
187 ++block_num ) {
188 /* Process an address range block */
189 struct MemoryBlock tempBlock;
190 unsigned long i;
191
192 tempBlock.absStart =
193 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart;
194 tempBlock.absEnd =
195 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd;
196 tempBlock.logicalStart = 0;
197 tempBlock.logicalEnd = 0;
198 printk("\n block %ld absStart=%016lx absEnd=%016lx",
199 block_num, tempBlock.absStart,
200 tempBlock.absEnd);
201
202 for (i = 0; i < numSegmentBlocks; ++i) {
203 if (mb_array[i].absStart ==
204 tempBlock.absStart)
205 break;
206 }
207 if (i == numSegmentBlocks) {
208 if (numSegmentBlocks == max_entries)
209 panic("iSeries_process_mainstore_vpd: too many memory blocks");
210 mb_array[numSegmentBlocks] = tempBlock;
211 ++numSegmentBlocks;
212 } else
213 printk(" (duplicate)");
214 }
215 printk("\n");
216 }
217 existsBits <<= 1;
218 }
219 /* Now sort the blocks found into ascending sequence */
220 if (numSegmentBlocks > 1) {
221 unsigned long m, n;
222
223 for (m = 0; m < numSegmentBlocks - 1; ++m) {
224 for (n = numSegmentBlocks - 1; m < n; --n) {
225 if (mb_array[n].absStart <
226 mb_array[n-1].absStart) {
227 struct MemoryBlock tempBlock;
228
229 tempBlock = mb_array[n];
230 mb_array[n] = mb_array[n-1];
231 mb_array[n-1] = tempBlock;
232 }
233 }
234 }
235 }
236 /*
237 * Assign "logical" addresses to each block. These
238 * addresses correspond to the hypervisor "bitmap" space.
239 * Convert all addresses into units of 256K chunks.
240 */
241 {
242 unsigned long i, nextBitmapAddress;
243
244 printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks);
245 nextBitmapAddress = 0;
246 for (i = 0; i < numSegmentBlocks; ++i) {
247 unsigned long length = mb_array[i].absEnd -
248 mb_array[i].absStart;
249
250 mb_array[i].logicalStart = nextBitmapAddress;
251 mb_array[i].logicalEnd = nextBitmapAddress + length;
252 nextBitmapAddress += length;
253 printk(" Bitmap range: %016lx - %016lx\n"
254 " Absolute range: %016lx - %016lx\n",
255 mb_array[i].logicalStart,
256 mb_array[i].logicalEnd,
257 mb_array[i].absStart, mb_array[i].absEnd);
258 mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart &
259 0x000fffffffffffff);
260 mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd &
261 0x000fffffffffffff);
262 mb_array[i].logicalStart =
263 addr_to_chunk(mb_array[i].logicalStart);
264 mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd);
265 }
266 }
267
268 return numSegmentBlocks;
269}
270
271static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
272 unsigned long max_entries)
273{
274 unsigned long i;
275 unsigned long mem_blocks = 0;
276
277 if (cpu_has_feature(CPU_FTR_SLB))
278 mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
279 max_entries);
280 else
281 mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array,
282 max_entries);
283
284 printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks);
285 for (i = 0; i < mem_blocks; ++i) {
286 printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
287 " abs chunks %016lx - %016lx\n",
288 i, mb_array[i].logicalStart, mb_array[i].logicalEnd,
289 mb_array[i].absStart, mb_array[i].absEnd);
290 }
291 return mem_blocks;
292}
293
294static void __init iSeries_get_cmdline(void)
295{
296 char *p, *q;
297
298 /* copy the command line parameter from the primary VSP */
299 HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256,
300 HvLpDma_Direction_RemoteToLocal);
301
302 p = cmd_line;
303 q = cmd_line + 255;
304 while(p < q) {
305 if (!*p || *p == '\n')
306 break;
307 ++p;
308 }
309 *p = 0;
310}
311
312static void __init iSeries_init_early(void)
313{
314 extern unsigned long memory_limit;
315
316 DBG(" -> iSeries_init_early()\n");
317
aed31351
SR		 318 ppc64_firmware_features = FW_FEATURE_ISERIES;
319
1da177e4
LT		 320 ppcdbg_initialize();
321
322#if defined(CONFIG_BLK_DEV_INITRD)
323 /*
324 * If the init RAM disk has been configured and there is
325 * a non-zero starting address for it, set it up
326 */
327 if (naca.xRamDisk) {
328 initrd_start = (unsigned long)__va(naca.xRamDisk);
329 initrd_end = initrd_start + naca.xRamDiskSize * PAGE_SIZE;
330 initrd_below_start_ok = 1; // ramdisk in kernel space
331 ROOT_DEV = Root_RAM0;
332 if (((rd_size * 1024) / PAGE_SIZE) < naca.xRamDiskSize)
333 rd_size = (naca.xRamDiskSize * PAGE_SIZE) / 1024;
334 } else
335#endif /* CONFIG_BLK_DEV_INITRD */
336 {
337 /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */
338 }
339
340 iSeries_recal_tb = get_tb();
341 iSeries_recal_titan = HvCallXm_loadTod();
342
343 /*
344 * Cache sizes must be initialized before hpte_init_iSeries is called
345 * as the later need them for flush_icache_range()
346 */
347 setup_iSeries_cache_sizes();
348
349 /*
350 * Initialize the hash table management pointers
351 */
352 hpte_init_iSeries();
353
354 /*
355 * Initialize the DMA/TCE management
356 */
357 iommu_init_early_iSeries();
358
359 /*
360 * Initialize the table which translate Linux physical addresses to
361 * AS/400 absolute addresses
362 */
363 build_iSeries_Memory_Map();
364
365 iSeries_get_cmdline();
366
367 /* Save unparsed command line copy for /proc/cmdline */
368 strlcpy(saved_command_line, cmd_line, COMMAND_LINE_SIZE);
369
370 /* Parse early parameters, in particular mem=x */
371 parse_early_param();
372
373 if (memory_limit) {
374 if (memory_limit < systemcfg->physicalMemorySize)
375 systemcfg->physicalMemorySize = memory_limit;
376 else {
377 printk("Ignoring mem=%lu >= ram_top.\n", memory_limit);
378 memory_limit = 0;
379 }
380 }
381
382 /* Bolt kernel mappings for all of memory (or just a bit if we've got a limit) */
383 iSeries_bolt_kernel(0, systemcfg->physicalMemorySize);
384
385 lmb_init();
386 lmb_add(0, systemcfg->physicalMemorySize);
387 lmb_analyze();
388 lmb_reserve(0, __pa(klimit));
389
390 /* Initialize machine-dependency vectors */
391#ifdef CONFIG_SMP
392 smp_init_iSeries();
393#endif
394 if (itLpNaca.xPirEnvironMode == 0)
395 piranha_simulator = 1;
396
397 /* Associate Lp Event Queue 0 with processor 0 */
398 HvCallEvent_setLpEventQueueInterruptProc(0, 0);
399
400 mf_init();
401 mf_initialized = 1;
402 mb();
403
404 /* If we were passed an initrd, set the ROOT_DEV properly if the values
405 * look sensible. If not, clear initrd reference.
406 */
407#ifdef CONFIG_BLK_DEV_INITRD
408 if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE &&
409 initrd_end > initrd_start)
410 ROOT_DEV = Root_RAM0;
411 else
412 initrd_start = initrd_end = 0;
413#endif /* CONFIG_BLK_DEV_INITRD */
414
415 DBG(" <- iSeries_init_early()\n");
416}
417
418/*
419 * The iSeries may have very large memories ( > 128 GB ) and a partition
420 * may get memory in "chunks" that may be anywhere in the 2**52 real
421 * address space. The chunks are 256K in size. To map this to the
422 * memory model Linux expects, the AS/400 specific code builds a
423 * translation table to translate what Linux thinks are "physical"
424 * addresses to the actual real addresses. This allows us to make
425 * it appear to Linux that we have contiguous memory starting at
426 * physical address zero while in fact this could be far from the truth.
427 * To avoid confusion, I'll let the words physical and/or real address
428 * apply to the Linux addresses while I'll use "absolute address" to
429 * refer to the actual hardware real address.
430 *
431 * build_iSeries_Memory_Map gets information from the Hypervisor and
432 * looks at the Main Store VPD to determine the absolute addresses
433 * of the memory that has been assigned to our partition and builds
434 * a table used to translate Linux's physical addresses to these
435 * absolute addresses. Absolute addresses are needed when
436 * communicating with the hypervisor (e.g. to build HPT entries)
437 */
438
439static void __init build_iSeries_Memory_Map(void)
440{
441 u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize;
442 u32 nextPhysChunk;
443 u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages;
444 u32 num_ptegs;
445 u32 totalChunks,moreChunks;
446 u32 currChunk, thisChunk, absChunk;
447 u32 currDword;
448 u32 chunkBit;
449 u64 map;
450 struct MemoryBlock mb[32];
451 unsigned long numMemoryBlocks, curBlock;
452
453 /* Chunk size on iSeries is 256K bytes */
454 totalChunks = (u32)HvLpConfig_getMsChunks();
455 klimit = msChunks_alloc(klimit, totalChunks, 1UL << 18);
456
457 /*
458 * Get absolute address of our load area
459 * and map it to physical address 0
460 * This guarantees that the loadarea ends up at physical 0
461 * otherwise, it might not be returned by PLIC as the first
462 * chunks
463 */
464
465 loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr);
466 loadAreaSize = itLpNaca.xLoadAreaChunks;
467
468 /*
469 * Only add the pages already mapped here.
470 * Otherwise we might add the hpt pages
471 * The rest of the pages of the load area
472 * aren't in the HPT yet and can still
473 * be assigned an arbitrary physical address
474 */
475 if ((loadAreaSize * 64) > HvPagesToMap)
476 loadAreaSize = HvPagesToMap / 64;
477
478 loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1;
479
480 /*
481 * TODO Do we need to do something if the HPT is in the 64MB load area?
482 * This would be required if the itLpNaca.xLoadAreaChunks includes
483 * the HPT size
484 */
485
486 printk("Mapping load area - physical addr = 0000000000000000\n"
487 " absolute addr = %016lx\n",
488 chunk_to_addr(loadAreaFirstChunk));
489 printk("Load area size %dK\n", loadAreaSize * 256);
490
491 for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk)
492 msChunks.abs[nextPhysChunk] =
493 loadAreaFirstChunk + nextPhysChunk;
494
495 /*
496 * Get absolute address of our HPT and remember it so
497 * we won't map it to any physical address
498 */
499 hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress());
500 hptSizePages = (u32)HvCallHpt_getHptPages();
501 hptSizeChunks = hptSizePages >> (msChunks.chunk_shift - PAGE_SHIFT);
502 hptLastChunk = hptFirstChunk + hptSizeChunks - 1;
503
504 printk("HPT absolute addr = %016lx, size = %dK\n",
505 chunk_to_addr(hptFirstChunk), hptSizeChunks * 256);
506
507 /* Fill in the hashed page table hash mask */
508 num_ptegs = hptSizePages *
96e28449 509 (PAGE_SIZE / (sizeof(hpte_t) * HPTES_PER_GROUP));
1da177e4
LT		 510 htab_hash_mask = num_ptegs - 1;
511
512 /*
513 * The actual hashed page table is in the hypervisor,
514 * we have no direct access
515 */
516 htab_address = NULL;
517
518 /*
519 * Determine if absolute memory has any
520 * holes so that we can interpret the
521 * access map we get back from the hypervisor
522 * correctly.
523 */
524 numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32);
525
526 /*
527 * Process the main store access map from the hypervisor
528 * to build up our physical -> absolute translation table
529 */
530 curBlock = 0;
531 currChunk = 0;
532 currDword = 0;
533 moreChunks = totalChunks;
534
535 while (moreChunks) {
536 map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex,
537 currDword);
538 thisChunk = currChunk;
539 while (map) {
540 chunkBit = map >> 63;
541 map <<= 1;
542 if (chunkBit) {
543 --moreChunks;
544 while (thisChunk >= mb[curBlock].logicalEnd) {
545 ++curBlock;
546 if (curBlock >= numMemoryBlocks)
547 panic("out of memory blocks");
548 }
549 if (thisChunk < mb[curBlock].logicalStart)
550 panic("memory block error");
551
552 absChunk = mb[curBlock].absStart +
553 (thisChunk - mb[curBlock].logicalStart);
554 if (((absChunk < hptFirstChunk) ||
555 (absChunk > hptLastChunk)) &&
556 ((absChunk < loadAreaFirstChunk) ||
557 (absChunk > loadAreaLastChunk))) {
558 msChunks.abs[nextPhysChunk] = absChunk;
559 ++nextPhysChunk;
560 }
561 }
562 ++thisChunk;
563 }
564 ++currDword;
565 currChunk += 64;
566 }
567
568 /*
569 * main store size (in chunks) is
570 * totalChunks - hptSizeChunks
571 * which should be equal to
572 * nextPhysChunk
573 */
574 systemcfg->physicalMemorySize = chunk_to_addr(nextPhysChunk);
575}
576
577/*
578 * Set up the variables that describe the cache line sizes
579 * for this machine.
580 */
581static void __init setup_iSeries_cache_sizes(void)
582{
583 unsigned int i, n;
584 unsigned int procIx = get_paca()->lppaca.dyn_hv_phys_proc_index;
585
586 systemcfg->icache_size =
587 ppc64_caches.isize = xIoHriProcessorVpd[procIx].xInstCacheSize * 1024;
588 systemcfg->icache_line_size =
589 ppc64_caches.iline_size =
590 xIoHriProcessorVpd[procIx].xInstCacheOperandSize;
591 systemcfg->dcache_size =
592 ppc64_caches.dsize =
593 xIoHriProcessorVpd[procIx].xDataL1CacheSizeKB * 1024;
594 systemcfg->dcache_line_size =
595 ppc64_caches.dline_size =
596 xIoHriProcessorVpd[procIx].xDataCacheOperandSize;
597 ppc64_caches.ilines_per_page = PAGE_SIZE / ppc64_caches.iline_size;
598 ppc64_caches.dlines_per_page = PAGE_SIZE / ppc64_caches.dline_size;
599
600 i = ppc64_caches.iline_size;
601 n = 0;
602 while ((i = (i / 2)))
603 ++n;
604 ppc64_caches.log_iline_size = n;
605
606 i = ppc64_caches.dline_size;
607 n = 0;
608 while ((i = (i / 2)))
609 ++n;
610 ppc64_caches.log_dline_size = n;
611
612 printk("D-cache line size = %d\n",
613 (unsigned int)ppc64_caches.dline_size);
614 printk("I-cache line size = %d\n",
615 (unsigned int)ppc64_caches.iline_size);
616}
617
618/*
619 * Create a pte. Used during initialization only.
620 */
621static void iSeries_make_pte(unsigned long va, unsigned long pa,
622 int mode)
623{
96e28449 624 hpte_t local_hpte, rhpte;
1da177e4
LT		 625 unsigned long hash, vpn;
626 long slot;
627
628 vpn = va >> PAGE_SHIFT;
629 hash = hpt_hash(vpn, 0);
630
96e28449
DG		 631 local_hpte.r = pa | mode;
632 local_hpte.v = ((va >> 23) << HPTE_V_AVPN_SHIFT)
633 | HPTE_V_BOLTED | HPTE_V_VALID;
1da177e4
LT		 634
635 slot = HvCallHpt_findValid(&rhpte, vpn);
636 if (slot < 0) {
637 /* Must find space in primary group */
638 panic("hash_page: hpte already exists\n");
639 }
96e28449 640 HvCallHpt_addValidate(slot, 0, &local_hpte);
1da177e4
LT		 641}
642
643/*
644 * Bolt the kernel addr space into the HPT
645 */
646static void __init iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr)
647{
648 unsigned long pa;
649 unsigned long mode_rw = _PAGE_ACCESSED | _PAGE_COHERENT | PP_RWXX;
96e28449 650 hpte_t hpte;
1da177e4
LT		 651
652 for (pa = saddr; pa < eaddr ;pa += PAGE_SIZE) {
653 unsigned long ea = (unsigned long)__va(pa);
654 unsigned long vsid = get_kernel_vsid(ea);
655 unsigned long va = (vsid << 28) | (pa & 0xfffffff);
656 unsigned long vpn = va >> PAGE_SHIFT;
657 unsigned long slot = HvCallHpt_findValid(&hpte, vpn);
658
659 /* Make non-kernel text non-executable */
660 if (!in_kernel_text(ea))
661 mode_rw |= HW_NO_EXEC;
662
96e28449 663 if (hpte.v & HPTE_V_VALID) {
1da177e4
LT		 664 /* HPTE exists, so just bolt it */
665 HvCallHpt_setSwBits(slot, 0x10, 0);
666 /* And make sure the pp bits are correct */
667 HvCallHpt_setPp(slot, PP_RWXX);
668 } else
669 /* No HPTE exists, so create a new bolted one */
670 iSeries_make_pte(va, phys_to_abs(pa), mode_rw);
671 }
672}
673
1da177e4
LT		 674/*
675 * Document me.
676 */
677static void __init iSeries_setup_arch(void)
678{
1da177e4
LT		 679 unsigned procIx = get_paca()->lppaca.dyn_hv_phys_proc_index;
680
681 /* Add an eye catcher and the systemcfg layout version number */
682 strcpy(systemcfg->eye_catcher, "SYSTEMCFG:PPC64");
683 systemcfg->version.major = SYSTEMCFG_MAJOR;
684 systemcfg->version.minor = SYSTEMCFG_MINOR;
685
686 /* Setup the Lp Event Queue */
512d31d6 687 setup_hvlpevent_queue();
1da177e4
LT		 688
689 /* Compute processor frequency */
690 procFreqHz = ((1UL << 34) * 1000000) /
691 xIoHriProcessorVpd[procIx].xProcFreq;
692 procFreqMhz = procFreqHz / 1000000;
693 procFreqMhzHundreths = (procFreqHz / 10000) - (procFreqMhz * 100);
694 ppc_proc_freq = procFreqHz;
695
696 /* Compute time base frequency */
697 tbFreqHz = ((1UL << 32) * 1000000) /
698 xIoHriProcessorVpd[procIx].xTimeBaseFreq;
699 tbFreqMhz = tbFreqHz / 1000000;
700 tbFreqMhzHundreths = (tbFreqHz / 10000) - (tbFreqMhz * 100);
701 ppc_tb_freq = tbFreqHz;
702
703 printk("Max logical processors = %d\n",
704 itVpdAreas.xSlicMaxLogicalProcs);
705 printk("Max physical processors = %d\n",
706 itVpdAreas.xSlicMaxPhysicalProcs);
707 printk("Processor frequency = %lu.%02lu\n", procFreqMhz,
708 procFreqMhzHundreths);
709 printk("Time base frequency = %lu.%02lu\n", tbFreqMhz,
710 tbFreqMhzHundreths);
711 systemcfg->processor = xIoHriProcessorVpd[procIx].xPVR;
712 printk("Processor version = %x\n", systemcfg->processor);
713}
714
715static void iSeries_get_cpuinfo(struct seq_file *m)
716{
717 seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n");
718}
719
720/*
721 * Document me.
722 * and Implement me.
723 */
724static int iSeries_get_irq(struct pt_regs *regs)
725{
726 /* -2 means ignore this interrupt */
727 return -2;
728}
729
730/*
731 * Document me.
732 */
733static void iSeries_restart(char *cmd)
734{
735 mf_reboot();
736}
737
738/*
739 * Document me.
740 */
741static void iSeries_power_off(void)
742{
743 mf_power_off();
744}
745
746/*
747 * Document me.
748 */
749static void iSeries_halt(void)
750{
751 mf_power_off();
752}
753
1da177e4
LT		 754/*
755 * void __init iSeries_calibrate_decr()
756 *
757 * Description:
758 * This routine retrieves the internal processor frequency from the VPD,
759 * and sets up the kernel timer decrementer based on that value.
760 *
761 */
762static void __init iSeries_calibrate_decr(void)
763{
764 unsigned long cyclesPerUsec;
765 struct div_result divres;
766
767 /* Compute decrementer (and TB) frequency in cycles/sec */
768 cyclesPerUsec = ppc_tb_freq / 1000000;
769
770 /*
771 * Set the amount to refresh the decrementer by. This
772 * is the number of decrementer ticks it takes for
773 * 1/HZ seconds.
774 */
775 tb_ticks_per_jiffy = ppc_tb_freq / HZ;
776
777#if 0
778 /* TEST CODE FOR ADJTIME */
779 tb_ticks_per_jiffy += tb_ticks_per_jiffy / 5000;
780 /* END OF TEST CODE */
781#endif
782
783 /*
784 * tb_ticks_per_sec = freq; would give better accuracy
785 * but tb_ticks_per_sec = tb_ticks_per_jiffy*HZ; assures
786 * that jiffies (and xtime) will match the time returned
787 * by do_gettimeofday.
788 */
789 tb_ticks_per_sec = tb_ticks_per_jiffy * HZ;
790 tb_ticks_per_usec = cyclesPerUsec;
791 tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000);
792 div128_by_32(1024 * 1024, 0, tb_ticks_per_sec, &divres);
793 tb_to_xs = divres.result_low;
794 setup_default_decr();
795}
796
797static void __init iSeries_progress(char * st, unsigned short code)
798{
799 printk("Progress: [%04x] - %s\n", (unsigned)code, st);
800 if (!piranha_simulator && mf_initialized) {
801 if (code != 0xffff)
802 mf_display_progress(code);
803 else
804 mf_clear_src();
805 }
806}
807
808static void __init iSeries_fixup_klimit(void)
809{
810 /*
811 * Change klimit to take into account any ram disk
812 * that may be included
813 */
814 if (naca.xRamDisk)
815 klimit = KERNELBASE + (u64)naca.xRamDisk +
816 (naca.xRamDiskSize * PAGE_SIZE);
817 else {
818 /*
819 * No ram disk was included - check and see if there
820 * was an embedded system map. Change klimit to take
821 * into account any embedded system map
822 */
823 if (embedded_sysmap_end)
824 klimit = KERNELBASE + ((embedded_sysmap_end + 4095) &
825 0xfffffffffffff000);
826 }
827}
828
829static int __init iSeries_src_init(void)
830{
831 /* clear the progress line */
832 ppc_md.progress(" ", 0xffff);
833 return 0;
834}
835
836late_initcall(iSeries_src_init);
837
d200903e
ME		 838static inline void process_iSeries_events(void)
839{
840 asm volatile ("li 0,0x5555; sc" : : : "r0", "r3");
841}
842
843static void yield_shared_processor(void)
844{
845 unsigned long tb;
d200903e
ME		 846
847 HvCall_setEnabledInterrupts(HvCall_MaskIPI |
848 HvCall_MaskLpEvent |
849 HvCall_MaskLpProd |
850 HvCall_MaskTimeout);
851
852 tb = get_tb();
853 /* Compute future tb value when yield should expire */
854 HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy);
855
d200903e
ME		 856 /*
857 * The decrementer stops during the yield. Force a fake decrementer
858 * here and let the timer_interrupt code sort out the actual time.
859 */
860 get_paca()->lppaca.int_dword.fields.decr_int = 1;
861 process_iSeries_events();
862}
863
3c57bb9f 864static int iseries_shared_idle(void)
d200903e 865{
3c57bb9f
AB		 866 while (1) {
867 while (!need_resched() && !hvlpevent_is_pending()) {
868 local_irq_disable();
869 ppc64_runlatch_off();
870
871 /* Recheck with irqs off */
872 if (!need_resched() && !hvlpevent_is_pending())
873 yield_shared_processor();
d200903e 874
3c57bb9f
AB		 875 HMT_medium();
876 local_irq_enable();
877 }
878
879 ppc64_runlatch_on();
d200903e 880
3c57bb9f
AB		 881 if (hvlpevent_is_pending())
882 process_iSeries_events();
883
884 schedule();
885 }
886
887 return 0;
888}
889
890static int iseries_dedicated_idle(void)
891{
3c57bb9f 892 long oldval;
d200903e
ME		 893
894 while (1) {
3c57bb9f 895 oldval = test_and_clear_thread_flag(TIF_NEED_RESCHED);
d200903e 896
3c57bb9f
AB		 897 if (!oldval) {
898 set_thread_flag(TIF_POLLING_NRFLAG);
d200903e 899
3c57bb9f
AB		 900 while (!need_resched()) {
901 ppc64_runlatch_off();
902 HMT_low();
903
904 if (hvlpevent_is_pending()) {
d200903e 905 HMT_medium();
3c57bb9f
AB		 906 ppc64_runlatch_on();
907 process_iSeries_events();
d200903e 908 }
d200903e 909 }
3c57bb9f
AB		 910
911 HMT_medium();
912 clear_thread_flag(TIF_POLLING_NRFLAG);
913 } else {
914 set_need_resched();
d200903e
ME		 915 }
916
917 ppc64_runlatch_on();
918 schedule();
d200903e
ME		 919 }
920
921 return 0;
922}
923
145d01e4
SR		 924#ifndef CONFIG_PCI
925void __init iSeries_init_IRQ(void) { }
926#endif
927
1da177e4
LT		 928void __init iSeries_early_setup(void)
929{
930 iSeries_fixup_klimit();
931
932 ppc_md.setup_arch = iSeries_setup_arch;
933 ppc_md.get_cpuinfo = iSeries_get_cpuinfo;
934 ppc_md.init_IRQ = iSeries_init_IRQ;
935 ppc_md.get_irq = iSeries_get_irq;
936 ppc_md.init_early = iSeries_init_early,
937
938 ppc_md.pcibios_fixup = iSeries_pci_final_fixup;
939
940 ppc_md.restart = iSeries_restart;
941 ppc_md.power_off = iSeries_power_off;
942 ppc_md.halt = iSeries_halt;
943
944 ppc_md.get_boot_time = iSeries_get_boot_time;
945 ppc_md.set_rtc_time = iSeries_set_rtc_time;
946 ppc_md.get_rtc_time = iSeries_get_rtc_time;
947 ppc_md.calibrate_decr = iSeries_calibrate_decr;
948 ppc_md.progress = iSeries_progress;
3c57bb9f 949
b6bff397 950 if (get_paca()->lppaca.shared_proc) {
3c57bb9f 951 ppc_md.idle_loop = iseries_shared_idle;
b6bff397
ME		 952 printk(KERN_INFO "Using shared processor idle loop\n");
953 } else {
3c57bb9f 954 ppc_md.idle_loop = iseries_dedicated_idle;
b6bff397
ME		 955 printk(KERN_INFO "Using dedicated idle loop\n");
956 }
1da177e4
LT		 957}
958
Linux kernel - Deliverables
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