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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
3 | * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu> | |
4 | * | |
5 | * Module name: iSeries_setup.c | |
6 | * | |
7 | * Description: | |
8 | * Architecture- / platform-specific boot-time initialization code for | |
9 | * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and | |
10 | * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek | |
11 | * <dan@net4x.com>. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
19 | #undef DEBUG | |
20 | ||
21 | #include <linux/config.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/threads.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/param.h> | |
26 | #include <linux/string.h> | |
1da177e4 LT |
27 | #include <linux/initrd.h> |
28 | #include <linux/seq_file.h> | |
29 | #include <linux/kdev_t.h> | |
30 | #include <linux/major.h> | |
31 | #include <linux/root_dev.h> | |
32 | ||
33 | #include <asm/processor.h> | |
34 | #include <asm/machdep.h> | |
35 | #include <asm/page.h> | |
36 | #include <asm/mmu.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/mmu_context.h> | |
39 | #include <asm/cputable.h> | |
40 | #include <asm/sections.h> | |
41 | #include <asm/iommu.h> | |
42 | ||
43 | #include <asm/time.h> | |
44 | #include "iSeries_setup.h" | |
45 | #include <asm/naca.h> | |
46 | #include <asm/paca.h> | |
47 | #include <asm/cache.h> | |
48 | #include <asm/sections.h> | |
0bc0ffd5 | 49 | #include <asm/abs_addr.h> |
1da177e4 LT |
50 | #include <asm/iSeries/HvCallHpt.h> |
51 | #include <asm/iSeries/HvLpConfig.h> | |
52 | #include <asm/iSeries/HvCallEvent.h> | |
53 | #include <asm/iSeries/HvCallSm.h> | |
54 | #include <asm/iSeries/HvCallXm.h> | |
55 | #include <asm/iSeries/ItLpQueue.h> | |
56 | #include <asm/iSeries/IoHriMainStore.h> | |
1da177e4 LT |
57 | #include <asm/iSeries/mf.h> |
58 | #include <asm/iSeries/HvLpEvent.h> | |
59 | #include <asm/iSeries/iSeries_irq.h> | |
0bc0ffd5 SR |
60 | #include <asm/iSeries/IoHriProcessorVpd.h> |
61 | #include <asm/iSeries/ItVpdAreas.h> | |
62 | #include <asm/iSeries/LparMap.h> | |
1da177e4 LT |
63 | |
64 | extern void hvlog(char *fmt, ...); | |
65 | ||
66 | #ifdef DEBUG | |
67 | #define DBG(fmt...) hvlog(fmt) | |
68 | #else | |
69 | #define DBG(fmt...) | |
70 | #endif | |
71 | ||
72 | /* Function Prototypes */ | |
73 | extern void ppcdbg_initialize(void); | |
74 | ||
75 | static void build_iSeries_Memory_Map(void); | |
76 | static void setup_iSeries_cache_sizes(void); | |
77 | static void iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr); | |
145d01e4 | 78 | #ifdef CONFIG_PCI |
1da177e4 | 79 | extern void iSeries_pci_final_fixup(void); |
145d01e4 SR |
80 | #else |
81 | static void iSeries_pci_final_fixup(void) { } | |
82 | #endif | |
1da177e4 LT |
83 | |
84 | /* Global Variables */ | |
85 | static unsigned long procFreqHz; | |
86 | static unsigned long procFreqMhz; | |
87 | static unsigned long procFreqMhzHundreths; | |
88 | ||
89 | static unsigned long tbFreqHz; | |
90 | static unsigned long tbFreqMhz; | |
91 | static unsigned long tbFreqMhzHundreths; | |
92 | ||
93 | int piranha_simulator; | |
94 | ||
95 | extern int rd_size; /* Defined in drivers/block/rd.c */ | |
96 | extern unsigned long klimit; | |
97 | extern unsigned long embedded_sysmap_start; | |
98 | extern unsigned long embedded_sysmap_end; | |
99 | ||
100 | extern unsigned long iSeries_recal_tb; | |
101 | extern unsigned long iSeries_recal_titan; | |
102 | ||
103 | static int mf_initialized; | |
104 | ||
105 | struct MemoryBlock { | |
106 | unsigned long absStart; | |
107 | unsigned long absEnd; | |
108 | unsigned long logicalStart; | |
109 | unsigned long logicalEnd; | |
110 | }; | |
111 | ||
112 | /* | |
113 | * Process the main store vpd to determine where the holes in memory are | |
114 | * and return the number of physical blocks and fill in the array of | |
115 | * block data. | |
116 | */ | |
117 | static unsigned long iSeries_process_Condor_mainstore_vpd( | |
118 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
119 | { | |
120 | unsigned long holeFirstChunk, holeSizeChunks; | |
121 | unsigned long numMemoryBlocks = 1; | |
122 | struct IoHriMainStoreSegment4 *msVpd = | |
123 | (struct IoHriMainStoreSegment4 *)xMsVpd; | |
124 | unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr; | |
125 | unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr; | |
126 | unsigned long holeSize = holeEnd - holeStart; | |
127 | ||
128 | printk("Mainstore_VPD: Condor\n"); | |
129 | /* | |
130 | * Determine if absolute memory has any | |
131 | * holes so that we can interpret the | |
132 | * access map we get back from the hypervisor | |
133 | * correctly. | |
134 | */ | |
135 | mb_array[0].logicalStart = 0; | |
136 | mb_array[0].logicalEnd = 0x100000000; | |
137 | mb_array[0].absStart = 0; | |
138 | mb_array[0].absEnd = 0x100000000; | |
139 | ||
140 | if (holeSize) { | |
141 | numMemoryBlocks = 2; | |
142 | holeStart = holeStart & 0x000fffffffffffff; | |
143 | holeStart = addr_to_chunk(holeStart); | |
144 | holeFirstChunk = holeStart; | |
145 | holeSize = addr_to_chunk(holeSize); | |
146 | holeSizeChunks = holeSize; | |
147 | printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n", | |
148 | holeFirstChunk, holeSizeChunks ); | |
149 | mb_array[0].logicalEnd = holeFirstChunk; | |
150 | mb_array[0].absEnd = holeFirstChunk; | |
151 | mb_array[1].logicalStart = holeFirstChunk; | |
152 | mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks; | |
153 | mb_array[1].absStart = holeFirstChunk + holeSizeChunks; | |
154 | mb_array[1].absEnd = 0x100000000; | |
155 | } | |
156 | return numMemoryBlocks; | |
157 | } | |
158 | ||
159 | #define MaxSegmentAreas 32 | |
160 | #define MaxSegmentAdrRangeBlocks 128 | |
161 | #define MaxAreaRangeBlocks 4 | |
162 | ||
163 | static unsigned long iSeries_process_Regatta_mainstore_vpd( | |
164 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
165 | { | |
166 | struct IoHriMainStoreSegment5 *msVpdP = | |
167 | (struct IoHriMainStoreSegment5 *)xMsVpd; | |
168 | unsigned long numSegmentBlocks = 0; | |
169 | u32 existsBits = msVpdP->msAreaExists; | |
170 | unsigned long area_num; | |
171 | ||
172 | printk("Mainstore_VPD: Regatta\n"); | |
173 | ||
174 | for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) { | |
175 | unsigned long numAreaBlocks; | |
176 | struct IoHriMainStoreArea4 *currentArea; | |
177 | ||
178 | if (existsBits & 0x80000000) { | |
179 | unsigned long block_num; | |
180 | ||
181 | currentArea = &msVpdP->msAreaArray[area_num]; | |
182 | numAreaBlocks = currentArea->numAdrRangeBlocks; | |
183 | printk("ms_vpd: processing area %2ld blocks=%ld", | |
184 | area_num, numAreaBlocks); | |
185 | for (block_num = 0; block_num < numAreaBlocks; | |
186 | ++block_num ) { | |
187 | /* Process an address range block */ | |
188 | struct MemoryBlock tempBlock; | |
189 | unsigned long i; | |
190 | ||
191 | tempBlock.absStart = | |
192 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart; | |
193 | tempBlock.absEnd = | |
194 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd; | |
195 | tempBlock.logicalStart = 0; | |
196 | tempBlock.logicalEnd = 0; | |
197 | printk("\n block %ld absStart=%016lx absEnd=%016lx", | |
198 | block_num, tempBlock.absStart, | |
199 | tempBlock.absEnd); | |
200 | ||
201 | for (i = 0; i < numSegmentBlocks; ++i) { | |
202 | if (mb_array[i].absStart == | |
203 | tempBlock.absStart) | |
204 | break; | |
205 | } | |
206 | if (i == numSegmentBlocks) { | |
207 | if (numSegmentBlocks == max_entries) | |
208 | panic("iSeries_process_mainstore_vpd: too many memory blocks"); | |
209 | mb_array[numSegmentBlocks] = tempBlock; | |
210 | ++numSegmentBlocks; | |
211 | } else | |
212 | printk(" (duplicate)"); | |
213 | } | |
214 | printk("\n"); | |
215 | } | |
216 | existsBits <<= 1; | |
217 | } | |
218 | /* Now sort the blocks found into ascending sequence */ | |
219 | if (numSegmentBlocks > 1) { | |
220 | unsigned long m, n; | |
221 | ||
222 | for (m = 0; m < numSegmentBlocks - 1; ++m) { | |
223 | for (n = numSegmentBlocks - 1; m < n; --n) { | |
224 | if (mb_array[n].absStart < | |
225 | mb_array[n-1].absStart) { | |
226 | struct MemoryBlock tempBlock; | |
227 | ||
228 | tempBlock = mb_array[n]; | |
229 | mb_array[n] = mb_array[n-1]; | |
230 | mb_array[n-1] = tempBlock; | |
231 | } | |
232 | } | |
233 | } | |
234 | } | |
235 | /* | |
236 | * Assign "logical" addresses to each block. These | |
237 | * addresses correspond to the hypervisor "bitmap" space. | |
238 | * Convert all addresses into units of 256K chunks. | |
239 | */ | |
240 | { | |
241 | unsigned long i, nextBitmapAddress; | |
242 | ||
243 | printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks); | |
244 | nextBitmapAddress = 0; | |
245 | for (i = 0; i < numSegmentBlocks; ++i) { | |
246 | unsigned long length = mb_array[i].absEnd - | |
247 | mb_array[i].absStart; | |
248 | ||
249 | mb_array[i].logicalStart = nextBitmapAddress; | |
250 | mb_array[i].logicalEnd = nextBitmapAddress + length; | |
251 | nextBitmapAddress += length; | |
252 | printk(" Bitmap range: %016lx - %016lx\n" | |
253 | " Absolute range: %016lx - %016lx\n", | |
254 | mb_array[i].logicalStart, | |
255 | mb_array[i].logicalEnd, | |
256 | mb_array[i].absStart, mb_array[i].absEnd); | |
257 | mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart & | |
258 | 0x000fffffffffffff); | |
259 | mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd & | |
260 | 0x000fffffffffffff); | |
261 | mb_array[i].logicalStart = | |
262 | addr_to_chunk(mb_array[i].logicalStart); | |
263 | mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd); | |
264 | } | |
265 | } | |
266 | ||
267 | return numSegmentBlocks; | |
268 | } | |
269 | ||
270 | static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array, | |
271 | unsigned long max_entries) | |
272 | { | |
273 | unsigned long i; | |
274 | unsigned long mem_blocks = 0; | |
275 | ||
276 | if (cpu_has_feature(CPU_FTR_SLB)) | |
277 | mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array, | |
278 | max_entries); | |
279 | else | |
280 | mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array, | |
281 | max_entries); | |
282 | ||
283 | printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks); | |
284 | for (i = 0; i < mem_blocks; ++i) { | |
285 | printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n" | |
286 | " abs chunks %016lx - %016lx\n", | |
287 | i, mb_array[i].logicalStart, mb_array[i].logicalEnd, | |
288 | mb_array[i].absStart, mb_array[i].absEnd); | |
289 | } | |
290 | return mem_blocks; | |
291 | } | |
292 | ||
293 | static void __init iSeries_get_cmdline(void) | |
294 | { | |
295 | char *p, *q; | |
296 | ||
297 | /* copy the command line parameter from the primary VSP */ | |
298 | HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256, | |
299 | HvLpDma_Direction_RemoteToLocal); | |
300 | ||
301 | p = cmd_line; | |
302 | q = cmd_line + 255; | |
303 | while(p < q) { | |
304 | if (!*p || *p == '\n') | |
305 | break; | |
306 | ++p; | |
307 | } | |
308 | *p = 0; | |
309 | } | |
310 | ||
311 | static void __init iSeries_init_early(void) | |
312 | { | |
313 | extern unsigned long memory_limit; | |
314 | ||
315 | DBG(" -> iSeries_init_early()\n"); | |
316 | ||
317 | ppcdbg_initialize(); | |
318 | ||
319 | #if defined(CONFIG_BLK_DEV_INITRD) | |
320 | /* | |
321 | * If the init RAM disk has been configured and there is | |
322 | * a non-zero starting address for it, set it up | |
323 | */ | |
324 | if (naca.xRamDisk) { | |
325 | initrd_start = (unsigned long)__va(naca.xRamDisk); | |
326 | initrd_end = initrd_start + naca.xRamDiskSize * PAGE_SIZE; | |
327 | initrd_below_start_ok = 1; // ramdisk in kernel space | |
328 | ROOT_DEV = Root_RAM0; | |
329 | if (((rd_size * 1024) / PAGE_SIZE) < naca.xRamDiskSize) | |
330 | rd_size = (naca.xRamDiskSize * PAGE_SIZE) / 1024; | |
331 | } else | |
332 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
333 | { | |
334 | /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */ | |
335 | } | |
336 | ||
337 | iSeries_recal_tb = get_tb(); | |
338 | iSeries_recal_titan = HvCallXm_loadTod(); | |
339 | ||
340 | /* | |
341 | * Cache sizes must be initialized before hpte_init_iSeries is called | |
342 | * as the later need them for flush_icache_range() | |
343 | */ | |
344 | setup_iSeries_cache_sizes(); | |
345 | ||
346 | /* | |
347 | * Initialize the hash table management pointers | |
348 | */ | |
349 | hpte_init_iSeries(); | |
350 | ||
351 | /* | |
352 | * Initialize the DMA/TCE management | |
353 | */ | |
354 | iommu_init_early_iSeries(); | |
355 | ||
356 | /* | |
357 | * Initialize the table which translate Linux physical addresses to | |
358 | * AS/400 absolute addresses | |
359 | */ | |
360 | build_iSeries_Memory_Map(); | |
361 | ||
362 | iSeries_get_cmdline(); | |
363 | ||
364 | /* Save unparsed command line copy for /proc/cmdline */ | |
365 | strlcpy(saved_command_line, cmd_line, COMMAND_LINE_SIZE); | |
366 | ||
367 | /* Parse early parameters, in particular mem=x */ | |
368 | parse_early_param(); | |
369 | ||
370 | if (memory_limit) { | |
371 | if (memory_limit < systemcfg->physicalMemorySize) | |
372 | systemcfg->physicalMemorySize = memory_limit; | |
373 | else { | |
374 | printk("Ignoring mem=%lu >= ram_top.\n", memory_limit); | |
375 | memory_limit = 0; | |
376 | } | |
377 | } | |
378 | ||
379 | /* Bolt kernel mappings for all of memory (or just a bit if we've got a limit) */ | |
380 | iSeries_bolt_kernel(0, systemcfg->physicalMemorySize); | |
381 | ||
382 | lmb_init(); | |
383 | lmb_add(0, systemcfg->physicalMemorySize); | |
384 | lmb_analyze(); | |
385 | lmb_reserve(0, __pa(klimit)); | |
386 | ||
387 | /* Initialize machine-dependency vectors */ | |
388 | #ifdef CONFIG_SMP | |
389 | smp_init_iSeries(); | |
390 | #endif | |
391 | if (itLpNaca.xPirEnvironMode == 0) | |
392 | piranha_simulator = 1; | |
393 | ||
394 | /* Associate Lp Event Queue 0 with processor 0 */ | |
395 | HvCallEvent_setLpEventQueueInterruptProc(0, 0); | |
396 | ||
397 | mf_init(); | |
398 | mf_initialized = 1; | |
399 | mb(); | |
400 | ||
401 | /* If we were passed an initrd, set the ROOT_DEV properly if the values | |
402 | * look sensible. If not, clear initrd reference. | |
403 | */ | |
404 | #ifdef CONFIG_BLK_DEV_INITRD | |
405 | if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE && | |
406 | initrd_end > initrd_start) | |
407 | ROOT_DEV = Root_RAM0; | |
408 | else | |
409 | initrd_start = initrd_end = 0; | |
410 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
411 | ||
412 | DBG(" <- iSeries_init_early()\n"); | |
413 | } | |
414 | ||
415 | /* | |
416 | * The iSeries may have very large memories ( > 128 GB ) and a partition | |
417 | * may get memory in "chunks" that may be anywhere in the 2**52 real | |
418 | * address space. The chunks are 256K in size. To map this to the | |
419 | * memory model Linux expects, the AS/400 specific code builds a | |
420 | * translation table to translate what Linux thinks are "physical" | |
421 | * addresses to the actual real addresses. This allows us to make | |
422 | * it appear to Linux that we have contiguous memory starting at | |
423 | * physical address zero while in fact this could be far from the truth. | |
424 | * To avoid confusion, I'll let the words physical and/or real address | |
425 | * apply to the Linux addresses while I'll use "absolute address" to | |
426 | * refer to the actual hardware real address. | |
427 | * | |
428 | * build_iSeries_Memory_Map gets information from the Hypervisor and | |
429 | * looks at the Main Store VPD to determine the absolute addresses | |
430 | * of the memory that has been assigned to our partition and builds | |
431 | * a table used to translate Linux's physical addresses to these | |
432 | * absolute addresses. Absolute addresses are needed when | |
433 | * communicating with the hypervisor (e.g. to build HPT entries) | |
434 | */ | |
435 | ||
436 | static void __init build_iSeries_Memory_Map(void) | |
437 | { | |
438 | u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize; | |
439 | u32 nextPhysChunk; | |
440 | u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages; | |
441 | u32 num_ptegs; | |
442 | u32 totalChunks,moreChunks; | |
443 | u32 currChunk, thisChunk, absChunk; | |
444 | u32 currDword; | |
445 | u32 chunkBit; | |
446 | u64 map; | |
447 | struct MemoryBlock mb[32]; | |
448 | unsigned long numMemoryBlocks, curBlock; | |
449 | ||
450 | /* Chunk size on iSeries is 256K bytes */ | |
451 | totalChunks = (u32)HvLpConfig_getMsChunks(); | |
452 | klimit = msChunks_alloc(klimit, totalChunks, 1UL << 18); | |
453 | ||
454 | /* | |
455 | * Get absolute address of our load area | |
456 | * and map it to physical address 0 | |
457 | * This guarantees that the loadarea ends up at physical 0 | |
458 | * otherwise, it might not be returned by PLIC as the first | |
459 | * chunks | |
460 | */ | |
461 | ||
462 | loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr); | |
463 | loadAreaSize = itLpNaca.xLoadAreaChunks; | |
464 | ||
465 | /* | |
466 | * Only add the pages already mapped here. | |
467 | * Otherwise we might add the hpt pages | |
468 | * The rest of the pages of the load area | |
469 | * aren't in the HPT yet and can still | |
470 | * be assigned an arbitrary physical address | |
471 | */ | |
472 | if ((loadAreaSize * 64) > HvPagesToMap) | |
473 | loadAreaSize = HvPagesToMap / 64; | |
474 | ||
475 | loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1; | |
476 | ||
477 | /* | |
478 | * TODO Do we need to do something if the HPT is in the 64MB load area? | |
479 | * This would be required if the itLpNaca.xLoadAreaChunks includes | |
480 | * the HPT size | |
481 | */ | |
482 | ||
483 | printk("Mapping load area - physical addr = 0000000000000000\n" | |
484 | " absolute addr = %016lx\n", | |
485 | chunk_to_addr(loadAreaFirstChunk)); | |
486 | printk("Load area size %dK\n", loadAreaSize * 256); | |
487 | ||
488 | for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk) | |
489 | msChunks.abs[nextPhysChunk] = | |
490 | loadAreaFirstChunk + nextPhysChunk; | |
491 | ||
492 | /* | |
493 | * Get absolute address of our HPT and remember it so | |
494 | * we won't map it to any physical address | |
495 | */ | |
496 | hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress()); | |
497 | hptSizePages = (u32)HvCallHpt_getHptPages(); | |
498 | hptSizeChunks = hptSizePages >> (msChunks.chunk_shift - PAGE_SHIFT); | |
499 | hptLastChunk = hptFirstChunk + hptSizeChunks - 1; | |
500 | ||
501 | printk("HPT absolute addr = %016lx, size = %dK\n", | |
502 | chunk_to_addr(hptFirstChunk), hptSizeChunks * 256); | |
503 | ||
504 | /* Fill in the hashed page table hash mask */ | |
505 | num_ptegs = hptSizePages * | |
96e28449 | 506 | (PAGE_SIZE / (sizeof(hpte_t) * HPTES_PER_GROUP)); |
1da177e4 LT |
507 | htab_hash_mask = num_ptegs - 1; |
508 | ||
509 | /* | |
510 | * The actual hashed page table is in the hypervisor, | |
511 | * we have no direct access | |
512 | */ | |
513 | htab_address = NULL; | |
514 | ||
515 | /* | |
516 | * Determine if absolute memory has any | |
517 | * holes so that we can interpret the | |
518 | * access map we get back from the hypervisor | |
519 | * correctly. | |
520 | */ | |
521 | numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32); | |
522 | ||
523 | /* | |
524 | * Process the main store access map from the hypervisor | |
525 | * to build up our physical -> absolute translation table | |
526 | */ | |
527 | curBlock = 0; | |
528 | currChunk = 0; | |
529 | currDword = 0; | |
530 | moreChunks = totalChunks; | |
531 | ||
532 | while (moreChunks) { | |
533 | map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex, | |
534 | currDword); | |
535 | thisChunk = currChunk; | |
536 | while (map) { | |
537 | chunkBit = map >> 63; | |
538 | map <<= 1; | |
539 | if (chunkBit) { | |
540 | --moreChunks; | |
541 | while (thisChunk >= mb[curBlock].logicalEnd) { | |
542 | ++curBlock; | |
543 | if (curBlock >= numMemoryBlocks) | |
544 | panic("out of memory blocks"); | |
545 | } | |
546 | if (thisChunk < mb[curBlock].logicalStart) | |
547 | panic("memory block error"); | |
548 | ||
549 | absChunk = mb[curBlock].absStart + | |
550 | (thisChunk - mb[curBlock].logicalStart); | |
551 | if (((absChunk < hptFirstChunk) || | |
552 | (absChunk > hptLastChunk)) && | |
553 | ((absChunk < loadAreaFirstChunk) || | |
554 | (absChunk > loadAreaLastChunk))) { | |
555 | msChunks.abs[nextPhysChunk] = absChunk; | |
556 | ++nextPhysChunk; | |
557 | } | |
558 | } | |
559 | ++thisChunk; | |
560 | } | |
561 | ++currDword; | |
562 | currChunk += 64; | |
563 | } | |
564 | ||
565 | /* | |
566 | * main store size (in chunks) is | |
567 | * totalChunks - hptSizeChunks | |
568 | * which should be equal to | |
569 | * nextPhysChunk | |
570 | */ | |
571 | systemcfg->physicalMemorySize = chunk_to_addr(nextPhysChunk); | |
572 | } | |
573 | ||
574 | /* | |
575 | * Set up the variables that describe the cache line sizes | |
576 | * for this machine. | |
577 | */ | |
578 | static void __init setup_iSeries_cache_sizes(void) | |
579 | { | |
580 | unsigned int i, n; | |
581 | unsigned int procIx = get_paca()->lppaca.dyn_hv_phys_proc_index; | |
582 | ||
583 | systemcfg->icache_size = | |
584 | ppc64_caches.isize = xIoHriProcessorVpd[procIx].xInstCacheSize * 1024; | |
585 | systemcfg->icache_line_size = | |
586 | ppc64_caches.iline_size = | |
587 | xIoHriProcessorVpd[procIx].xInstCacheOperandSize; | |
588 | systemcfg->dcache_size = | |
589 | ppc64_caches.dsize = | |
590 | xIoHriProcessorVpd[procIx].xDataL1CacheSizeKB * 1024; | |
591 | systemcfg->dcache_line_size = | |
592 | ppc64_caches.dline_size = | |
593 | xIoHriProcessorVpd[procIx].xDataCacheOperandSize; | |
594 | ppc64_caches.ilines_per_page = PAGE_SIZE / ppc64_caches.iline_size; | |
595 | ppc64_caches.dlines_per_page = PAGE_SIZE / ppc64_caches.dline_size; | |
596 | ||
597 | i = ppc64_caches.iline_size; | |
598 | n = 0; | |
599 | while ((i = (i / 2))) | |
600 | ++n; | |
601 | ppc64_caches.log_iline_size = n; | |
602 | ||
603 | i = ppc64_caches.dline_size; | |
604 | n = 0; | |
605 | while ((i = (i / 2))) | |
606 | ++n; | |
607 | ppc64_caches.log_dline_size = n; | |
608 | ||
609 | printk("D-cache line size = %d\n", | |
610 | (unsigned int)ppc64_caches.dline_size); | |
611 | printk("I-cache line size = %d\n", | |
612 | (unsigned int)ppc64_caches.iline_size); | |
613 | } | |
614 | ||
615 | /* | |
616 | * Create a pte. Used during initialization only. | |
617 | */ | |
618 | static void iSeries_make_pte(unsigned long va, unsigned long pa, | |
619 | int mode) | |
620 | { | |
96e28449 | 621 | hpte_t local_hpte, rhpte; |
1da177e4 LT |
622 | unsigned long hash, vpn; |
623 | long slot; | |
624 | ||
625 | vpn = va >> PAGE_SHIFT; | |
626 | hash = hpt_hash(vpn, 0); | |
627 | ||
96e28449 DG |
628 | local_hpte.r = pa | mode; |
629 | local_hpte.v = ((va >> 23) << HPTE_V_AVPN_SHIFT) | |
630 | | HPTE_V_BOLTED | HPTE_V_VALID; | |
1da177e4 LT |
631 | |
632 | slot = HvCallHpt_findValid(&rhpte, vpn); | |
633 | if (slot < 0) { | |
634 | /* Must find space in primary group */ | |
635 | panic("hash_page: hpte already exists\n"); | |
636 | } | |
96e28449 | 637 | HvCallHpt_addValidate(slot, 0, &local_hpte); |
1da177e4 LT |
638 | } |
639 | ||
640 | /* | |
641 | * Bolt the kernel addr space into the HPT | |
642 | */ | |
643 | static void __init iSeries_bolt_kernel(unsigned long saddr, unsigned long eaddr) | |
644 | { | |
645 | unsigned long pa; | |
646 | unsigned long mode_rw = _PAGE_ACCESSED | _PAGE_COHERENT | PP_RWXX; | |
96e28449 | 647 | hpte_t hpte; |
1da177e4 LT |
648 | |
649 | for (pa = saddr; pa < eaddr ;pa += PAGE_SIZE) { | |
650 | unsigned long ea = (unsigned long)__va(pa); | |
651 | unsigned long vsid = get_kernel_vsid(ea); | |
652 | unsigned long va = (vsid << 28) | (pa & 0xfffffff); | |
653 | unsigned long vpn = va >> PAGE_SHIFT; | |
654 | unsigned long slot = HvCallHpt_findValid(&hpte, vpn); | |
655 | ||
656 | /* Make non-kernel text non-executable */ | |
657 | if (!in_kernel_text(ea)) | |
658 | mode_rw |= HW_NO_EXEC; | |
659 | ||
96e28449 | 660 | if (hpte.v & HPTE_V_VALID) { |
1da177e4 LT |
661 | /* HPTE exists, so just bolt it */ |
662 | HvCallHpt_setSwBits(slot, 0x10, 0); | |
663 | /* And make sure the pp bits are correct */ | |
664 | HvCallHpt_setPp(slot, PP_RWXX); | |
665 | } else | |
666 | /* No HPTE exists, so create a new bolted one */ | |
667 | iSeries_make_pte(va, phys_to_abs(pa), mode_rw); | |
668 | } | |
669 | } | |
670 | ||
1da177e4 LT |
671 | /* |
672 | * Document me. | |
673 | */ | |
674 | static void __init iSeries_setup_arch(void) | |
675 | { | |
1da177e4 LT |
676 | unsigned procIx = get_paca()->lppaca.dyn_hv_phys_proc_index; |
677 | ||
678 | /* Add an eye catcher and the systemcfg layout version number */ | |
679 | strcpy(systemcfg->eye_catcher, "SYSTEMCFG:PPC64"); | |
680 | systemcfg->version.major = SYSTEMCFG_MAJOR; | |
681 | systemcfg->version.minor = SYSTEMCFG_MINOR; | |
682 | ||
683 | /* Setup the Lp Event Queue */ | |
512d31d6 | 684 | setup_hvlpevent_queue(); |
1da177e4 LT |
685 | |
686 | /* Compute processor frequency */ | |
687 | procFreqHz = ((1UL << 34) * 1000000) / | |
688 | xIoHriProcessorVpd[procIx].xProcFreq; | |
689 | procFreqMhz = procFreqHz / 1000000; | |
690 | procFreqMhzHundreths = (procFreqHz / 10000) - (procFreqMhz * 100); | |
691 | ppc_proc_freq = procFreqHz; | |
692 | ||
693 | /* Compute time base frequency */ | |
694 | tbFreqHz = ((1UL << 32) * 1000000) / | |
695 | xIoHriProcessorVpd[procIx].xTimeBaseFreq; | |
696 | tbFreqMhz = tbFreqHz / 1000000; | |
697 | tbFreqMhzHundreths = (tbFreqHz / 10000) - (tbFreqMhz * 100); | |
698 | ppc_tb_freq = tbFreqHz; | |
699 | ||
700 | printk("Max logical processors = %d\n", | |
701 | itVpdAreas.xSlicMaxLogicalProcs); | |
702 | printk("Max physical processors = %d\n", | |
703 | itVpdAreas.xSlicMaxPhysicalProcs); | |
704 | printk("Processor frequency = %lu.%02lu\n", procFreqMhz, | |
705 | procFreqMhzHundreths); | |
706 | printk("Time base frequency = %lu.%02lu\n", tbFreqMhz, | |
707 | tbFreqMhzHundreths); | |
708 | systemcfg->processor = xIoHriProcessorVpd[procIx].xPVR; | |
709 | printk("Processor version = %x\n", systemcfg->processor); | |
710 | } | |
711 | ||
712 | static void iSeries_get_cpuinfo(struct seq_file *m) | |
713 | { | |
714 | seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n"); | |
715 | } | |
716 | ||
717 | /* | |
718 | * Document me. | |
719 | * and Implement me. | |
720 | */ | |
721 | static int iSeries_get_irq(struct pt_regs *regs) | |
722 | { | |
723 | /* -2 means ignore this interrupt */ | |
724 | return -2; | |
725 | } | |
726 | ||
727 | /* | |
728 | * Document me. | |
729 | */ | |
730 | static void iSeries_restart(char *cmd) | |
731 | { | |
732 | mf_reboot(); | |
733 | } | |
734 | ||
735 | /* | |
736 | * Document me. | |
737 | */ | |
738 | static void iSeries_power_off(void) | |
739 | { | |
740 | mf_power_off(); | |
741 | } | |
742 | ||
743 | /* | |
744 | * Document me. | |
745 | */ | |
746 | static void iSeries_halt(void) | |
747 | { | |
748 | mf_power_off(); | |
749 | } | |
750 | ||
1da177e4 LT |
751 | /* |
752 | * void __init iSeries_calibrate_decr() | |
753 | * | |
754 | * Description: | |
755 | * This routine retrieves the internal processor frequency from the VPD, | |
756 | * and sets up the kernel timer decrementer based on that value. | |
757 | * | |
758 | */ | |
759 | static void __init iSeries_calibrate_decr(void) | |
760 | { | |
761 | unsigned long cyclesPerUsec; | |
762 | struct div_result divres; | |
763 | ||
764 | /* Compute decrementer (and TB) frequency in cycles/sec */ | |
765 | cyclesPerUsec = ppc_tb_freq / 1000000; | |
766 | ||
767 | /* | |
768 | * Set the amount to refresh the decrementer by. This | |
769 | * is the number of decrementer ticks it takes for | |
770 | * 1/HZ seconds. | |
771 | */ | |
772 | tb_ticks_per_jiffy = ppc_tb_freq / HZ; | |
773 | ||
774 | #if 0 | |
775 | /* TEST CODE FOR ADJTIME */ | |
776 | tb_ticks_per_jiffy += tb_ticks_per_jiffy / 5000; | |
777 | /* END OF TEST CODE */ | |
778 | #endif | |
779 | ||
780 | /* | |
781 | * tb_ticks_per_sec = freq; would give better accuracy | |
782 | * but tb_ticks_per_sec = tb_ticks_per_jiffy*HZ; assures | |
783 | * that jiffies (and xtime) will match the time returned | |
784 | * by do_gettimeofday. | |
785 | */ | |
786 | tb_ticks_per_sec = tb_ticks_per_jiffy * HZ; | |
787 | tb_ticks_per_usec = cyclesPerUsec; | |
788 | tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000); | |
789 | div128_by_32(1024 * 1024, 0, tb_ticks_per_sec, &divres); | |
790 | tb_to_xs = divres.result_low; | |
791 | setup_default_decr(); | |
792 | } | |
793 | ||
794 | static void __init iSeries_progress(char * st, unsigned short code) | |
795 | { | |
796 | printk("Progress: [%04x] - %s\n", (unsigned)code, st); | |
797 | if (!piranha_simulator && mf_initialized) { | |
798 | if (code != 0xffff) | |
799 | mf_display_progress(code); | |
800 | else | |
801 | mf_clear_src(); | |
802 | } | |
803 | } | |
804 | ||
805 | static void __init iSeries_fixup_klimit(void) | |
806 | { | |
807 | /* | |
808 | * Change klimit to take into account any ram disk | |
809 | * that may be included | |
810 | */ | |
811 | if (naca.xRamDisk) | |
812 | klimit = KERNELBASE + (u64)naca.xRamDisk + | |
813 | (naca.xRamDiskSize * PAGE_SIZE); | |
814 | else { | |
815 | /* | |
816 | * No ram disk was included - check and see if there | |
817 | * was an embedded system map. Change klimit to take | |
818 | * into account any embedded system map | |
819 | */ | |
820 | if (embedded_sysmap_end) | |
821 | klimit = KERNELBASE + ((embedded_sysmap_end + 4095) & | |
822 | 0xfffffffffffff000); | |
823 | } | |
824 | } | |
825 | ||
826 | static int __init iSeries_src_init(void) | |
827 | { | |
828 | /* clear the progress line */ | |
829 | ppc_md.progress(" ", 0xffff); | |
830 | return 0; | |
831 | } | |
832 | ||
833 | late_initcall(iSeries_src_init); | |
834 | ||
d200903e ME |
835 | static inline void process_iSeries_events(void) |
836 | { | |
837 | asm volatile ("li 0,0x5555; sc" : : : "r0", "r3"); | |
838 | } | |
839 | ||
840 | static void yield_shared_processor(void) | |
841 | { | |
842 | unsigned long tb; | |
d200903e ME |
843 | |
844 | HvCall_setEnabledInterrupts(HvCall_MaskIPI | | |
845 | HvCall_MaskLpEvent | | |
846 | HvCall_MaskLpProd | | |
847 | HvCall_MaskTimeout); | |
848 | ||
849 | tb = get_tb(); | |
850 | /* Compute future tb value when yield should expire */ | |
851 | HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy); | |
852 | ||
d200903e ME |
853 | /* |
854 | * The decrementer stops during the yield. Force a fake decrementer | |
855 | * here and let the timer_interrupt code sort out the actual time. | |
856 | */ | |
857 | get_paca()->lppaca.int_dword.fields.decr_int = 1; | |
858 | process_iSeries_events(); | |
859 | } | |
860 | ||
3c57bb9f | 861 | static int iseries_shared_idle(void) |
d200903e | 862 | { |
3c57bb9f AB |
863 | while (1) { |
864 | while (!need_resched() && !hvlpevent_is_pending()) { | |
865 | local_irq_disable(); | |
866 | ppc64_runlatch_off(); | |
867 | ||
868 | /* Recheck with irqs off */ | |
869 | if (!need_resched() && !hvlpevent_is_pending()) | |
870 | yield_shared_processor(); | |
d200903e | 871 | |
3c57bb9f AB |
872 | HMT_medium(); |
873 | local_irq_enable(); | |
874 | } | |
875 | ||
876 | ppc64_runlatch_on(); | |
d200903e | 877 | |
3c57bb9f AB |
878 | if (hvlpevent_is_pending()) |
879 | process_iSeries_events(); | |
880 | ||
881 | schedule(); | |
882 | } | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
887 | static int iseries_dedicated_idle(void) | |
888 | { | |
3c57bb9f | 889 | long oldval; |
d200903e ME |
890 | |
891 | while (1) { | |
3c57bb9f | 892 | oldval = test_and_clear_thread_flag(TIF_NEED_RESCHED); |
d200903e | 893 | |
3c57bb9f AB |
894 | if (!oldval) { |
895 | set_thread_flag(TIF_POLLING_NRFLAG); | |
d200903e | 896 | |
3c57bb9f AB |
897 | while (!need_resched()) { |
898 | ppc64_runlatch_off(); | |
899 | HMT_low(); | |
900 | ||
901 | if (hvlpevent_is_pending()) { | |
d200903e | 902 | HMT_medium(); |
3c57bb9f AB |
903 | ppc64_runlatch_on(); |
904 | process_iSeries_events(); | |
d200903e | 905 | } |
d200903e | 906 | } |
3c57bb9f AB |
907 | |
908 | HMT_medium(); | |
909 | clear_thread_flag(TIF_POLLING_NRFLAG); | |
910 | } else { | |
911 | set_need_resched(); | |
d200903e ME |
912 | } |
913 | ||
914 | ppc64_runlatch_on(); | |
915 | schedule(); | |
d200903e ME |
916 | } |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
145d01e4 SR |
921 | #ifndef CONFIG_PCI |
922 | void __init iSeries_init_IRQ(void) { } | |
923 | #endif | |
924 | ||
1da177e4 LT |
925 | void __init iSeries_early_setup(void) |
926 | { | |
927 | iSeries_fixup_klimit(); | |
928 | ||
929 | ppc_md.setup_arch = iSeries_setup_arch; | |
930 | ppc_md.get_cpuinfo = iSeries_get_cpuinfo; | |
931 | ppc_md.init_IRQ = iSeries_init_IRQ; | |
932 | ppc_md.get_irq = iSeries_get_irq; | |
933 | ppc_md.init_early = iSeries_init_early, | |
934 | ||
935 | ppc_md.pcibios_fixup = iSeries_pci_final_fixup; | |
936 | ||
937 | ppc_md.restart = iSeries_restart; | |
938 | ppc_md.power_off = iSeries_power_off; | |
939 | ppc_md.halt = iSeries_halt; | |
940 | ||
941 | ppc_md.get_boot_time = iSeries_get_boot_time; | |
942 | ppc_md.set_rtc_time = iSeries_set_rtc_time; | |
943 | ppc_md.get_rtc_time = iSeries_get_rtc_time; | |
944 | ppc_md.calibrate_decr = iSeries_calibrate_decr; | |
945 | ppc_md.progress = iSeries_progress; | |
3c57bb9f | 946 | |
b6bff397 | 947 | if (get_paca()->lppaca.shared_proc) { |
3c57bb9f | 948 | ppc_md.idle_loop = iseries_shared_idle; |
b6bff397 ME |
949 | printk(KERN_INFO "Using shared processor idle loop\n"); |
950 | } else { | |
3c57bb9f | 951 | ppc_md.idle_loop = iseries_dedicated_idle; |
b6bff397 ME |
952 | printk(KERN_INFO "Using dedicated idle loop\n"); |
953 | } | |
1da177e4 LT |
954 | } |
955 |