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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), | |
3 | * IBM Corp. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #define DEBUG | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/bootmem.h> | |
19 | ||
20 | #include <asm/sections.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/prom.h> | |
23 | #include <asm/pci-bridge.h> | |
24 | #include <asm/machdep.h> | |
25 | #include <asm/iommu.h> | |
d387899f | 26 | #include <asm/ppc-pci.h> |
1da177e4 LT |
27 | |
28 | #ifdef DEBUG | |
29 | #define DBG(x...) printk(x) | |
30 | #else | |
31 | #define DBG(x...) | |
32 | #endif | |
33 | ||
34 | static struct pci_controller *u3_agp, *u3_ht; | |
35 | ||
36 | static int __init fixup_one_level_bus_range(struct device_node *node, int higher) | |
37 | { | |
38 | for (; node != 0;node = node->sibling) { | |
39 | int * bus_range; | |
40 | unsigned int *class_code; | |
41 | int len; | |
42 | ||
43 | /* For PCI<->PCI bridges or CardBus bridges, we go down */ | |
44 | class_code = (unsigned int *) get_property(node, "class-code", NULL); | |
45 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && | |
46 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
47 | continue; | |
48 | bus_range = (int *) get_property(node, "bus-range", &len); | |
49 | if (bus_range != NULL && len > 2 * sizeof(int)) { | |
50 | if (bus_range[1] > higher) | |
51 | higher = bus_range[1]; | |
52 | } | |
53 | higher = fixup_one_level_bus_range(node->child, higher); | |
54 | } | |
55 | return higher; | |
56 | } | |
57 | ||
58 | /* This routine fixes the "bus-range" property of all bridges in the | |
59 | * system since they tend to have their "last" member wrong on macs | |
60 | * | |
61 | * Note that the bus numbers manipulated here are OF bus numbers, they | |
62 | * are not Linux bus numbers. | |
63 | */ | |
64 | static void __init fixup_bus_range(struct device_node *bridge) | |
65 | { | |
66 | int * bus_range; | |
67 | int len; | |
68 | ||
69 | /* Lookup the "bus-range" property for the hose */ | |
70 | bus_range = (int *) get_property(bridge, "bus-range", &len); | |
71 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
72 | printk(KERN_WARNING "Can't get bus-range for %s\n", | |
73 | bridge->full_name); | |
74 | return; | |
75 | } | |
76 | bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); | |
77 | } | |
78 | ||
79 | ||
80 | #define U3_AGP_CFA0(devfn, off) \ | |
81 | ((1 << (unsigned long)PCI_SLOT(dev_fn)) \ | |
82 | | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \ | |
83 | | (((unsigned long)(off)) & 0xFCUL)) | |
84 | ||
85 | #define U3_AGP_CFA1(bus, devfn, off) \ | |
86 | ((((unsigned long)(bus)) << 16) \ | |
87 | |(((unsigned long)(devfn)) << 8) \ | |
88 | |(((unsigned long)(off)) & 0xFCUL) \ | |
89 | |1UL) | |
90 | ||
91 | static unsigned long u3_agp_cfg_access(struct pci_controller* hose, | |
92 | u8 bus, u8 dev_fn, u8 offset) | |
93 | { | |
94 | unsigned int caddr; | |
95 | ||
96 | if (bus == hose->first_busno) { | |
97 | if (dev_fn < (11 << 3)) | |
98 | return 0; | |
99 | caddr = U3_AGP_CFA0(dev_fn, offset); | |
100 | } else | |
101 | caddr = U3_AGP_CFA1(bus, dev_fn, offset); | |
102 | ||
103 | /* Uninorth will return garbage if we don't read back the value ! */ | |
104 | do { | |
105 | out_le32(hose->cfg_addr, caddr); | |
106 | } while (in_le32(hose->cfg_addr) != caddr); | |
107 | ||
108 | offset &= 0x07; | |
109 | return ((unsigned long)hose->cfg_data) + offset; | |
110 | } | |
111 | ||
112 | static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn, | |
113 | int offset, int len, u32 *val) | |
114 | { | |
115 | struct pci_controller *hose; | |
116 | unsigned long addr; | |
117 | ||
118 | hose = pci_bus_to_host(bus); | |
119 | if (hose == NULL) | |
120 | return PCIBIOS_DEVICE_NOT_FOUND; | |
121 | ||
122 | addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); | |
123 | if (!addr) | |
124 | return PCIBIOS_DEVICE_NOT_FOUND; | |
125 | /* | |
126 | * Note: the caller has already checked that offset is | |
127 | * suitably aligned and that len is 1, 2 or 4. | |
128 | */ | |
129 | switch (len) { | |
130 | case 1: | |
131 | *val = in_8((u8 *)addr); | |
132 | break; | |
133 | case 2: | |
134 | *val = in_le16((u16 *)addr); | |
135 | break; | |
136 | default: | |
137 | *val = in_le32((u32 *)addr); | |
138 | break; | |
139 | } | |
140 | return PCIBIOS_SUCCESSFUL; | |
141 | } | |
142 | ||
143 | static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn, | |
144 | int offset, int len, u32 val) | |
145 | { | |
146 | struct pci_controller *hose; | |
147 | unsigned long addr; | |
148 | ||
149 | hose = pci_bus_to_host(bus); | |
150 | if (hose == NULL) | |
151 | return PCIBIOS_DEVICE_NOT_FOUND; | |
152 | ||
153 | addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); | |
154 | if (!addr) | |
155 | return PCIBIOS_DEVICE_NOT_FOUND; | |
156 | /* | |
157 | * Note: the caller has already checked that offset is | |
158 | * suitably aligned and that len is 1, 2 or 4. | |
159 | */ | |
160 | switch (len) { | |
161 | case 1: | |
162 | out_8((u8 *)addr, val); | |
163 | (void) in_8((u8 *)addr); | |
164 | break; | |
165 | case 2: | |
166 | out_le16((u16 *)addr, val); | |
167 | (void) in_le16((u16 *)addr); | |
168 | break; | |
169 | default: | |
170 | out_le32((u32 *)addr, val); | |
171 | (void) in_le32((u32 *)addr); | |
172 | break; | |
173 | } | |
174 | return PCIBIOS_SUCCESSFUL; | |
175 | } | |
176 | ||
177 | static struct pci_ops u3_agp_pci_ops = | |
178 | { | |
179 | u3_agp_read_config, | |
180 | u3_agp_write_config | |
181 | }; | |
182 | ||
183 | ||
184 | #define U3_HT_CFA0(devfn, off) \ | |
185 | ((((unsigned long)devfn) << 8) | offset) | |
186 | #define U3_HT_CFA1(bus, devfn, off) \ | |
187 | (U3_HT_CFA0(devfn, off) \ | |
188 | + (((unsigned long)bus) << 16) \ | |
189 | + 0x01000000UL) | |
190 | ||
191 | static unsigned long u3_ht_cfg_access(struct pci_controller* hose, | |
192 | u8 bus, u8 devfn, u8 offset) | |
193 | { | |
194 | if (bus == hose->first_busno) { | |
195 | if (PCI_SLOT(devfn) == 0) | |
196 | return 0; | |
197 | return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset); | |
198 | } else | |
199 | return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); | |
200 | } | |
201 | ||
202 | static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, | |
203 | int offset, int len, u32 *val) | |
204 | { | |
205 | struct pci_controller *hose; | |
206 | unsigned long addr; | |
207 | ||
208 | hose = pci_bus_to_host(bus); | |
209 | if (hose == NULL) | |
210 | return PCIBIOS_DEVICE_NOT_FOUND; | |
211 | ||
212 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); | |
213 | if (!addr) | |
214 | return PCIBIOS_DEVICE_NOT_FOUND; | |
215 | ||
216 | /* | |
217 | * Note: the caller has already checked that offset is | |
218 | * suitably aligned and that len is 1, 2 or 4. | |
219 | */ | |
220 | switch (len) { | |
221 | case 1: | |
222 | *val = in_8((u8 *)addr); | |
223 | break; | |
224 | case 2: | |
225 | *val = in_le16((u16 *)addr); | |
226 | break; | |
227 | default: | |
228 | *val = in_le32((u32 *)addr); | |
229 | break; | |
230 | } | |
231 | return PCIBIOS_SUCCESSFUL; | |
232 | } | |
233 | ||
234 | static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, | |
235 | int offset, int len, u32 val) | |
236 | { | |
237 | struct pci_controller *hose; | |
238 | unsigned long addr; | |
239 | ||
240 | hose = pci_bus_to_host(bus); | |
241 | if (hose == NULL) | |
242 | return PCIBIOS_DEVICE_NOT_FOUND; | |
243 | ||
244 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); | |
245 | if (!addr) | |
246 | return PCIBIOS_DEVICE_NOT_FOUND; | |
247 | /* | |
248 | * Note: the caller has already checked that offset is | |
249 | * suitably aligned and that len is 1, 2 or 4. | |
250 | */ | |
251 | switch (len) { | |
252 | case 1: | |
253 | out_8((u8 *)addr, val); | |
254 | (void) in_8((u8 *)addr); | |
255 | break; | |
256 | case 2: | |
257 | out_le16((u16 *)addr, val); | |
258 | (void) in_le16((u16 *)addr); | |
259 | break; | |
260 | default: | |
261 | out_le32((u32 *)addr, val); | |
262 | (void) in_le32((u32 *)addr); | |
263 | break; | |
264 | } | |
265 | return PCIBIOS_SUCCESSFUL; | |
266 | } | |
267 | ||
268 | static struct pci_ops u3_ht_pci_ops = | |
269 | { | |
270 | u3_ht_read_config, | |
271 | u3_ht_write_config | |
272 | }; | |
273 | ||
274 | static void __init setup_u3_agp(struct pci_controller* hose) | |
275 | { | |
276 | /* On G5, we move AGP up to high bus number so we don't need | |
277 | * to reassign bus numbers for HT. If we ever have P2P bridges | |
399fe2bd | 278 | * on AGP, we'll have to move pci_assign_all_buses to the |
1da177e4 LT |
279 | * pci_controller structure so we enable it for AGP and not for |
280 | * HT childs. | |
281 | * We hard code the address because of the different size of | |
282 | * the reg address cell, we shall fix that by killing struct | |
283 | * reg_property and using some accessor functions instead | |
284 | */ | |
3238e9c9 | 285 | hose->first_busno = 0xf0; |
1da177e4 LT |
286 | hose->last_busno = 0xff; |
287 | hose->ops = &u3_agp_pci_ops; | |
288 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
289 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
290 | ||
291 | u3_agp = hose; | |
292 | } | |
293 | ||
294 | static void __init setup_u3_ht(struct pci_controller* hose) | |
295 | { | |
296 | hose->ops = &u3_ht_pci_ops; | |
297 | ||
298 | /* We hard code the address because of the different size of | |
299 | * the reg address cell, we shall fix that by killing struct | |
300 | * reg_property and using some accessor functions instead | |
301 | */ | |
302 | hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); | |
303 | ||
304 | hose->first_busno = 0; | |
305 | hose->last_busno = 0xef; | |
306 | ||
307 | u3_ht = hose; | |
308 | } | |
309 | ||
310 | static int __init add_bridge(struct device_node *dev) | |
311 | { | |
312 | int len; | |
313 | struct pci_controller *hose; | |
314 | char* disp_name; | |
315 | int *bus_range; | |
316 | int primary = 1; | |
3238e9c9 | 317 | struct property *of_prop; |
1da177e4 LT |
318 | |
319 | DBG("Adding PCI host bridge %s\n", dev->full_name); | |
320 | ||
3238e9c9 AB |
321 | bus_range = (int *) get_property(dev, "bus-range", &len); |
322 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
323 | printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n", | |
324 | dev->full_name); | |
325 | } | |
1da177e4 LT |
326 | |
327 | hose = alloc_bootmem(sizeof(struct pci_controller)); | |
328 | if (hose == NULL) | |
329 | return -ENOMEM; | |
3238e9c9 | 330 | pci_setup_pci_controller(hose); |
1da177e4 | 331 | |
3238e9c9 AB |
332 | hose->arch_data = dev; |
333 | hose->first_busno = bus_range ? bus_range[0] : 0; | |
334 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
1da177e4 LT |
335 | |
336 | of_prop = alloc_bootmem(sizeof(struct property) + | |
337 | sizeof(hose->global_number)); | |
338 | if (of_prop) { | |
339 | memset(of_prop, 0, sizeof(struct property)); | |
340 | of_prop->name = "linux,pci-domain"; | |
341 | of_prop->length = sizeof(hose->global_number); | |
342 | of_prop->value = (unsigned char *)&of_prop[1]; | |
343 | memcpy(of_prop->value, &hose->global_number, sizeof(hose->global_number)); | |
344 | prom_add_property(dev, of_prop); | |
345 | } | |
346 | ||
347 | disp_name = NULL; | |
3238e9c9 AB |
348 | if (device_is_compatible(dev, "u3-agp")) { |
349 | setup_u3_agp(hose); | |
350 | disp_name = "U3-AGP"; | |
351 | primary = 0; | |
352 | } else if (device_is_compatible(dev, "u3-ht")) { | |
353 | setup_u3_ht(hose); | |
354 | disp_name = "U3-HT"; | |
355 | primary = 1; | |
356 | } | |
357 | printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n", | |
358 | disp_name, hose->first_busno, hose->last_busno); | |
359 | ||
360 | /* Interpret the "ranges" property */ | |
361 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
362 | pci_process_bridge_OF_ranges(hose, dev); | |
1da177e4 LT |
363 | pci_setup_phb_io(hose, primary); |
364 | ||
3238e9c9 AB |
365 | /* Fixup "bus-range" OF property */ |
366 | fixup_bus_range(dev); | |
1da177e4 LT |
367 | |
368 | return 0; | |
369 | } | |
370 | ||
371 | ||
372 | void __init maple_pcibios_fixup(void) | |
373 | { | |
374 | struct pci_dev *dev = NULL; | |
375 | ||
376 | DBG(" -> maple_pcibios_fixup\n"); | |
377 | ||
378 | for_each_pci_dev(dev) | |
379 | pci_read_irq_line(dev); | |
380 | ||
381 | /* Do the mapping of the IO space */ | |
382 | phbs_remap_io(); | |
383 | ||
384 | DBG(" <- maple_pcibios_fixup\n"); | |
385 | } | |
386 | ||
387 | static void __init maple_fixup_phb_resources(void) | |
388 | { | |
389 | struct pci_controller *hose, *tmp; | |
390 | ||
391 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
392 | unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
393 | hose->io_resource.start += offset; | |
394 | hose->io_resource.end += offset; | |
395 | printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", | |
396 | hose->global_number, | |
397 | hose->io_resource.start, hose->io_resource.end); | |
398 | } | |
399 | } | |
400 | ||
401 | void __init maple_pci_init(void) | |
402 | { | |
403 | struct device_node *np, *root; | |
404 | struct device_node *ht = NULL; | |
405 | ||
406 | /* Probe root PCI hosts, that is on U3 the AGP host and the | |
407 | * HyperTransport host. That one is actually "kept" around | |
408 | * and actually added last as it's resource management relies | |
409 | * on the AGP resources to have been setup first | |
410 | */ | |
411 | root = of_find_node_by_path("/"); | |
412 | if (root == NULL) { | |
413 | printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n"); | |
414 | return; | |
415 | } | |
416 | for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { | |
417 | if (np->name == NULL) | |
418 | continue; | |
419 | if (strcmp(np->name, "pci") == 0) { | |
420 | if (add_bridge(np) == 0) | |
421 | of_node_get(np); | |
422 | } | |
423 | if (strcmp(np->name, "ht") == 0) { | |
424 | of_node_get(np); | |
425 | ht = np; | |
426 | } | |
427 | } | |
428 | of_node_put(root); | |
429 | ||
430 | /* Now setup the HyperTransport host if we found any | |
431 | */ | |
432 | if (ht && add_bridge(ht) != 0) | |
433 | of_node_put(ht); | |
434 | ||
435 | /* Fixup the IO resources on our host bridges as the common code | |
436 | * does it only for childs of the host bridges | |
437 | */ | |
438 | maple_fixup_phb_resources(); | |
439 | ||
440 | /* Setup the linkage between OF nodes and PHBs */ | |
441 | pci_devs_phb_init(); | |
442 | ||
443 | /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We | |
444 | * assume there is no P2P bridge on the AGP bus, which should be a | |
445 | * safe assumptions hopefully. | |
446 | */ | |
447 | if (u3_agp) { | |
448 | struct device_node *np = u3_agp->arch_data; | |
1635317f | 449 | PCI_DN(np)->busno = 0xf0; |
1da177e4 | 450 | for (np = np->child; np; np = np->sibling) |
1635317f | 451 | PCI_DN(np)->busno = 0xf0; |
1da177e4 LT |
452 | } |
453 | ||
454 | /* Tell pci.c to use the common resource allocation mecanism */ | |
455 | pci_probe_only = 0; | |
456 | ||
457 | /* Allow all IO */ | |
458 | io_page_mask = -1; | |
459 | } | |
460 | ||
461 | int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel) | |
462 | { | |
463 | struct device_node *np; | |
464 | int irq = channel ? 15 : 14; | |
465 | ||
466 | if (pdev->vendor != PCI_VENDOR_ID_AMD || | |
467 | pdev->device != PCI_DEVICE_ID_AMD_8111_IDE) | |
468 | return irq; | |
469 | ||
470 | np = pci_device_to_OF_node(pdev); | |
471 | if (np == NULL) | |
472 | return irq; | |
473 | if (np->n_intrs < 2) | |
474 | return irq; | |
475 | return np->intrs[channel & 0x1].line; | |
476 | } | |
477 | ||
478 | /* XXX: To remove once all firmwares are ok */ | |
479 | static void fixup_maple_ide(struct pci_dev* dev) | |
480 | { | |
481 | #if 0 /* Enable this to enable IDE port 0 */ | |
482 | { | |
483 | u8 v; | |
484 | ||
485 | pci_read_config_byte(dev, 0x40, &v); | |
486 | v |= 2; | |
487 | pci_write_config_byte(dev, 0x40, v); | |
488 | } | |
489 | #endif | |
490 | #if 0 /* fix bus master base */ | |
491 | pci_write_config_dword(dev, 0x20, 0xcc01); | |
492 | printk("old ide resource: %lx -> %lx \n", | |
493 | dev->resource[4].start, dev->resource[4].end); | |
494 | dev->resource[4].start = 0xcc00; | |
495 | dev->resource[4].end = 0xcc10; | |
496 | #endif | |
497 | #if 1 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */ | |
498 | { | |
499 | struct pci_dev *apicdev; | |
500 | u32 v; | |
501 | ||
502 | apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0)); | |
503 | if (apicdev == NULL) | |
504 | printk("IDE Fixup IRQ: Can't find IO-APIC !\n"); | |
505 | else { | |
506 | pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14); | |
507 | pci_read_config_dword(apicdev, 0xf4, &v); | |
508 | v &= ~0x00000022; | |
509 | pci_write_config_dword(apicdev, 0xf4, v); | |
510 | pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15); | |
511 | pci_read_config_dword(apicdev, 0xf4, &v); | |
512 | v &= ~0x00000022; | |
513 | pci_write_config_dword(apicdev, 0xf4, v); | |
514 | pci_dev_put(apicdev); | |
515 | } | |
516 | } | |
517 | #endif | |
518 | } | |
519 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, | |
520 | fixup_maple_ide); |