projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] ppc64: SMU based macs cpufreq support
[deliverable/linux.git] / arch / ppc64 / kernel / misc.S
CommitLineData
1da177e4
LT		 1/*
2 * arch/ppc/kernel/misc.S
3 *
4 *
5 *
6 * This file contains miscellaneous low-level functions.
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras.
11 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
12 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 *
19 */
20
21#include <linux/config.h>
22#include <linux/sys.h>
23#include <asm/unistd.h>
24#include <asm/errno.h>
25#include <asm/processor.h>
26#include <asm/page.h>
27#include <asm/cache.h>
28#include <asm/ppc_asm.h>
0013a854 29#include <asm/asm-offsets.h>
1da177e4 30#include <asm/cputable.h>
6cb7bfeb 31#include <asm/thread_info.h>
1da177e4
LT		 32
33 .text
34
35/*
5e2afc1d 36 * Returns (address we were linked at) - (address we are running at)
1da177e4
LT		 37 * for use before the text and data are mapped to KERNELBASE.
38 */
39
40_GLOBAL(reloc_offset)
41 mflr r0
42 bl 1f
431: mflr r3
44 LOADADDR(r4,1b)
45 sub r3,r4,r3
46 mtlr r0
47 blr
48
49_GLOBAL(get_msr)
50 mfmsr r3
51 blr
52
53_GLOBAL(get_dar)
54 mfdar r3
55 blr
56
57_GLOBAL(get_srr0)
58 mfsrr0 r3
59 blr
60
61_GLOBAL(get_srr1)
62 mfsrr1 r3
63 blr
64
65_GLOBAL(get_sp)
66 mr r3,r1
67 blr
1da177e4
LT		 68
69#ifdef CONFIG_IRQSTACKS
70_GLOBAL(call_do_softirq)
71 mflr r0
72 std r0,16(r1)
73 stdu r1,THREAD_SIZE-112(r3)
74 mr r1,r3
75 bl .__do_softirq
76 ld r1,0(r1)
77 ld r0,16(r1)
78 mtlr r0
79 blr
80
81_GLOBAL(call_handle_IRQ_event)
82 mflr r0
83 std r0,16(r1)
84 stdu r1,THREAD_SIZE-112(r6)
85 mr r1,r6
86 bl .handle_IRQ_event
87 ld r1,0(r1)
88 ld r0,16(r1)
89 mtlr r0
90 blr
91#endif /* CONFIG_IRQSTACKS */
92
93 /*
94 * To be called by C code which needs to do some operations with MMU
95 * disabled. Note that interrupts have to be disabled by the caller
96 * prior to calling us. The code called _MUST_ be in the RMO of course
97 * and part of the linear mapping as we don't attempt to translate the
98 * stack pointer at all. The function is called with the stack switched
99 * to this CPU emergency stack
100 *
101 * prototype is void *call_with_mmu_off(void *func, void *data);
102 *
103 * the called function is expected to be of the form
104 *
105 * void *called(void *data);
106 */
107_GLOBAL(call_with_mmu_off)
108 mflr r0 /* get link, save it on stackframe */
109 std r0,16(r1)
110 mr r1,r5 /* save old stack ptr */
111 ld r1,PACAEMERGSP(r13) /* get emerg. stack */
112 subi r1,r1,STACK_FRAME_OVERHEAD
113 std r0,16(r1) /* save link on emerg. stack */
114 std r5,0(r1) /* save old stack ptr in backchain */
115 ld r3,0(r3) /* get to real function ptr (assume same TOC) */
116 bl 2f /* we need LR to return, continue at label 2 */
117
118 ld r0,16(r1) /* we return here from the call, get LR and */
119 ld r1,0(r1) /* .. old stack ptr */
120 mtspr SPRN_SRR0,r0 /* and get back to virtual mode with these */
121 mfmsr r4
122 ori r4,r4,MSR_IR|MSR_DR
123 mtspr SPRN_SRR1,r4
124 rfid
125
1262: mtspr SPRN_SRR0,r3 /* coming from above, enter real mode */
127 mr r3,r4 /* get parameter */
128 mfmsr r0
129 ori r0,r0,MSR_IR|MSR_DR
130 xori r0,r0,MSR_IR|MSR_DR
131 mtspr SPRN_SRR1,r0
132 rfid
133
134
135 .section ".toc","aw"
136PPC64_CACHES:
137 .tc ppc64_caches[TC],ppc64_caches
138 .section ".text"
139
140/*
141 * Write any modified data cache blocks out to memory
142 * and invalidate the corresponding instruction cache blocks.
143 *
144 * flush_icache_range(unsigned long start, unsigned long stop)
145 *
146 * flush all bytes from start through stop-1 inclusive
147 */
148
bb144a85 149_KPROBE(__flush_icache_range)
1da177e4
LT		 150
151/*
152 * Flush the data cache to memory
153 *
154 * Different systems have different cache line sizes
155 * and in some cases i-cache and d-cache line sizes differ from
156 * each other.
157 */
158 ld r10,PPC64_CACHES@toc(r2)
159 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
160 addi r5,r7,-1
161 andc r6,r3,r5 /* round low to line bdy */
162 subf r8,r6,r4 /* compute length */
163 add r8,r8,r5 /* ensure we get enough */
164 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
165 srw. r8,r8,r9 /* compute line count */
166 beqlr /* nothing to do? */
167 mtctr r8
1681: dcbst 0,r6
169 add r6,r6,r7
170 bdnz 1b
171 sync
172
173/* Now invalidate the instruction cache */
174
175 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
176 addi r5,r7,-1
177 andc r6,r3,r5 /* round low to line bdy */
178 subf r8,r6,r4 /* compute length */
179 add r8,r8,r5
180 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
181 srw. r8,r8,r9 /* compute line count */
182 beqlr /* nothing to do? */
183 mtctr r8
1842: icbi 0,r6
185 add r6,r6,r7
186 bdnz 2b
187 isync
188 blr
bb144a85 189 .previous .text
1da177e4
LT		 190/*
191 * Like above, but only do the D-cache.
192 *
193 * flush_dcache_range(unsigned long start, unsigned long stop)
194 *
195 * flush all bytes from start to stop-1 inclusive
196 */
197_GLOBAL(flush_dcache_range)
198
199/*
200 * Flush the data cache to memory
201 *
202 * Different systems have different cache line sizes
203 */
204 ld r10,PPC64_CACHES@toc(r2)
205 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
206 addi r5,r7,-1
207 andc r6,r3,r5 /* round low to line bdy */
208 subf r8,r6,r4 /* compute length */
209 add r8,r8,r5 /* ensure we get enough */
210 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
211 srw. r8,r8,r9 /* compute line count */
212 beqlr /* nothing to do? */
213 mtctr r8
2140: dcbst 0,r6
215 add r6,r6,r7
216 bdnz 0b
217 sync
218 blr
219
220/*
221 * Like above, but works on non-mapped physical addresses.
222 * Use only for non-LPAR setups ! It also assumes real mode
223 * is cacheable. Used for flushing out the DART before using
224 * it as uncacheable memory
225 *
226 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
227 *
228 * flush all bytes from start to stop-1 inclusive
229 */
230_GLOBAL(flush_dcache_phys_range)
231 ld r10,PPC64_CACHES@toc(r2)
232 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
233 addi r5,r7,-1
234 andc r6,r3,r5 /* round low to line bdy */
235 subf r8,r6,r4 /* compute length */
236 add r8,r8,r5 /* ensure we get enough */
237 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
238 srw. r8,r8,r9 /* compute line count */
239 beqlr /* nothing to do? */
240 mfmsr r5 /* Disable MMU Data Relocation */
241 ori r0,r5,MSR_DR
242 xori r0,r0,MSR_DR
243 sync
244 mtmsr r0
245 sync
246 isync
247 mtctr r8
2480: dcbst 0,r6
249 add r6,r6,r7
250 bdnz 0b
251 sync
252 isync
253 mtmsr r5 /* Re-enable MMU Data Relocation */
254 sync
255 isync
256 blr
257
258_GLOBAL(flush_inval_dcache_range)
259 ld r10,PPC64_CACHES@toc(r2)
260 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
261 addi r5,r7,-1
262 andc r6,r3,r5 /* round low to line bdy */
263 subf r8,r6,r4 /* compute length */
264 add r8,r8,r5 /* ensure we get enough */
265 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
266 srw. r8,r8,r9 /* compute line count */
267 beqlr /* nothing to do? */
268 sync
269 isync
270 mtctr r8
2710: dcbf 0,r6
272 add r6,r6,r7
273 bdnz 0b
274 sync
275 isync
276 blr
277
278
279/*
280 * Flush a particular page from the data cache to RAM.
281 * Note: this is necessary because the instruction cache does *not*
282 * snoop from the data cache.
283 *
284 * void __flush_dcache_icache(void *page)
285 */
286_GLOBAL(__flush_dcache_icache)
287/*
288 * Flush the data cache to memory
289 *
290 * Different systems have different cache line sizes
291 */
292
293/* Flush the dcache */
294 ld r7,PPC64_CACHES@toc(r2)
637a6ff6 295 clrrdi r3,r3,PAGE_SHIFT /* Page align */
1da177e4
LT		 296 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
297 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
298 mr r6,r3
299 mtctr r4
3000: dcbst 0,r6
301 add r6,r6,r5
302 bdnz 0b
303 sync
304
305/* Now invalidate the icache */
306
307 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
308 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
309 mtctr r4
3101: icbi 0,r3
311 add r3,r3,r5
312 bdnz 1b
313 isync
314 blr
315
316/*
317 * I/O string operations
318 *
319 * insb(port, buf, len)
320 * outsb(port, buf, len)
321 * insw(port, buf, len)
322 * outsw(port, buf, len)
323 * insl(port, buf, len)
324 * outsl(port, buf, len)
325 * insw_ns(port, buf, len)
326 * outsw_ns(port, buf, len)
327 * insl_ns(port, buf, len)
328 * outsl_ns(port, buf, len)
329 *
330 * The *_ns versions don't do byte-swapping.
331 */
332_GLOBAL(_insb)
333 cmpwi 0,r5,0
334 mtctr r5
335 subi r4,r4,1
336 blelr-
33700: lbz r5,0(r3)
338 eieio
339 stbu r5,1(r4)
340 bdnz 00b
341 twi 0,r5,0
342 isync
343 blr
344
345_GLOBAL(_outsb)
346 cmpwi 0,r5,0
347 mtctr r5
348 subi r4,r4,1
349 blelr-
35000: lbzu r5,1(r4)
351 stb r5,0(r3)
352 bdnz 00b
353 sync
354 blr
355
356_GLOBAL(_insw)
357 cmpwi 0,r5,0
358 mtctr r5
359 subi r4,r4,2
360 blelr-
36100: lhbrx r5,0,r3
362 eieio
363 sthu r5,2(r4)
364 bdnz 00b
365 twi 0,r5,0
366 isync
367 blr
368
369_GLOBAL(_outsw)
370 cmpwi 0,r5,0
371 mtctr r5
372 subi r4,r4,2
373 blelr-
37400: lhzu r5,2(r4)
375 sthbrx r5,0,r3
376 bdnz 00b
377 sync
378 blr
379
380_GLOBAL(_insl)
381 cmpwi 0,r5,0
382 mtctr r5
383 subi r4,r4,4
384 blelr-
38500: lwbrx r5,0,r3
386 eieio
387 stwu r5,4(r4)
388 bdnz 00b
389 twi 0,r5,0
390 isync
391 blr
392
393_GLOBAL(_outsl)
394 cmpwi 0,r5,0
395 mtctr r5
396 subi r4,r4,4
397 blelr-
39800: lwzu r5,4(r4)
399 stwbrx r5,0,r3
400 bdnz 00b
401 sync
402 blr
403
404/* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */
405_GLOBAL(_insw_ns)
406 cmpwi 0,r5,0
407 mtctr r5
408 subi r4,r4,2
409 blelr-
41000: lhz r5,0(r3)
411 eieio
412 sthu r5,2(r4)
413 bdnz 00b
414 twi 0,r5,0
415 isync
416 blr
417
418/* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */
419_GLOBAL(_outsw_ns)
420 cmpwi 0,r5,0
421 mtctr r5
422 subi r4,r4,2
423 blelr-
42400: lhzu r5,2(r4)
425 sth r5,0(r3)
426 bdnz 00b
427 sync
428 blr
429
430_GLOBAL(_insl_ns)
431 cmpwi 0,r5,0
432 mtctr r5
433 subi r4,r4,4
434 blelr-
43500: lwz r5,0(r3)
436 eieio
437 stwu r5,4(r4)
438 bdnz 00b
439 twi 0,r5,0
440 isync
441 blr
442
443_GLOBAL(_outsl_ns)
444 cmpwi 0,r5,0
445 mtctr r5
446 subi r4,r4,4
447 blelr-
44800: lwzu r5,4(r4)
449 stw r5,0(r3)
450 bdnz 00b
451 sync
452 blr
453
1da177e4
LT		 454/*
455 * identify_cpu and calls setup_cpu
456 * In: r3 = base of the cpu_specs array
457 * r4 = address of cur_cpu_spec
458 * r5 = relocation offset
459 */
460_GLOBAL(identify_cpu)
461 mfpvr r7
4621:
463 lwz r8,CPU_SPEC_PVR_MASK(r3)
464 and r8,r8,r7
465 lwz r9,CPU_SPEC_PVR_VALUE(r3)
466 cmplw 0,r9,r8
467 beq 1f
468 addi r3,r3,CPU_SPEC_ENTRY_SIZE
469 b 1b
4701:
471 add r0,r3,r5
472 std r0,0(r4)
473 ld r4,CPU_SPEC_SETUP(r3)
474 sub r4,r4,r5
475 ld r4,0(r4)
476 sub r4,r4,r5
477 mtctr r4
478 /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
479 mr r4,r3
480 mr r3,r5
481 bctr
482
483/*
484 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
485 * and writes nop's over sections of code that don't apply for this cpu.
486 * r3 = data offset (not changed)
487 */
488_GLOBAL(do_cpu_ftr_fixups)
489 /* Get CPU 0 features */
490 LOADADDR(r6,cur_cpu_spec)
491 sub r6,r6,r3
492 ld r4,0(r6)
493 sub r4,r4,r3
494 ld r4,CPU_SPEC_FEATURES(r4)
495 /* Get the fixup table */
496 LOADADDR(r6,__start___ftr_fixup)
497 sub r6,r6,r3
498 LOADADDR(r7,__stop___ftr_fixup)
499 sub r7,r7,r3
500 /* Do the fixup */
5011: cmpld r6,r7
502 bgelr
503 addi r6,r6,32
504 ld r8,-32(r6) /* mask */
505 and r8,r8,r4
506 ld r9,-24(r6) /* value */
507 cmpld r8,r9
508 beq 1b
509 ld r8,-16(r6) /* section begin */
510 ld r9,-8(r6) /* section end */
511 subf. r9,r8,r9
512 beq 1b
513 /* write nops over the section of code */
514 /* todo: if large section, add a branch at the start of it */
515 srwi r9,r9,2
516 mtctr r9
517 sub r8,r8,r3
518 lis r0,0x60000000@h /* nop */
5193: stw r0,0(r8)
520 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
521 beq 2f
522 dcbst 0,r8 /* suboptimal, but simpler */
523 sync
524 icbi 0,r8
5252: addi r8,r8,4
526 bdnz 3b
527 sync /* additional sync needed on g4 */
528 isync
529 b 1b
530
531#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
532/*
533 * Do an IO access in real mode
534 */
535_GLOBAL(real_readb)
536 mfmsr r7
537 ori r0,r7,MSR_DR
538 xori r0,r0,MSR_DR
539 sync
540 mtmsrd r0
541 sync
542 isync
543 mfspr r6,SPRN_HID4
544 rldicl r5,r6,32,0
545 ori r5,r5,0x100
546 rldicl r5,r5,32,0
547 sync
548 mtspr SPRN_HID4,r5
549 isync
550 slbia
551 isync
552 lbz r3,0(r3)
553 sync
554 mtspr SPRN_HID4,r6
555 isync
556 slbia
557 isync
558 mtmsrd r7
559 sync
560 isync
561 blr
562
4350147a 563/*
1da177e4
LT		 564 * Do an IO access in real mode
565 */
566_GLOBAL(real_writeb)
567 mfmsr r7
568 ori r0,r7,MSR_DR
569 xori r0,r0,MSR_DR
570 sync
571 mtmsrd r0
572 sync
573 isync
574 mfspr r6,SPRN_HID4
575 rldicl r5,r6,32,0
576 ori r5,r5,0x100
577 rldicl r5,r5,32,0
578 sync
579 mtspr SPRN_HID4,r5
580 isync
581 slbia
582 isync
583 stb r3,0(r4)
584 sync
585 mtspr SPRN_HID4,r6
586 isync
587 slbia
588 isync
589 mtmsrd r7
590 sync
591 isync
592 blr
593#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
594
4350147a
BH		 595/*
596 * SCOM access functions for 970 (FX only for now)
597 *
598 * unsigned long scom970_read(unsigned int address);
599 * void scom970_write(unsigned int address, unsigned long value);
600 *
601 * The address passed in is the 24 bits register address. This code
602 * is 970 specific and will not check the status bits, so you should
603 * know what you are doing.
604 */
605_GLOBAL(scom970_read)
606 /* interrupts off */
607 mfmsr r4
608 ori r0,r4,MSR_EE
609 xori r0,r0,MSR_EE
610 mtmsrd r0,1
611
612 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
613 * (including parity). On current CPUs they must be 0'd,
614 * and finally or in RW bit
615 */
616 rlwinm r3,r3,8,0,15
617 ori r3,r3,0x8000
618
619 /* do the actual scom read */
620 sync
621 mtspr SPRN_SCOMC,r3
622 isync
623 mfspr r3,SPRN_SCOMD
624 isync
625 mfspr r0,SPRN_SCOMC
626 isync
627
628 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
629 * that's the best we can do). Not implemented yet as we don't use
630 * the scom on any of the bogus CPUs yet, but may have to be done
631 * ultimately
632 */
633
634 /* restore interrupts */
635 mtmsrd r4,1
636 blr
637
638
639_GLOBAL(scom970_write)
640 /* interrupts off */
641 mfmsr r5
642 ori r0,r5,MSR_EE
643 xori r0,r0,MSR_EE
644 mtmsrd r0,1
645
646 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
647 * (including parity). On current CPUs they must be 0'd.
648 */
649
650 rlwinm r3,r3,8,0,15
651
652 sync
653 mtspr SPRN_SCOMD,r4 /* write data */
654 isync
655 mtspr SPRN_SCOMC,r3 /* write command */
656 isync
657 mfspr 3,SPRN_SCOMC
658 isync
659
660 /* restore interrupts */
661 mtmsrd r5,1
662 blr
663
664
1da177e4
LT		 665/*
666 * Create a kernel thread
667 * kernel_thread(fn, arg, flags)
668 */
669_GLOBAL(kernel_thread)
670 std r29,-24(r1)
671 std r30,-16(r1)
672 stdu r1,-STACK_FRAME_OVERHEAD(r1)
673 mr r29,r3
674 mr r30,r4
675 ori r3,r5,CLONE_VM /* flags */
676 oris r3,r3,(CLONE_UNTRACED>>16)
677 li r4,0 /* new sp (unused) */
678 li r0,__NR_clone
679 sc
680 cmpdi 0,r3,0 /* parent or child? */
681 bne 1f /* return if parent */
682 li r0,0
683 stdu r0,-STACK_FRAME_OVERHEAD(r1)
684 ld r2,8(r29)
685 ld r29,0(r29)
686 mtlr r29 /* fn addr in lr */
687 mr r3,r30 /* load arg and call fn */
688 blrl
689 li r0,__NR_exit /* exit after child exits */
690 li r3,0
691 sc
6921: addi r1,r1,STACK_FRAME_OVERHEAD
693 ld r29,-24(r1)
694 ld r30,-16(r1)
695 blr
696
0ab20002
DG		 697/*
698 * disable_kernel_fp()
699 * Disable the FPU.
700 */
701_GLOBAL(disable_kernel_fp)
702 mfmsr r3
703 rldicl r0,r3,(63-MSR_FP_LG),1
704 rldicl r3,r0,(MSR_FP_LG+1),0
705 mtmsrd r3 /* disable use of fpu now */
706 isync
707 blr
708
0ab20002
DG		 709#ifdef CONFIG_ALTIVEC
710
711#if 0 /* this has no callers for now */
712/*
713 * disable_kernel_altivec()
714 * Disable the VMX.
715 */
716_GLOBAL(disable_kernel_altivec)
717 mfmsr r3
718 rldicl r0,r3,(63-MSR_VEC_LG),1
719 rldicl r3,r0,(MSR_VEC_LG+1),0
720 mtmsrd r3 /* disable use of VMX now */
721 isync
722 blr
723#endif /* 0 */
724
725/*
726 * giveup_altivec(tsk)
727 * Disable VMX for the task given as the argument,
728 * and save the vector registers in its thread_struct.
729 * Enables the VMX for use in the kernel on return.
730 */
731_GLOBAL(giveup_altivec)
732 mfmsr r5
733 oris r5,r5,MSR_VEC@h
734 mtmsrd r5 /* enable use of VMX now */
735 isync
736 cmpdi 0,r3,0
737 beqlr- /* if no previous owner, done */
738 addi r3,r3,THREAD /* want THREAD of task */
739 ld r5,PT_REGS(r3)
740 cmpdi 0,r5,0
741 SAVE_32VRS(0,r4,r3)
742 mfvscr vr0
743 li r4,THREAD_VSCR
744 stvx vr0,r4,r3
745 beq 1f
746 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
747 lis r3,MSR_VEC@h
748 andc r4,r4,r3 /* disable FP for previous task */
749 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
7501:
751#ifndef CONFIG_SMP
752 li r5,0
753 ld r4,last_task_used_altivec@got(r2)
754 std r5,0(r4)
755#endif /* CONFIG_SMP */
756 blr
757
758#endif /* CONFIG_ALTIVEC */
759
760_GLOBAL(__setup_cpu_power3)
761 blr
762
f6960123
PM		 763_GLOBAL(execve)
764 li r0,__NR_execve
765 sc
766 bnslr
767 neg r3,r3
768 blr
769
fce0d574
S		 770/* kexec_wait(phys_cpu)
771 *
772 * wait for the flag to change, indicating this kernel is going away but
773 * the slave code for the next one is at addresses 0 to 100.
774 *
775 * This is used by all slaves.
776 *
777 * Physical (hardware) cpu id should be in r3.
778 */
779_GLOBAL(kexec_wait)
780 bl 1f
7811: mflr r5
782 addi r5,r5,kexec_flag-1b
783
78499: HMT_LOW
785#ifdef CONFIG_KEXEC /* use no memory without kexec */
786 lwz r4,0(r5)
787 cmpwi 0,r4,0
788 bnea 0x60
789#endif
790 b 99b
791
792/* this can be in text because we won't change it until we are
793 * running in real anyways
794 */
795kexec_flag:
796 .long 0
797
798
799#ifdef CONFIG_KEXEC
800
801/* kexec_smp_wait(void)
802 *
803 * call with interrupts off
804 * note: this is a terminal routine, it does not save lr
805 *
806 * get phys id from paca
807 * set paca id to -1 to say we got here
808 * switch to real mode
809 * join other cpus in kexec_wait(phys_id)
810 */
811_GLOBAL(kexec_smp_wait)
812 lhz r3,PACAHWCPUID(r13)
813 li r4,-1
814 sth r4,PACAHWCPUID(r13) /* let others know we left */
815 bl real_mode
816 b .kexec_wait
817
818/*
819 * switch to real mode (turn mmu off)
820 * we use the early kernel trick that the hardware ignores bits
821 * 0 and 1 (big endian) of the effective address in real mode
822 *
823 * don't overwrite r3 here, it is live for kexec_wait above.
824 */
825real_mode: /* assume normal blr return */
8261: li r9,MSR_RI
827 li r10,MSR_DR|MSR_IR
828 mflr r11 /* return address to SRR0 */
829 mfmsr r12
830 andc r9,r12,r9
831 andc r10,r12,r10
832
833 mtmsrd r9,1
834 mtspr SPRN_SRR1,r10
835 mtspr SPRN_SRR0,r11
836 rfid
837
838
839/*
840 * kexec_sequence(newstack, start, image, control, clear_all())
841 *
842 * does the grungy work with stack switching and real mode switches
843 * also does simple calls to other code
844 */
845
846_GLOBAL(kexec_sequence)
847 mflr r0
848 std r0,16(r1)
849
850 /* switch stacks to newstack -- &kexec_stack.stack */
851 stdu r1,THREAD_SIZE-112(r3)
852 mr r1,r3
853
854 li r0,0
855 std r0,16(r1)
856
857 /* save regs for local vars on new stack.
858 * yes, we won't go back, but ...
859 */
860 std r31,-8(r1)
861 std r30,-16(r1)
862 std r29,-24(r1)
863 std r28,-32(r1)
864 std r27,-40(r1)
865 std r26,-48(r1)
866 std r25,-56(r1)
867
868 stdu r1,-112-64(r1)
869
870 /* save args into preserved regs */
871 mr r31,r3 /* newstack (both) */
872 mr r30,r4 /* start (real) */
873 mr r29,r5 /* image (virt) */
874 mr r28,r6 /* control, unused */
875 mr r27,r7 /* clear_all() fn desc */
876 mr r26,r8 /* spare */
877 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
878
879 /* disable interrupts, we are overwriting kernel data next */
880 mfmsr r3
881 rlwinm r3,r3,0,17,15
882 mtmsrd r3,1
883
884 /* copy dest pages, flush whole dest image */
885 mr r3,r29
886 bl .kexec_copy_flush /* (image) */
887
888 /* turn off mmu */
889 bl real_mode
890
891 /* clear out hardware hash page table and tlb */
892 ld r5,0(r27) /* deref function descriptor */
893 mtctr r5
894 bctrl /* ppc_md.hash_clear_all(void); */
895
896/*
897 * kexec image calling is:
898 * the first 0x100 bytes of the entry point are copied to 0
899 *
900 * all slaves branch to slave = 0x60 (absolute)
901 * slave(phys_cpu_id);
902 *
903 * master goes to start = entry point
904 * start(phys_cpu_id, start, 0);
905 *
906 *
907 * a wrapper is needed to call existing kernels, here is an approximate
908 * description of one method:
909 *
910 * v2: (2.6.10)
911 * start will be near the boot_block (maybe 0x100 bytes before it?)
912 * it will have a 0x60, which will b to boot_block, where it will wait
913 * and 0 will store phys into struct boot-block and load r3 from there,
914 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
915 *
916 * v1: (2.6.9)
917 * boot block will have all cpus scanning device tree to see if they
918 * are the boot cpu ?????
919 * other device tree differences (prop sizes, va vs pa, etc)...
920 */
921
922 /* copy 0x100 bytes starting at start to 0 */
923 li r3,0
924 mr r4,r30
925 li r5,0x100
926 li r6,0
927 bl .copy_and_flush /* (dest, src, copy limit, start offset) */
9281: /* assume normal blr return */
929
930 /* release other cpus to the new kernel secondary start at 0x60 */
931 mflr r5
932 li r6,1
933 stw r6,kexec_flag-1b(5)
934 mr r3,r25 # my phys cpu
935 mr r4,r30 # start, aka phys mem offset
936 mtlr 4
937 li r5,0
938 blr /* image->start(physid, image->start, 0); */
939#endif /* CONFIG_KEXEC */
Linux kernel - Deliverables
This page took 0.118778 seconds and 5 git commands to generate.