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1da177e4 LT |
1 | /* |
2 | * Port for PPC64 David Engebretsen, IBM Corp. | |
3 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
4 | * | |
5 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * Rework, based on alpha PCI code. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #undef DEBUG | |
15 | ||
16 | #include <linux/config.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/list.h> | |
24 | ||
25 | #include <asm/processor.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/prom.h> | |
28 | #include <asm/pci-bridge.h> | |
29 | #include <asm/byteorder.h> | |
30 | #include <asm/irq.h> | |
31 | #include <asm/machdep.h> | |
32 | #include <asm/udbg.h> | |
33 | ||
34 | #include "pci.h" | |
35 | ||
36 | #ifdef DEBUG | |
37 | #define DBG(fmt...) udbg_printf(fmt) | |
38 | #else | |
39 | #define DBG(fmt...) | |
40 | #endif | |
41 | ||
42 | unsigned long pci_probe_only = 1; | |
43 | unsigned long pci_assign_all_buses = 0; | |
44 | ||
45 | /* | |
46 | * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch | |
47 | * devices we don't have access to. | |
48 | */ | |
49 | unsigned long io_page_mask; | |
50 | ||
51 | EXPORT_SYMBOL(io_page_mask); | |
52 | ||
53 | ||
54 | unsigned int pcibios_assign_all_busses(void) | |
55 | { | |
56 | return pci_assign_all_buses; | |
57 | } | |
58 | ||
59 | /* pci_io_base -- the base address from which io bars are offsets. | |
60 | * This is the lowest I/O base address (so bar values are always positive), | |
61 | * and it *must* be the start of ISA space if an ISA bus exists because | |
62 | * ISA drivers use hard coded offsets. If no ISA bus exists a dummy | |
63 | * page is mapped and isa_io_limit prevents access to it. | |
64 | */ | |
65 | unsigned long isa_io_base; /* NULL if no ISA bus */ | |
66 | EXPORT_SYMBOL(isa_io_base); | |
67 | unsigned long pci_io_base; | |
68 | EXPORT_SYMBOL(pci_io_base); | |
69 | ||
70 | void iSeries_pcibios_init(void); | |
71 | ||
72 | LIST_HEAD(hose_list); | |
73 | ||
74 | struct dma_mapping_ops pci_dma_ops; | |
75 | EXPORT_SYMBOL(pci_dma_ops); | |
76 | ||
77 | int global_phb_number; /* Global phb counter */ | |
78 | ||
79 | /* Cached ISA bridge dev. */ | |
80 | struct pci_dev *ppc64_isabridge_dev = NULL; | |
81 | ||
82 | static void fixup_broken_pcnet32(struct pci_dev* dev) | |
83 | { | |
84 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | |
85 | dev->vendor = PCI_VENDOR_ID_AMD; | |
86 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | |
1da177e4 LT |
87 | } |
88 | } | |
89 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | |
90 | ||
91 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
92 | struct resource *res) | |
93 | { | |
94 | unsigned long offset = 0; | |
95 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
96 | ||
97 | if (!hose) | |
98 | return; | |
99 | ||
100 | if (res->flags & IORESOURCE_IO) | |
101 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
102 | ||
103 | if (res->flags & IORESOURCE_MEM) | |
104 | offset = hose->pci_mem_offset; | |
105 | ||
106 | region->start = res->start - offset; | |
107 | region->end = res->end - offset; | |
108 | } | |
109 | ||
43c34735 DB |
110 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
111 | struct pci_bus_region *region) | |
112 | { | |
113 | unsigned long offset = 0; | |
114 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
115 | ||
116 | if (!hose) | |
117 | return; | |
118 | ||
119 | if (res->flags & IORESOURCE_IO) | |
120 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
121 | ||
122 | if (res->flags & IORESOURCE_MEM) | |
123 | offset = hose->pci_mem_offset; | |
124 | ||
125 | res->start = region->start + offset; | |
126 | res->end = region->end + offset; | |
127 | } | |
128 | ||
1da177e4 LT |
129 | #ifdef CONFIG_HOTPLUG |
130 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
43c34735 | 131 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
132 | #endif |
133 | ||
134 | /* | |
135 | * We need to avoid collisions with `mirrored' VGA ports | |
136 | * and other strange ISA hardware, so we always want the | |
137 | * addresses to be allocated in the 0x000-0x0ff region | |
138 | * modulo 0x400. | |
139 | * | |
140 | * Why? Because some silly external IO cards only decode | |
141 | * the low 10 bits of the IO address. The 0x00-0xff region | |
142 | * is reserved for motherboard devices that decode all 16 | |
143 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
144 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
145 | * which might have be mirrored at 0x0100-0x03ff.. | |
146 | */ | |
147 | void pcibios_align_resource(void *data, struct resource *res, | |
148 | unsigned long size, unsigned long align) | |
149 | { | |
150 | struct pci_dev *dev = data; | |
151 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
152 | unsigned long start = res->start; | |
153 | unsigned long alignto; | |
154 | ||
155 | if (res->flags & IORESOURCE_IO) { | |
156 | unsigned long offset = (unsigned long)hose->io_base_virt - | |
157 | pci_io_base; | |
158 | /* Make sure we start at our min on all hoses */ | |
159 | if (start - offset < PCIBIOS_MIN_IO) | |
160 | start = PCIBIOS_MIN_IO + offset; | |
161 | ||
162 | /* | |
163 | * Put everything into 0x00-0xff region modulo 0x400 | |
164 | */ | |
165 | if (start & 0x300) | |
166 | start = (start + 0x3ff) & ~0x3ff; | |
167 | ||
168 | } else if (res->flags & IORESOURCE_MEM) { | |
169 | /* Make sure we start at our min on all hoses */ | |
170 | if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM) | |
171 | start = PCIBIOS_MIN_MEM + hose->pci_mem_offset; | |
172 | ||
173 | /* Align to multiple of size of minimum base. */ | |
174 | alignto = max(0x1000UL, align); | |
175 | start = ALIGN(start, alignto); | |
176 | } | |
177 | ||
178 | res->start = start; | |
179 | } | |
180 | ||
181 | static DEFINE_SPINLOCK(hose_spinlock); | |
182 | ||
183 | /* | |
184 | * pci_controller(phb) initialized common variables. | |
185 | */ | |
186 | void __devinit pci_setup_pci_controller(struct pci_controller *hose) | |
187 | { | |
188 | memset(hose, 0, sizeof(struct pci_controller)); | |
189 | ||
190 | spin_lock(&hose_spinlock); | |
191 | hose->global_number = global_phb_number++; | |
192 | list_add_tail(&hose->list_node, &hose_list); | |
193 | spin_unlock(&hose_spinlock); | |
194 | } | |
195 | ||
196 | static void __init pcibios_claim_one_bus(struct pci_bus *b) | |
197 | { | |
198 | struct pci_dev *dev; | |
199 | struct pci_bus *child_bus; | |
200 | ||
201 | list_for_each_entry(dev, &b->devices, bus_list) { | |
202 | int i; | |
203 | ||
204 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
205 | struct resource *r = &dev->resource[i]; | |
206 | ||
207 | if (r->parent || !r->start || !r->flags) | |
208 | continue; | |
209 | pci_claim_resource(dev, i); | |
210 | } | |
211 | } | |
212 | ||
213 | list_for_each_entry(child_bus, &b->children, node) | |
214 | pcibios_claim_one_bus(child_bus); | |
215 | } | |
216 | ||
217 | #ifndef CONFIG_PPC_ISERIES | |
218 | static void __init pcibios_claim_of_setup(void) | |
219 | { | |
220 | struct pci_bus *b; | |
221 | ||
222 | list_for_each_entry(b, &pci_root_buses, node) | |
223 | pcibios_claim_one_bus(b); | |
224 | } | |
225 | #endif | |
226 | ||
227 | static int __init pcibios_init(void) | |
228 | { | |
229 | struct pci_controller *hose, *tmp; | |
230 | struct pci_bus *bus; | |
231 | ||
232 | /* For now, override phys_mem_access_prot. If we need it, | |
233 | * later, we may move that initialization to each ppc_md | |
234 | */ | |
235 | ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; | |
236 | ||
237 | #ifdef CONFIG_PPC_ISERIES | |
238 | iSeries_pcibios_init(); | |
239 | #endif | |
240 | ||
241 | printk("PCI: Probing PCI hardware\n"); | |
242 | ||
243 | /* Scan all of the recorded PCI controllers. */ | |
244 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
245 | hose->last_busno = 0xff; | |
246 | bus = pci_scan_bus(hose->first_busno, hose->ops, | |
247 | hose->arch_data); | |
248 | hose->bus = bus; | |
249 | hose->last_busno = bus->subordinate; | |
250 | } | |
251 | ||
252 | #ifndef CONFIG_PPC_ISERIES | |
253 | if (pci_probe_only) | |
254 | pcibios_claim_of_setup(); | |
255 | else | |
256 | /* FIXME: `else' will be removed when | |
257 | pci_assign_unassigned_resources() is able to work | |
258 | correctly with [partially] allocated PCI tree. */ | |
259 | pci_assign_unassigned_resources(); | |
260 | #endif /* !CONFIG_PPC_ISERIES */ | |
261 | ||
262 | /* Call machine dependent final fixup */ | |
263 | if (ppc_md.pcibios_fixup) | |
264 | ppc_md.pcibios_fixup(); | |
265 | ||
266 | /* Cache the location of the ISA bridge (if we have one) */ | |
267 | ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
268 | if (ppc64_isabridge_dev != NULL) | |
269 | printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev)); | |
270 | ||
271 | printk("PCI: Probing PCI hardware done\n"); | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
276 | subsys_initcall(pcibios_init); | |
277 | ||
278 | char __init *pcibios_setup(char *str) | |
279 | { | |
280 | return str; | |
281 | } | |
282 | ||
283 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
284 | { | |
285 | u16 cmd, oldcmd; | |
286 | int i; | |
287 | ||
288 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
289 | oldcmd = cmd; | |
290 | ||
291 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
292 | struct resource *res = &dev->resource[i]; | |
293 | ||
294 | /* Only set up the requested stuff */ | |
295 | if (!(mask & (1<<i))) | |
296 | continue; | |
297 | ||
298 | if (res->flags & IORESOURCE_IO) | |
299 | cmd |= PCI_COMMAND_IO; | |
300 | if (res->flags & IORESOURCE_MEM) | |
301 | cmd |= PCI_COMMAND_MEMORY; | |
302 | } | |
303 | ||
304 | if (cmd != oldcmd) { | |
305 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
306 | pci_name(dev), cmd); | |
307 | /* Enable the appropriate bits in the PCI command register. */ | |
308 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
309 | } | |
310 | return 0; | |
311 | } | |
312 | ||
313 | /* | |
314 | * Return the domain number for this bus. | |
315 | */ | |
316 | int pci_domain_nr(struct pci_bus *bus) | |
317 | { | |
318 | #ifdef CONFIG_PPC_ISERIES | |
319 | return 0; | |
320 | #else | |
321 | struct pci_controller *hose = pci_bus_to_host(bus); | |
322 | ||
323 | return hose->global_number; | |
324 | #endif | |
325 | } | |
326 | ||
327 | EXPORT_SYMBOL(pci_domain_nr); | |
328 | ||
329 | /* Decide whether to display the domain number in /proc */ | |
330 | int pci_proc_domain(struct pci_bus *bus) | |
331 | { | |
332 | #ifdef CONFIG_PPC_ISERIES | |
333 | return 0; | |
334 | #else | |
335 | struct pci_controller *hose = pci_bus_to_host(bus); | |
336 | return hose->buid; | |
337 | #endif | |
338 | } | |
339 | ||
340 | /* | |
341 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
342 | * modelled on the sparc64 implementation by Dave Miller. | |
343 | * -- paulus. | |
344 | */ | |
345 | ||
346 | /* | |
347 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
348 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
349 | * | |
350 | * Basically, the user finds the base address for his device which he wishes | |
351 | * to mmap. They read the 32-bit value from the config space base register, | |
352 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
353 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
354 | * | |
355 | * Returns negative error code on failure, zero on success. | |
356 | */ | |
357 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
358 | unsigned long *offset, | |
359 | enum pci_mmap_state mmap_state) | |
360 | { | |
361 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
362 | unsigned long io_offset = 0; | |
363 | int i, res_bit; | |
364 | ||
365 | if (hose == 0) | |
366 | return NULL; /* should never happen */ | |
367 | ||
368 | /* If memory, add on the PCI bridge address offset */ | |
369 | if (mmap_state == pci_mmap_mem) { | |
370 | *offset += hose->pci_mem_offset; | |
371 | res_bit = IORESOURCE_MEM; | |
372 | } else { | |
2311b1f2 | 373 | io_offset = (unsigned long)hose->io_base_virt - pci_io_base; |
1da177e4 LT |
374 | *offset += io_offset; |
375 | res_bit = IORESOURCE_IO; | |
376 | } | |
377 | ||
378 | /* | |
379 | * Check that the offset requested corresponds to one of the | |
380 | * resources of the device. | |
381 | */ | |
382 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
383 | struct resource *rp = &dev->resource[i]; | |
384 | int flags = rp->flags; | |
385 | ||
386 | /* treat ROM as memory (should be already) */ | |
387 | if (i == PCI_ROM_RESOURCE) | |
388 | flags |= IORESOURCE_MEM; | |
389 | ||
390 | /* Active and same type? */ | |
391 | if ((flags & res_bit) == 0) | |
392 | continue; | |
393 | ||
394 | /* In the range of this resource? */ | |
395 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
396 | continue; | |
397 | ||
398 | /* found it! construct the final physical address */ | |
399 | if (mmap_state == pci_mmap_io) | |
2311b1f2 | 400 | *offset += hose->io_base_phys - io_offset; |
1da177e4 LT |
401 | return rp; |
402 | } | |
403 | ||
404 | return NULL; | |
405 | } | |
406 | ||
407 | /* | |
408 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
409 | * device mapping. | |
410 | */ | |
411 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
412 | pgprot_t protection, | |
413 | enum pci_mmap_state mmap_state, | |
414 | int write_combine) | |
415 | { | |
416 | unsigned long prot = pgprot_val(protection); | |
417 | ||
418 | /* Write combine is always 0 on non-memory space mappings. On | |
419 | * memory space, if the user didn't pass 1, we check for a | |
420 | * "prefetchable" resource. This is a bit hackish, but we use | |
421 | * this to workaround the inability of /sysfs to provide a write | |
422 | * combine bit | |
423 | */ | |
424 | if (mmap_state != pci_mmap_mem) | |
425 | write_combine = 0; | |
426 | else if (write_combine == 0) { | |
427 | if (rp->flags & IORESOURCE_PREFETCH) | |
428 | write_combine = 1; | |
429 | } | |
430 | ||
431 | /* XXX would be nice to have a way to ask for write-through */ | |
432 | prot |= _PAGE_NO_CACHE; | |
433 | if (write_combine) | |
434 | prot &= ~_PAGE_GUARDED; | |
435 | else | |
436 | prot |= _PAGE_GUARDED; | |
437 | ||
438 | printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start, | |
439 | prot); | |
440 | ||
441 | return __pgprot(prot); | |
442 | } | |
443 | ||
444 | /* | |
445 | * This one is used by /dev/mem and fbdev who have no clue about the | |
446 | * PCI device, it tries to find the PCI device first and calls the | |
447 | * above routine | |
448 | */ | |
449 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
450 | unsigned long offset, | |
451 | unsigned long size, | |
452 | pgprot_t protection) | |
453 | { | |
454 | struct pci_dev *pdev = NULL; | |
455 | struct resource *found = NULL; | |
456 | unsigned long prot = pgprot_val(protection); | |
457 | int i; | |
458 | ||
459 | if (page_is_ram(offset >> PAGE_SHIFT)) | |
1f8d419e | 460 | return __pgprot(prot); |
1da177e4 LT |
461 | |
462 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; | |
463 | ||
464 | for_each_pci_dev(pdev) { | |
465 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
466 | struct resource *rp = &pdev->resource[i]; | |
467 | int flags = rp->flags; | |
468 | ||
469 | /* Active and same type? */ | |
470 | if ((flags & IORESOURCE_MEM) == 0) | |
471 | continue; | |
472 | /* In the range of this resource? */ | |
473 | if (offset < (rp->start & PAGE_MASK) || | |
474 | offset > rp->end) | |
475 | continue; | |
476 | found = rp; | |
477 | break; | |
478 | } | |
479 | if (found) | |
480 | break; | |
481 | } | |
482 | if (found) { | |
483 | if (found->flags & IORESOURCE_PREFETCH) | |
484 | prot &= ~_PAGE_GUARDED; | |
485 | pci_dev_put(pdev); | |
486 | } | |
487 | ||
488 | DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); | |
489 | ||
490 | return __pgprot(prot); | |
491 | } | |
492 | ||
493 | ||
494 | /* | |
495 | * Perform the actual remap of the pages for a PCI device mapping, as | |
496 | * appropriate for this architecture. The region in the process to map | |
497 | * is described by vm_start and vm_end members of VMA, the base physical | |
498 | * address is found in vm_pgoff. | |
499 | * The pci device structure is provided so that architectures may make mapping | |
500 | * decisions on a per-device or per-bus basis. | |
501 | * | |
502 | * Returns a negative error code on failure, zero on success. | |
503 | */ | |
504 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
505 | enum pci_mmap_state mmap_state, | |
506 | int write_combine) | |
507 | { | |
508 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; | |
509 | struct resource *rp; | |
510 | int ret; | |
511 | ||
512 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
513 | if (rp == NULL) | |
514 | return -EINVAL; | |
515 | ||
516 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
517 | vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO; | |
518 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
519 | vma->vm_page_prot, | |
520 | mmap_state, write_combine); | |
521 | ||
522 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
523 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
524 | ||
525 | return ret; | |
526 | } | |
527 | ||
528 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
ff381d22 | 529 | static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf) |
1da177e4 LT |
530 | { |
531 | struct pci_dev *pdev; | |
532 | struct device_node *np; | |
533 | ||
534 | pdev = to_pci_dev (dev); | |
535 | np = pci_device_to_OF_node(pdev); | |
536 | if (np == NULL || np->full_name == NULL) | |
537 | return 0; | |
538 | return sprintf(buf, "%s", np->full_name); | |
539 | } | |
540 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
541 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
542 | ||
543 | void pcibios_add_platform_entries(struct pci_dev *pdev) | |
544 | { | |
545 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
546 | device_create_file(&pdev->dev, &dev_attr_devspec); | |
547 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
548 | } | |
549 | ||
550 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
551 | ||
552 | #define ISA_SPACE_MASK 0x1 | |
553 | #define ISA_SPACE_IO 0x1 | |
554 | ||
555 | static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node, | |
556 | unsigned long phb_io_base_phys, | |
557 | void __iomem * phb_io_base_virt) | |
558 | { | |
559 | struct isa_range *range; | |
560 | unsigned long pci_addr; | |
561 | unsigned int isa_addr; | |
562 | unsigned int size; | |
563 | int rlen = 0; | |
564 | ||
565 | range = (struct isa_range *) get_property(isa_node, "ranges", &rlen); | |
566 | if (range == NULL || (rlen < sizeof(struct isa_range))) { | |
567 | printk(KERN_ERR "no ISA ranges or unexpected isa range size," | |
568 | "mapping 64k\n"); | |
dfbacdc1 BH |
569 | __ioremap_explicit(phb_io_base_phys, |
570 | (unsigned long)phb_io_base_virt, | |
571 | 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED); | |
1da177e4 LT |
572 | return; |
573 | } | |
574 | ||
575 | /* From "ISA Binding to 1275" | |
576 | * The ranges property is laid out as an array of elements, | |
577 | * each of which comprises: | |
578 | * cells 0 - 1: an ISA address | |
579 | * cells 2 - 4: a PCI address | |
580 | * (size depending on dev->n_addr_cells) | |
581 | * cell 5: the size of the range | |
582 | */ | |
583 | if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) { | |
584 | isa_addr = range->isa_addr.a_lo; | |
585 | pci_addr = (unsigned long) range->pci_addr.a_mid << 32 | | |
586 | range->pci_addr.a_lo; | |
587 | ||
588 | /* Assume these are both zero */ | |
589 | if ((pci_addr != 0) || (isa_addr != 0)) { | |
590 | printk(KERN_ERR "unexpected isa to pci mapping: %s\n", | |
591 | __FUNCTION__); | |
592 | return; | |
593 | } | |
594 | ||
595 | size = PAGE_ALIGN(range->size); | |
596 | ||
597 | __ioremap_explicit(phb_io_base_phys, | |
598 | (unsigned long) phb_io_base_virt, | |
dfbacdc1 | 599 | size, _PAGE_NO_CACHE | _PAGE_GUARDED); |
1da177e4 LT |
600 | } |
601 | } | |
602 | ||
603 | void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
604 | struct device_node *dev) | |
605 | { | |
606 | unsigned int *ranges; | |
607 | unsigned long size; | |
608 | int rlen = 0; | |
609 | int memno = 0; | |
610 | struct resource *res; | |
611 | int np, na = prom_n_addr_cells(dev); | |
612 | unsigned long pci_addr, cpu_phys_addr; | |
613 | ||
614 | np = na + 5; | |
615 | ||
616 | /* From "PCI Binding to 1275" | |
617 | * The ranges property is laid out as an array of elements, | |
618 | * each of which comprises: | |
619 | * cells 0 - 2: a PCI address | |
620 | * cells 3 or 3+4: a CPU physical address | |
621 | * (size depending on dev->n_addr_cells) | |
622 | * cells 4+5 or 5+6: the size of the range | |
623 | */ | |
624 | rlen = 0; | |
625 | hose->io_base_phys = 0; | |
626 | ranges = (unsigned int *) get_property(dev, "ranges", &rlen); | |
627 | while ((rlen -= np * sizeof(unsigned int)) >= 0) { | |
628 | res = NULL; | |
629 | pci_addr = (unsigned long)ranges[1] << 32 | ranges[2]; | |
630 | ||
631 | cpu_phys_addr = ranges[3]; | |
632 | if (na == 2) | |
633 | cpu_phys_addr = cpu_phys_addr << 32 | ranges[4]; | |
634 | ||
635 | size = (unsigned long)ranges[na+3] << 32 | ranges[na+4]; | |
636 | if (size == 0) | |
637 | continue; | |
638 | switch ((ranges[0] >> 24) & 0x3) { | |
639 | case 1: /* I/O space */ | |
640 | hose->io_base_phys = cpu_phys_addr; | |
641 | hose->pci_io_size = size; | |
642 | ||
643 | res = &hose->io_resource; | |
644 | res->flags = IORESOURCE_IO; | |
645 | res->start = pci_addr; | |
646 | DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number, | |
647 | res->start, res->start + size - 1); | |
648 | break; | |
649 | case 2: /* memory space */ | |
650 | memno = 0; | |
651 | while (memno < 3 && hose->mem_resources[memno].flags) | |
652 | ++memno; | |
653 | ||
654 | if (memno == 0) | |
655 | hose->pci_mem_offset = cpu_phys_addr - pci_addr; | |
656 | if (memno < 3) { | |
657 | res = &hose->mem_resources[memno]; | |
658 | res->flags = IORESOURCE_MEM; | |
659 | res->start = cpu_phys_addr; | |
660 | DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number, | |
661 | res->start, res->start + size - 1); | |
662 | } | |
663 | break; | |
664 | } | |
665 | if (res != NULL) { | |
666 | res->name = dev->full_name; | |
667 | res->end = res->start + size - 1; | |
668 | res->parent = NULL; | |
669 | res->sibling = NULL; | |
670 | res->child = NULL; | |
671 | } | |
672 | ranges += np; | |
673 | } | |
674 | } | |
675 | ||
676 | void __init pci_setup_phb_io(struct pci_controller *hose, int primary) | |
677 | { | |
678 | unsigned long size = hose->pci_io_size; | |
679 | unsigned long io_virt_offset; | |
680 | struct resource *res; | |
681 | struct device_node *isa_dn; | |
682 | ||
683 | hose->io_base_virt = reserve_phb_iospace(size); | |
684 | DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", | |
685 | hose->global_number, hose->io_base_phys, | |
686 | (unsigned long) hose->io_base_virt); | |
687 | ||
688 | if (primary) { | |
689 | pci_io_base = (unsigned long)hose->io_base_virt; | |
690 | isa_dn = of_find_node_by_type(NULL, "isa"); | |
691 | if (isa_dn) { | |
692 | isa_io_base = pci_io_base; | |
693 | pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys, | |
694 | hose->io_base_virt); | |
695 | of_node_put(isa_dn); | |
696 | /* Allow all IO */ | |
697 | io_page_mask = -1; | |
698 | } | |
699 | } | |
700 | ||
701 | io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
702 | res = &hose->io_resource; | |
703 | res->start += io_virt_offset; | |
704 | res->end += io_virt_offset; | |
705 | } | |
706 | ||
707 | void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose, | |
708 | int primary) | |
709 | { | |
710 | unsigned long size = hose->pci_io_size; | |
711 | unsigned long io_virt_offset; | |
712 | struct resource *res; | |
713 | ||
714 | hose->io_base_virt = __ioremap(hose->io_base_phys, size, | |
dfbacdc1 | 715 | _PAGE_NO_CACHE | _PAGE_GUARDED); |
1da177e4 LT |
716 | DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", |
717 | hose->global_number, hose->io_base_phys, | |
718 | (unsigned long) hose->io_base_virt); | |
719 | ||
720 | if (primary) | |
721 | pci_io_base = (unsigned long)hose->io_base_virt; | |
722 | ||
723 | io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
724 | res = &hose->io_resource; | |
725 | res->start += io_virt_offset; | |
726 | res->end += io_virt_offset; | |
727 | } | |
728 | ||
729 | ||
730 | static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys, | |
731 | unsigned long *start_virt, unsigned long *size) | |
732 | { | |
733 | struct pci_controller *hose = pci_bus_to_host(bus); | |
734 | struct pci_bus_region region; | |
735 | struct resource *res; | |
736 | ||
737 | if (bus->self) { | |
738 | res = bus->resource[0]; | |
739 | pcibios_resource_to_bus(bus->self, ®ion, res); | |
740 | *start_phys = hose->io_base_phys + region.start; | |
741 | *start_virt = (unsigned long) hose->io_base_virt + | |
742 | region.start; | |
743 | if (region.end > region.start) | |
744 | *size = region.end - region.start + 1; | |
745 | else { | |
746 | printk("%s(): unexpected region 0x%lx->0x%lx\n", | |
747 | __FUNCTION__, region.start, region.end); | |
748 | return 1; | |
749 | } | |
750 | ||
751 | } else { | |
752 | /* Root Bus */ | |
753 | res = &hose->io_resource; | |
754 | *start_phys = hose->io_base_phys; | |
755 | *start_virt = (unsigned long) hose->io_base_virt; | |
756 | if (res->end > res->start) | |
757 | *size = res->end - res->start + 1; | |
758 | else { | |
759 | printk("%s(): unexpected region 0x%lx->0x%lx\n", | |
760 | __FUNCTION__, res->start, res->end); | |
761 | return 1; | |
762 | } | |
763 | } | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | int unmap_bus_range(struct pci_bus *bus) | |
769 | { | |
770 | unsigned long start_phys; | |
771 | unsigned long start_virt; | |
772 | unsigned long size; | |
773 | ||
774 | if (!bus) { | |
775 | printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); | |
776 | return 1; | |
777 | } | |
778 | ||
779 | if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) | |
780 | return 1; | |
781 | if (iounmap_explicit((void __iomem *) start_virt, size)) | |
782 | return 1; | |
783 | ||
784 | return 0; | |
785 | } | |
786 | EXPORT_SYMBOL(unmap_bus_range); | |
787 | ||
788 | int remap_bus_range(struct pci_bus *bus) | |
789 | { | |
790 | unsigned long start_phys; | |
791 | unsigned long start_virt; | |
792 | unsigned long size; | |
793 | ||
794 | if (!bus) { | |
795 | printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); | |
796 | return 1; | |
797 | } | |
798 | ||
799 | ||
800 | if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) | |
801 | return 1; | |
802 | printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size); | |
dfbacdc1 BH |
803 | if (__ioremap_explicit(start_phys, start_virt, size, |
804 | _PAGE_NO_CACHE | _PAGE_GUARDED)) | |
1da177e4 LT |
805 | return 1; |
806 | ||
807 | return 0; | |
808 | } | |
809 | EXPORT_SYMBOL(remap_bus_range); | |
810 | ||
811 | void phbs_remap_io(void) | |
812 | { | |
813 | struct pci_controller *hose, *tmp; | |
814 | ||
815 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
816 | remap_bus_range(hose->bus); | |
817 | } | |
818 | ||
819 | /* | |
820 | * ppc64 can have multifunction devices that do not respond to function 0. | |
821 | * In this case we must scan all functions. | |
822 | */ | |
823 | int pcibios_scan_all_fns(struct pci_bus *bus, int devfn) | |
824 | { | |
825 | struct device_node *busdn, *dn; | |
826 | ||
827 | if (bus->self) | |
828 | busdn = pci_device_to_OF_node(bus->self); | |
829 | else | |
830 | busdn = bus->sysdata; /* must be a phb */ | |
831 | ||
832 | if (busdn == NULL) | |
833 | return 0; | |
834 | ||
835 | /* | |
836 | * Check to see if there is any of the 8 functions are in the | |
837 | * device tree. If they are then we need to scan all the | |
838 | * functions of this slot. | |
839 | */ | |
1635317f PM |
840 | for (dn = busdn->child; dn; dn = dn->sibling) { |
841 | struct pci_dn *pdn = dn->data; | |
842 | if (pdn && (pdn->devfn >> 3) == (devfn >> 3)) | |
1da177e4 | 843 | return 1; |
1635317f | 844 | } |
1da177e4 LT |
845 | |
846 | return 0; | |
847 | } | |
848 | ||
849 | ||
850 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, | |
851 | struct pci_bus *bus) | |
852 | { | |
853 | /* Update device resources. */ | |
854 | struct pci_controller *hose = pci_bus_to_host(bus); | |
855 | int i; | |
856 | ||
857 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
858 | if (dev->resource[i].flags & IORESOURCE_IO) { | |
859 | unsigned long offset = (unsigned long)hose->io_base_virt | |
860 | - pci_io_base; | |
861 | unsigned long start, end, mask; | |
862 | ||
863 | start = dev->resource[i].start += offset; | |
864 | end = dev->resource[i].end += offset; | |
865 | ||
866 | /* Need to allow IO access to pages that are in the | |
867 | ISA range */ | |
868 | if (start < MAX_ISA_PORT) { | |
869 | if (end > MAX_ISA_PORT) | |
870 | end = MAX_ISA_PORT; | |
871 | ||
872 | start >>= PAGE_SHIFT; | |
873 | end >>= PAGE_SHIFT; | |
874 | ||
875 | /* get the range of pages for the map */ | |
876 | mask = ((1 << (end+1))-1) ^ ((1 << start)-1); | |
877 | io_page_mask |= mask; | |
878 | } | |
879 | } | |
880 | else if (dev->resource[i].flags & IORESOURCE_MEM) { | |
881 | dev->resource[i].start += hose->pci_mem_offset; | |
882 | dev->resource[i].end += hose->pci_mem_offset; | |
883 | } | |
884 | } | |
885 | } | |
886 | EXPORT_SYMBOL(pcibios_fixup_device_resources); | |
887 | ||
888 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) | |
889 | { | |
890 | struct pci_controller *hose = pci_bus_to_host(bus); | |
891 | struct pci_dev *dev = bus->self; | |
892 | struct resource *res; | |
893 | int i; | |
894 | ||
895 | if (!dev) { | |
896 | /* Root bus. */ | |
897 | ||
898 | hose->bus = bus; | |
899 | bus->resource[0] = res = &hose->io_resource; | |
900 | ||
901 | if (res->flags && request_resource(&ioport_resource, res)) | |
902 | printk(KERN_ERR "Failed to request IO on " | |
903 | "PCI domain %d\n", pci_domain_nr(bus)); | |
904 | ||
905 | for (i = 0; i < 3; ++i) { | |
906 | res = &hose->mem_resources[i]; | |
907 | bus->resource[i+1] = res; | |
908 | if (res->flags && request_resource(&iomem_resource, res)) | |
909 | printk(KERN_ERR "Failed to request MEM on " | |
910 | "PCI domain %d\n", | |
911 | pci_domain_nr(bus)); | |
912 | } | |
913 | } else if (pci_probe_only && | |
914 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
915 | /* This is a subordinate bridge */ | |
916 | ||
917 | pci_read_bridge_bases(bus); | |
918 | pcibios_fixup_device_resources(dev, bus); | |
919 | } | |
920 | ||
921 | ppc_md.iommu_bus_setup(bus); | |
922 | ||
923 | list_for_each_entry(dev, &bus->devices, bus_list) | |
924 | ppc_md.iommu_dev_setup(dev); | |
925 | ||
dad32bbf JR |
926 | if (ppc_md.irq_bus_setup) |
927 | ppc_md.irq_bus_setup(bus); | |
928 | ||
1da177e4 LT |
929 | if (!pci_probe_only) |
930 | return; | |
931 | ||
932 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
933 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
934 | pcibios_fixup_device_resources(dev, bus); | |
935 | } | |
936 | } | |
937 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
938 | ||
939 | /* | |
940 | * Reads the interrupt pin to determine if interrupt is use by card. | |
941 | * If the interrupt is used, then gets the interrupt line from the | |
942 | * openfirmware and sets it in the pci_dev and pci_config line. | |
943 | */ | |
944 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
945 | { | |
946 | u8 intpin; | |
947 | struct device_node *node; | |
948 | ||
949 | pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin); | |
950 | if (intpin == 0) | |
951 | return 0; | |
952 | ||
953 | node = pci_device_to_OF_node(pci_dev); | |
954 | if (node == NULL) | |
955 | return -1; | |
956 | ||
957 | if (node->n_intrs == 0) | |
958 | return -1; | |
959 | ||
960 | pci_dev->irq = node->intrs[0].line; | |
961 | ||
962 | pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq); | |
963 | ||
964 | return 0; | |
965 | } | |
966 | EXPORT_SYMBOL(pci_read_irq_line); | |
967 | ||
2311b1f2 ME |
968 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
969 | const struct resource *rsrc, | |
970 | u64 *start, u64 *end) | |
971 | { | |
972 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
973 | unsigned long offset = 0; | |
974 | ||
975 | if (hose == NULL) | |
976 | return; | |
977 | ||
978 | if (rsrc->flags & IORESOURCE_IO) | |
979 | offset = pci_io_base - (unsigned long)hose->io_base_virt + | |
980 | hose->io_base_phys; | |
981 | ||
982 | *start = rsrc->start + offset; | |
983 | *end = rsrc->end + offset; | |
984 | } | |
985 | ||
1da177e4 | 986 | #endif /* CONFIG_PPC_MULTIPLATFORM */ |