Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999 |
1da177e4 LT |
4 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com) |
5 | * | |
6 | * Derived from "include/asm-i386/bitops.h" | |
7 | * Copyright (C) 1992, Linus Torvalds | |
8 | * | |
9 | */ | |
c406abd3 | 10 | |
a53c8fab HC |
11 | #ifndef _S390_BITOPS_H |
12 | #define _S390_BITOPS_H | |
13 | ||
0624517d JS |
14 | #ifndef _LINUX_BITOPS_H |
15 | #error only <linux/bitops.h> can be included directly | |
16 | #endif | |
17 | ||
1da177e4 LT |
18 | #include <linux/compiler.h> |
19 | ||
20 | /* | |
21 | * 32 bit bitops format: | |
22 | * bit 0 is the LSB of *addr; bit 31 is the MSB of *addr; | |
23 | * bit 32 is the LSB of *(addr+4). That combined with the | |
24 | * big endian byte order on S390 give the following bit | |
25 | * order in memory: | |
26 | * 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 \ | |
27 | * 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 | |
28 | * after that follows the next long with bit numbers | |
29 | * 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 | |
30 | * 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 | |
31 | * The reason for this bit ordering is the fact that | |
32 | * in the architecture independent code bits operations | |
33 | * of the form "flags |= (1 << bitnr)" are used INTERMIXED | |
34 | * with operation of the form "set_bit(bitnr, flags)". | |
35 | * | |
36 | * 64 bit bitops format: | |
37 | * bit 0 is the LSB of *addr; bit 63 is the MSB of *addr; | |
38 | * bit 64 is the LSB of *(addr+8). That combined with the | |
39 | * big endian byte order on S390 give the following bit | |
40 | * order in memory: | |
41 | * 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30 | |
42 | * 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20 | |
43 | * 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 | |
44 | * 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 | |
45 | * after that follows the next long with bit numbers | |
46 | * 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70 | |
47 | * 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60 | |
48 | * 5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50 | |
49 | * 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40 | |
50 | * The reason for this bit ordering is the fact that | |
51 | * in the architecture independent code bits operations | |
52 | * of the form "flags |= (1 << bitnr)" are used INTERMIXED | |
53 | * with operation of the form "set_bit(bitnr, flags)". | |
54 | */ | |
55 | ||
e3dd9c2d | 56 | /* bitmap tables from arch/s390/kernel/bitmap.c */ |
1da177e4 LT |
57 | extern const char _oi_bitmap[]; |
58 | extern const char _ni_bitmap[]; | |
59 | extern const char _zb_findmap[]; | |
60 | extern const char _sb_findmap[]; | |
61 | ||
f4815ac6 | 62 | #ifndef CONFIG_64BIT |
1da177e4 | 63 | |
1da177e4 LT |
64 | #define __BITOPS_OR "or" |
65 | #define __BITOPS_AND "nr" | |
66 | #define __BITOPS_XOR "xr" | |
67 | ||
94c12cc7 MS |
68 | #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \ |
69 | asm volatile( \ | |
70 | " l %0,%2\n" \ | |
71 | "0: lr %1,%0\n" \ | |
72 | __op_string " %1,%3\n" \ | |
73 | " cs %0,%1,%2\n" \ | |
74 | " jl 0b" \ | |
75 | : "=&d" (__old), "=&d" (__new), \ | |
76 | "=Q" (*(unsigned long *) __addr) \ | |
77 | : "d" (__val), "Q" (*(unsigned long *) __addr) \ | |
78 | : "cc"); | |
79 | ||
f4815ac6 | 80 | #else /* CONFIG_64BIT */ |
1da177e4 | 81 | |
1da177e4 LT |
82 | #define __BITOPS_OR "ogr" |
83 | #define __BITOPS_AND "ngr" | |
84 | #define __BITOPS_XOR "xgr" | |
85 | ||
94c12cc7 MS |
86 | #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \ |
87 | asm volatile( \ | |
88 | " lg %0,%2\n" \ | |
89 | "0: lgr %1,%0\n" \ | |
90 | __op_string " %1,%3\n" \ | |
91 | " csg %0,%1,%2\n" \ | |
92 | " jl 0b" \ | |
93 | : "=&d" (__old), "=&d" (__new), \ | |
94 | "=Q" (*(unsigned long *) __addr) \ | |
95 | : "d" (__val), "Q" (*(unsigned long *) __addr) \ | |
96 | : "cc"); | |
97 | ||
f4815ac6 | 98 | #endif /* CONFIG_64BIT */ |
1da177e4 | 99 | |
01c2475f | 100 | #define __BITOPS_WORDS(bits) (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG) |
94c12cc7 | 101 | #define __BITOPS_BARRIER() asm volatile("" : : : "memory") |
1da177e4 LT |
102 | |
103 | #ifdef CONFIG_SMP | |
104 | /* | |
105 | * SMP safe set_bit routine based on compare and swap (CS) | |
106 | */ | |
107 | static inline void set_bit_cs(unsigned long nr, volatile unsigned long *ptr) | |
108 | { | |
109 | unsigned long addr, old, new, mask; | |
110 | ||
111 | addr = (unsigned long) ptr; | |
1da177e4 | 112 | /* calculate address for CS */ |
01c2475f | 113 | addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3; |
1da177e4 | 114 | /* make OR mask */ |
01c2475f | 115 | mask = 1UL << (nr & (BITS_PER_LONG - 1)); |
1da177e4 LT |
116 | /* Do the atomic update. */ |
117 | __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR); | |
118 | } | |
119 | ||
120 | /* | |
121 | * SMP safe clear_bit routine based on compare and swap (CS) | |
122 | */ | |
123 | static inline void clear_bit_cs(unsigned long nr, volatile unsigned long *ptr) | |
124 | { | |
125 | unsigned long addr, old, new, mask; | |
126 | ||
127 | addr = (unsigned long) ptr; | |
1da177e4 | 128 | /* calculate address for CS */ |
01c2475f | 129 | addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3; |
1da177e4 | 130 | /* make AND mask */ |
01c2475f | 131 | mask = ~(1UL << (nr & (BITS_PER_LONG - 1))); |
1da177e4 LT |
132 | /* Do the atomic update. */ |
133 | __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND); | |
134 | } | |
135 | ||
136 | /* | |
137 | * SMP safe change_bit routine based on compare and swap (CS) | |
138 | */ | |
139 | static inline void change_bit_cs(unsigned long nr, volatile unsigned long *ptr) | |
140 | { | |
141 | unsigned long addr, old, new, mask; | |
142 | ||
143 | addr = (unsigned long) ptr; | |
1da177e4 | 144 | /* calculate address for CS */ |
01c2475f | 145 | addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3; |
1da177e4 | 146 | /* make XOR mask */ |
01c2475f | 147 | mask = 1UL << (nr & (BITS_PER_LONG - 1)); |
1da177e4 LT |
148 | /* Do the atomic update. */ |
149 | __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR); | |
150 | } | |
151 | ||
152 | /* | |
153 | * SMP safe test_and_set_bit routine based on compare and swap (CS) | |
154 | */ | |
155 | static inline int | |
156 | test_and_set_bit_cs(unsigned long nr, volatile unsigned long *ptr) | |
157 | { | |
158 | unsigned long addr, old, new, mask; | |
159 | ||
160 | addr = (unsigned long) ptr; | |
1da177e4 | 161 | /* calculate address for CS */ |
01c2475f | 162 | addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3; |
1da177e4 | 163 | /* make OR/test mask */ |
01c2475f | 164 | mask = 1UL << (nr & (BITS_PER_LONG - 1)); |
1da177e4 LT |
165 | /* Do the atomic update. */ |
166 | __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR); | |
167 | __BITOPS_BARRIER(); | |
168 | return (old & mask) != 0; | |
169 | } | |
170 | ||
171 | /* | |
172 | * SMP safe test_and_clear_bit routine based on compare and swap (CS) | |
173 | */ | |
174 | static inline int | |
175 | test_and_clear_bit_cs(unsigned long nr, volatile unsigned long *ptr) | |
176 | { | |
177 | unsigned long addr, old, new, mask; | |
178 | ||
179 | addr = (unsigned long) ptr; | |
1da177e4 | 180 | /* calculate address for CS */ |
01c2475f | 181 | addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3; |
1da177e4 | 182 | /* make AND/test mask */ |
01c2475f | 183 | mask = ~(1UL << (nr & (BITS_PER_LONG - 1))); |
1da177e4 LT |
184 | /* Do the atomic update. */ |
185 | __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND); | |
186 | __BITOPS_BARRIER(); | |
187 | return (old ^ new) != 0; | |
188 | } | |
189 | ||
190 | /* | |
191 | * SMP safe test_and_change_bit routine based on compare and swap (CS) | |
192 | */ | |
193 | static inline int | |
194 | test_and_change_bit_cs(unsigned long nr, volatile unsigned long *ptr) | |
195 | { | |
196 | unsigned long addr, old, new, mask; | |
197 | ||
198 | addr = (unsigned long) ptr; | |
1da177e4 | 199 | /* calculate address for CS */ |
01c2475f | 200 | addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3; |
1da177e4 | 201 | /* make XOR/test mask */ |
01c2475f | 202 | mask = 1UL << (nr & (BITS_PER_LONG - 1)); |
1da177e4 LT |
203 | /* Do the atomic update. */ |
204 | __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR); | |
205 | __BITOPS_BARRIER(); | |
206 | return (old & mask) != 0; | |
207 | } | |
208 | #endif /* CONFIG_SMP */ | |
209 | ||
210 | /* | |
211 | * fast, non-SMP set_bit routine | |
212 | */ | |
213 | static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr) | |
214 | { | |
215 | unsigned long addr; | |
216 | ||
01c2475f | 217 | addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
94c12cc7 | 218 | asm volatile( |
987bcdac MS |
219 | " oc %O0(1,%R0),%1" |
220 | : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" ); | |
1da177e4 LT |
221 | } |
222 | ||
223 | static inline void | |
224 | __constant_set_bit(const unsigned long nr, volatile unsigned long *ptr) | |
225 | { | |
226 | unsigned long addr; | |
227 | ||
01c2475f | 228 | addr = ((unsigned long) ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
94c12cc7 | 229 | *(unsigned char *) addr |= 1 << (nr & 7); |
1da177e4 LT |
230 | } |
231 | ||
232 | #define set_bit_simple(nr,addr) \ | |
233 | (__builtin_constant_p((nr)) ? \ | |
234 | __constant_set_bit((nr),(addr)) : \ | |
235 | __set_bit((nr),(addr)) ) | |
236 | ||
237 | /* | |
238 | * fast, non-SMP clear_bit routine | |
239 | */ | |
240 | static inline void | |
241 | __clear_bit(unsigned long nr, volatile unsigned long *ptr) | |
242 | { | |
243 | unsigned long addr; | |
244 | ||
01c2475f | 245 | addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
94c12cc7 | 246 | asm volatile( |
987bcdac MS |
247 | " nc %O0(1,%R0),%1" |
248 | : "=Q" (*(char *) addr) : "Q" (_ni_bitmap[nr & 7]) : "cc" ); | |
1da177e4 LT |
249 | } |
250 | ||
251 | static inline void | |
252 | __constant_clear_bit(const unsigned long nr, volatile unsigned long *ptr) | |
253 | { | |
254 | unsigned long addr; | |
255 | ||
01c2475f | 256 | addr = ((unsigned long) ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
94c12cc7 | 257 | *(unsigned char *) addr &= ~(1 << (nr & 7)); |
1da177e4 LT |
258 | } |
259 | ||
260 | #define clear_bit_simple(nr,addr) \ | |
261 | (__builtin_constant_p((nr)) ? \ | |
262 | __constant_clear_bit((nr),(addr)) : \ | |
263 | __clear_bit((nr),(addr)) ) | |
264 | ||
265 | /* | |
266 | * fast, non-SMP change_bit routine | |
267 | */ | |
268 | static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr) | |
269 | { | |
270 | unsigned long addr; | |
271 | ||
01c2475f | 272 | addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
94c12cc7 | 273 | asm volatile( |
987bcdac MS |
274 | " xc %O0(1,%R0),%1" |
275 | : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" ); | |
1da177e4 LT |
276 | } |
277 | ||
278 | static inline void | |
279 | __constant_change_bit(const unsigned long nr, volatile unsigned long *ptr) | |
280 | { | |
281 | unsigned long addr; | |
282 | ||
01c2475f | 283 | addr = ((unsigned long) ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
94c12cc7 | 284 | *(unsigned char *) addr ^= 1 << (nr & 7); |
1da177e4 LT |
285 | } |
286 | ||
287 | #define change_bit_simple(nr,addr) \ | |
288 | (__builtin_constant_p((nr)) ? \ | |
289 | __constant_change_bit((nr),(addr)) : \ | |
290 | __change_bit((nr),(addr)) ) | |
291 | ||
292 | /* | |
293 | * fast, non-SMP test_and_set_bit routine | |
294 | */ | |
295 | static inline int | |
296 | test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr) | |
297 | { | |
298 | unsigned long addr; | |
299 | unsigned char ch; | |
300 | ||
01c2475f | 301 | addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
1da177e4 | 302 | ch = *(unsigned char *) addr; |
94c12cc7 | 303 | asm volatile( |
987bcdac MS |
304 | " oc %O0(1,%R0),%1" |
305 | : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) | |
306 | : "cc", "memory"); | |
1da177e4 LT |
307 | return (ch >> (nr & 7)) & 1; |
308 | } | |
309 | #define __test_and_set_bit(X,Y) test_and_set_bit_simple(X,Y) | |
310 | ||
311 | /* | |
312 | * fast, non-SMP test_and_clear_bit routine | |
313 | */ | |
314 | static inline int | |
315 | test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr) | |
316 | { | |
317 | unsigned long addr; | |
318 | unsigned char ch; | |
319 | ||
01c2475f | 320 | addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
1da177e4 | 321 | ch = *(unsigned char *) addr; |
94c12cc7 | 322 | asm volatile( |
987bcdac MS |
323 | " nc %O0(1,%R0),%1" |
324 | : "=Q" (*(char *) addr) : "Q" (_ni_bitmap[nr & 7]) | |
325 | : "cc", "memory"); | |
1da177e4 LT |
326 | return (ch >> (nr & 7)) & 1; |
327 | } | |
328 | #define __test_and_clear_bit(X,Y) test_and_clear_bit_simple(X,Y) | |
329 | ||
330 | /* | |
331 | * fast, non-SMP test_and_change_bit routine | |
332 | */ | |
333 | static inline int | |
334 | test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr) | |
335 | { | |
336 | unsigned long addr; | |
337 | unsigned char ch; | |
338 | ||
01c2475f | 339 | addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
1da177e4 | 340 | ch = *(unsigned char *) addr; |
94c12cc7 | 341 | asm volatile( |
987bcdac MS |
342 | " xc %O0(1,%R0),%1" |
343 | : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) | |
344 | : "cc", "memory"); | |
1da177e4 LT |
345 | return (ch >> (nr & 7)) & 1; |
346 | } | |
347 | #define __test_and_change_bit(X,Y) test_and_change_bit_simple(X,Y) | |
348 | ||
349 | #ifdef CONFIG_SMP | |
350 | #define set_bit set_bit_cs | |
351 | #define clear_bit clear_bit_cs | |
352 | #define change_bit change_bit_cs | |
353 | #define test_and_set_bit test_and_set_bit_cs | |
354 | #define test_and_clear_bit test_and_clear_bit_cs | |
355 | #define test_and_change_bit test_and_change_bit_cs | |
356 | #else | |
357 | #define set_bit set_bit_simple | |
358 | #define clear_bit clear_bit_simple | |
359 | #define change_bit change_bit_simple | |
360 | #define test_and_set_bit test_and_set_bit_simple | |
361 | #define test_and_clear_bit test_and_clear_bit_simple | |
362 | #define test_and_change_bit test_and_change_bit_simple | |
363 | #endif | |
364 | ||
365 | ||
366 | /* | |
367 | * This routine doesn't need to be atomic. | |
368 | */ | |
369 | ||
370 | static inline int __test_bit(unsigned long nr, const volatile unsigned long *ptr) | |
371 | { | |
372 | unsigned long addr; | |
373 | unsigned char ch; | |
374 | ||
01c2475f | 375 | addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
1da177e4 LT |
376 | ch = *(volatile unsigned char *) addr; |
377 | return (ch >> (nr & 7)) & 1; | |
378 | } | |
379 | ||
380 | static inline int | |
381 | __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) { | |
ef1bea9e | 382 | return (((volatile char *) addr) |
01c2475f | 383 | [(nr^(BITS_PER_LONG-8))>>3] & (1<<(nr&7))) != 0; |
1da177e4 LT |
384 | } |
385 | ||
386 | #define test_bit(nr,addr) \ | |
387 | (__builtin_constant_p((nr)) ? \ | |
388 | __constant_test_bit((nr),(addr)) : \ | |
389 | __test_bit((nr),(addr)) ) | |
390 | ||
afff7e2b | 391 | /* |
0abbf05c | 392 | * Optimized find bit helper functions. |
afff7e2b | 393 | */ |
0abbf05c MS |
394 | |
395 | /** | |
396 | * __ffz_word_loop - find byte offset of first long != -1UL | |
397 | * @addr: pointer to array of unsigned long | |
398 | * @size: size of the array in bits | |
399 | */ | |
400 | static inline unsigned long __ffz_word_loop(const unsigned long *addr, | |
401 | unsigned long size) | |
402 | { | |
403 | typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype; | |
404 | unsigned long bytes = 0; | |
405 | ||
406 | asm volatile( | |
f4815ac6 | 407 | #ifndef CONFIG_64BIT |
a22fb7ff MS |
408 | " ahi %1,-1\n" |
409 | " sra %1,5\n" | |
410 | " jz 1f\n" | |
0abbf05c MS |
411 | "0: c %2,0(%0,%3)\n" |
412 | " jne 1f\n" | |
413 | " la %0,4(%0)\n" | |
414 | " brct %1,0b\n" | |
415 | "1:\n" | |
416 | #else | |
a22fb7ff MS |
417 | " aghi %1,-1\n" |
418 | " srag %1,%1,6\n" | |
419 | " jz 1f\n" | |
0abbf05c MS |
420 | "0: cg %2,0(%0,%3)\n" |
421 | " jne 1f\n" | |
422 | " la %0,8(%0)\n" | |
423 | " brct %1,0b\n" | |
424 | "1:\n" | |
425 | #endif | |
6d88f827 | 426 | : "+&a" (bytes), "+&d" (size) |
0abbf05c MS |
427 | : "d" (-1UL), "a" (addr), "m" (*(addrtype *) addr) |
428 | : "cc" ); | |
429 | return bytes; | |
430 | } | |
431 | ||
432 | /** | |
433 | * __ffs_word_loop - find byte offset of first long != 0UL | |
434 | * @addr: pointer to array of unsigned long | |
435 | * @size: size of the array in bits | |
436 | */ | |
437 | static inline unsigned long __ffs_word_loop(const unsigned long *addr, | |
438 | unsigned long size) | |
afff7e2b | 439 | { |
0abbf05c MS |
440 | typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype; |
441 | unsigned long bytes = 0; | |
afff7e2b | 442 | |
0abbf05c | 443 | asm volatile( |
f4815ac6 | 444 | #ifndef CONFIG_64BIT |
a22fb7ff MS |
445 | " ahi %1,-1\n" |
446 | " sra %1,5\n" | |
447 | " jz 1f\n" | |
0abbf05c MS |
448 | "0: c %2,0(%0,%3)\n" |
449 | " jne 1f\n" | |
450 | " la %0,4(%0)\n" | |
451 | " brct %1,0b\n" | |
452 | "1:\n" | |
453 | #else | |
a22fb7ff MS |
454 | " aghi %1,-1\n" |
455 | " srag %1,%1,6\n" | |
456 | " jz 1f\n" | |
0abbf05c MS |
457 | "0: cg %2,0(%0,%3)\n" |
458 | " jne 1f\n" | |
459 | " la %0,8(%0)\n" | |
460 | " brct %1,0b\n" | |
461 | "1:\n" | |
462 | #endif | |
6d88f827 | 463 | : "+&a" (bytes), "+&a" (size) |
0abbf05c MS |
464 | : "d" (0UL), "a" (addr), "m" (*(addrtype *) addr) |
465 | : "cc" ); | |
466 | return bytes; | |
467 | } | |
468 | ||
469 | /** | |
470 | * __ffz_word - add number of the first unset bit | |
471 | * @nr: base value the bit number is added to | |
472 | * @word: the word that is searched for unset bits | |
473 | */ | |
474 | static inline unsigned long __ffz_word(unsigned long nr, unsigned long word) | |
475 | { | |
f4815ac6 | 476 | #ifdef CONFIG_64BIT |
e13ed9b2 | 477 | if ((word & 0xffffffff) == 0xffffffff) { |
afff7e2b | 478 | word >>= 32; |
0abbf05c | 479 | nr += 32; |
afff7e2b MS |
480 | } |
481 | #endif | |
e13ed9b2 | 482 | if ((word & 0xffff) == 0xffff) { |
afff7e2b | 483 | word >>= 16; |
0abbf05c | 484 | nr += 16; |
afff7e2b | 485 | } |
e13ed9b2 | 486 | if ((word & 0xff) == 0xff) { |
afff7e2b | 487 | word >>= 8; |
0abbf05c | 488 | nr += 8; |
afff7e2b | 489 | } |
0abbf05c | 490 | return nr + _zb_findmap[(unsigned char) word]; |
afff7e2b MS |
491 | } |
492 | ||
0abbf05c MS |
493 | /** |
494 | * __ffs_word - add number of the first set bit | |
495 | * @nr: base value the bit number is added to | |
496 | * @word: the word that is searched for set bits | |
afff7e2b | 497 | */ |
0abbf05c | 498 | static inline unsigned long __ffs_word(unsigned long nr, unsigned long word) |
afff7e2b | 499 | { |
f4815ac6 | 500 | #ifdef CONFIG_64BIT |
e13ed9b2 | 501 | if ((word & 0xffffffff) == 0) { |
afff7e2b | 502 | word >>= 32; |
0abbf05c | 503 | nr += 32; |
afff7e2b MS |
504 | } |
505 | #endif | |
e13ed9b2 | 506 | if ((word & 0xffff) == 0) { |
afff7e2b | 507 | word >>= 16; |
0abbf05c | 508 | nr += 16; |
afff7e2b | 509 | } |
e13ed9b2 | 510 | if ((word & 0xff) == 0) { |
afff7e2b | 511 | word >>= 8; |
0abbf05c | 512 | nr += 8; |
afff7e2b | 513 | } |
0abbf05c | 514 | return nr + _sb_findmap[(unsigned char) word]; |
afff7e2b | 515 | } |
1da177e4 | 516 | |
afff7e2b | 517 | |
0abbf05c MS |
518 | /** |
519 | * __load_ulong_be - load big endian unsigned long | |
520 | * @p: pointer to array of unsigned long | |
521 | * @offset: byte offset of source value in the array | |
522 | */ | |
523 | static inline unsigned long __load_ulong_be(const unsigned long *p, | |
524 | unsigned long offset) | |
525 | { | |
526 | p = (unsigned long *)((unsigned long) p + offset); | |
527 | return *p; | |
528 | } | |
afff7e2b | 529 | |
0abbf05c MS |
530 | /** |
531 | * __load_ulong_le - load little endian unsigned long | |
532 | * @p: pointer to array of unsigned long | |
533 | * @offset: byte offset of source value in the array | |
534 | */ | |
535 | static inline unsigned long __load_ulong_le(const unsigned long *p, | |
536 | unsigned long offset) | |
1da177e4 | 537 | { |
0abbf05c | 538 | unsigned long word; |
1da177e4 | 539 | |
0abbf05c | 540 | p = (unsigned long *)((unsigned long) p + offset); |
f4815ac6 | 541 | #ifndef CONFIG_64BIT |
94c12cc7 | 542 | asm volatile( |
987bcdac MS |
543 | " ic %0,%O1(%R1)\n" |
544 | " icm %0,2,%O1+1(%R1)\n" | |
545 | " icm %0,4,%O1+2(%R1)\n" | |
546 | " icm %0,8,%O1+3(%R1)" | |
547 | : "=&d" (word) : "Q" (*p) : "cc"); | |
0abbf05c MS |
548 | #else |
549 | asm volatile( | |
550 | " lrvg %0,%1" | |
551 | : "=d" (word) : "m" (*p) ); | |
552 | #endif | |
553 | return word; | |
1da177e4 LT |
554 | } |
555 | ||
0abbf05c MS |
556 | /* |
557 | * The various find bit functions. | |
558 | */ | |
559 | ||
560 | /* | |
561 | * ffz - find first zero in word. | |
562 | * @word: The word to search | |
563 | * | |
564 | * Undefined if no zero exists, so code should check against ~0UL first. | |
565 | */ | |
566 | static inline unsigned long ffz(unsigned long word) | |
1da177e4 | 567 | { |
0abbf05c MS |
568 | return __ffz_word(0, word); |
569 | } | |
1da177e4 | 570 | |
0abbf05c MS |
571 | /** |
572 | * __ffs - find first bit in word. | |
573 | * @word: The word to search | |
574 | * | |
575 | * Undefined if no bit exists, so code should check against 0 first. | |
576 | */ | |
577 | static inline unsigned long __ffs (unsigned long word) | |
578 | { | |
579 | return __ffs_word(0, word); | |
1da177e4 LT |
580 | } |
581 | ||
0abbf05c MS |
582 | /** |
583 | * ffs - find first bit set | |
584 | * @x: the word to search | |
585 | * | |
586 | * This is defined the same way as | |
587 | * the libc and compiler builtin ffs routines, therefore | |
588 | * differs in spirit from the above ffz (man ffs). | |
589 | */ | |
590 | static inline int ffs(int x) | |
591 | { | |
592 | if (!x) | |
593 | return 0; | |
594 | return __ffs_word(1, x); | |
595 | } | |
1da177e4 | 596 | |
0abbf05c MS |
597 | /** |
598 | * find_first_zero_bit - find the first zero bit in a memory region | |
599 | * @addr: The address to start the search at | |
600 | * @size: The maximum size to search | |
601 | * | |
602 | * Returns the bit-number of the first zero bit, not the number of the byte | |
603 | * containing a bit. | |
604 | */ | |
605 | static inline unsigned long find_first_zero_bit(const unsigned long *addr, | |
606 | unsigned long size) | |
1da177e4 | 607 | { |
0abbf05c | 608 | unsigned long bytes, bits; |
1da177e4 LT |
609 | |
610 | if (!size) | |
611 | return 0; | |
0abbf05c MS |
612 | bytes = __ffz_word_loop(addr, size); |
613 | bits = __ffz_word(bytes*8, __load_ulong_be(addr, bytes)); | |
614 | return (bits < size) ? bits : size; | |
615 | } | |
a2812e17 | 616 | #define find_first_zero_bit find_first_zero_bit |
0abbf05c MS |
617 | |
618 | /** | |
619 | * find_first_bit - find the first set bit in a memory region | |
620 | * @addr: The address to start the search at | |
621 | * @size: The maximum size to search | |
622 | * | |
623 | * Returns the bit-number of the first set bit, not the number of the byte | |
624 | * containing a bit. | |
625 | */ | |
626 | static inline unsigned long find_first_bit(const unsigned long * addr, | |
627 | unsigned long size) | |
1da177e4 | 628 | { |
0abbf05c | 629 | unsigned long bytes, bits; |
1da177e4 LT |
630 | |
631 | if (!size) | |
632 | return 0; | |
0abbf05c MS |
633 | bytes = __ffs_word_loop(addr, size); |
634 | bits = __ffs_word(bytes*8, __load_ulong_be(addr, bytes)); | |
635 | return (bits < size) ? bits : size; | |
1da177e4 | 636 | } |
a2812e17 | 637 | #define find_first_bit find_first_bit |
1da177e4 | 638 | |
e56e4e87 JG |
639 | /* |
640 | * Big endian variant whichs starts bit counting from left using | |
641 | * the flogr (find leftmost one) instruction. | |
642 | */ | |
643 | static inline unsigned long __flo_word(unsigned long nr, unsigned long val) | |
644 | { | |
645 | register unsigned long bit asm("2") = val; | |
646 | register unsigned long out asm("3"); | |
647 | ||
648 | asm volatile ( | |
649 | " .insn rre,0xb9830000,%[bit],%[bit]\n" | |
650 | : [bit] "+d" (bit), [out] "=d" (out) : : "cc"); | |
651 | return nr + bit; | |
652 | } | |
653 | ||
654 | /* | |
655 | * 64 bit special left bitops format: | |
656 | * order in memory: | |
657 | * 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f | |
658 | * 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f | |
659 | * 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f | |
660 | * 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f | |
661 | * after that follows the next long with bit numbers | |
662 | * 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f | |
663 | * 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f | |
664 | * 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f | |
665 | * 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f | |
666 | * The reason for this bit ordering is the fact that | |
667 | * the hardware sets bits in a bitmap starting at bit 0 | |
668 | * and we don't want to scan the bitmap from the 'wrong | |
669 | * end'. | |
670 | */ | |
671 | static inline unsigned long find_first_bit_left(const unsigned long *addr, | |
672 | unsigned long size) | |
673 | { | |
674 | unsigned long bytes, bits; | |
675 | ||
676 | if (!size) | |
677 | return 0; | |
678 | bytes = __ffs_word_loop(addr, size); | |
679 | bits = __flo_word(bytes * 8, __load_ulong_be(addr, bytes)); | |
680 | return (bits < size) ? bits : size; | |
681 | } | |
682 | ||
683 | static inline int find_next_bit_left(const unsigned long *addr, | |
684 | unsigned long size, | |
685 | unsigned long offset) | |
686 | { | |
687 | const unsigned long *p; | |
688 | unsigned long bit, set; | |
689 | ||
690 | if (offset >= size) | |
691 | return size; | |
01c2475f | 692 | bit = offset & (BITS_PER_LONG - 1); |
e56e4e87 JG |
693 | offset -= bit; |
694 | size -= offset; | |
01c2475f | 695 | p = addr + offset / BITS_PER_LONG; |
e56e4e87 JG |
696 | if (bit) { |
697 | set = __flo_word(0, *p & (~0UL << bit)); | |
698 | if (set >= size) | |
699 | return size + offset; | |
01c2475f | 700 | if (set < BITS_PER_LONG) |
e56e4e87 | 701 | return set + offset; |
01c2475f AM |
702 | offset += BITS_PER_LONG; |
703 | size -= BITS_PER_LONG; | |
e56e4e87 JG |
704 | p++; |
705 | } | |
706 | return offset + find_first_bit_left(p, size); | |
707 | } | |
708 | ||
709 | #define for_each_set_bit_left(bit, addr, size) \ | |
710 | for ((bit) = find_first_bit_left((addr), (size)); \ | |
711 | (bit) < (size); \ | |
712 | (bit) = find_next_bit_left((addr), (size), (bit) + 1)) | |
713 | ||
714 | /* same as for_each_set_bit() but use bit as value to start with */ | |
715 | #define for_each_set_bit_left_cont(bit, addr, size) \ | |
716 | for ((bit) = find_next_bit_left((addr), (size), (bit)); \ | |
717 | (bit) < (size); \ | |
718 | (bit) = find_next_bit_left((addr), (size), (bit) + 1)) | |
719 | ||
0abbf05c MS |
720 | /** |
721 | * find_next_zero_bit - find the first zero bit in a memory region | |
722 | * @addr: The address to base the search on | |
723 | * @offset: The bitnumber to start searching at | |
724 | * @size: The maximum size to search | |
725 | */ | |
726 | static inline int find_next_zero_bit (const unsigned long * addr, | |
727 | unsigned long size, | |
728 | unsigned long offset) | |
1da177e4 | 729 | { |
afff7e2b MS |
730 | const unsigned long *p; |
731 | unsigned long bit, set; | |
732 | ||
733 | if (offset >= size) | |
734 | return size; | |
01c2475f | 735 | bit = offset & (BITS_PER_LONG - 1); |
afff7e2b MS |
736 | offset -= bit; |
737 | size -= offset; | |
01c2475f | 738 | p = addr + offset / BITS_PER_LONG; |
afff7e2b MS |
739 | if (bit) { |
740 | /* | |
01c2475f | 741 | * __ffz_word returns BITS_PER_LONG |
afff7e2b MS |
742 | * if no zero bit is present in the word. |
743 | */ | |
152382af | 744 | set = __ffz_word(bit, *p >> bit); |
afff7e2b MS |
745 | if (set >= size) |
746 | return size + offset; | |
01c2475f | 747 | if (set < BITS_PER_LONG) |
afff7e2b | 748 | return set + offset; |
01c2475f AM |
749 | offset += BITS_PER_LONG; |
750 | size -= BITS_PER_LONG; | |
afff7e2b | 751 | p++; |
1da177e4 | 752 | } |
afff7e2b | 753 | return offset + find_first_zero_bit(p, size); |
1da177e4 | 754 | } |
a2812e17 | 755 | #define find_next_zero_bit find_next_zero_bit |
1da177e4 | 756 | |
0abbf05c MS |
757 | /** |
758 | * find_next_bit - find the first set bit in a memory region | |
759 | * @addr: The address to base the search on | |
760 | * @offset: The bitnumber to start searching at | |
761 | * @size: The maximum size to search | |
762 | */ | |
763 | static inline int find_next_bit (const unsigned long * addr, | |
764 | unsigned long size, | |
765 | unsigned long offset) | |
1da177e4 | 766 | { |
afff7e2b MS |
767 | const unsigned long *p; |
768 | unsigned long bit, set; | |
769 | ||
770 | if (offset >= size) | |
771 | return size; | |
01c2475f | 772 | bit = offset & (BITS_PER_LONG - 1); |
afff7e2b MS |
773 | offset -= bit; |
774 | size -= offset; | |
01c2475f | 775 | p = addr + offset / BITS_PER_LONG; |
afff7e2b MS |
776 | if (bit) { |
777 | /* | |
01c2475f | 778 | * __ffs_word returns BITS_PER_LONG |
afff7e2b MS |
779 | * if no one bit is present in the word. |
780 | */ | |
0abbf05c | 781 | set = __ffs_word(0, *p & (~0UL << bit)); |
afff7e2b MS |
782 | if (set >= size) |
783 | return size + offset; | |
01c2475f | 784 | if (set < BITS_PER_LONG) |
afff7e2b | 785 | return set + offset; |
01c2475f AM |
786 | offset += BITS_PER_LONG; |
787 | size -= BITS_PER_LONG; | |
afff7e2b | 788 | p++; |
1da177e4 | 789 | } |
afff7e2b | 790 | return offset + find_first_bit(p, size); |
1da177e4 | 791 | } |
a2812e17 | 792 | #define find_next_bit find_next_bit |
1da177e4 LT |
793 | |
794 | /* | |
795 | * Every architecture must define this function. It's the fastest | |
796 | * way of searching a 140-bit bitmap where the first 100 bits are | |
797 | * unlikely to be set. It's guaranteed that at least one of the 140 | |
798 | * bits is cleared. | |
799 | */ | |
800 | static inline int sched_find_first_bit(unsigned long *b) | |
801 | { | |
802 | return find_first_bit(b, 140); | |
803 | } | |
804 | ||
7e33db4e | 805 | #include <asm-generic/bitops/fls.h> |
56a6b1eb | 806 | #include <asm-generic/bitops/__fls.h> |
7e33db4e | 807 | #include <asm-generic/bitops/fls64.h> |
1da177e4 | 808 | |
7e33db4e | 809 | #include <asm-generic/bitops/hweight.h> |
26333576 | 810 | #include <asm-generic/bitops/lock.h> |
1da177e4 | 811 | |
1da177e4 LT |
812 | /* |
813 | * ATTENTION: intel byte ordering convention for ext2 and minix !! | |
814 | * bit 0 is the LSB of addr; bit 31 is the MSB of addr; | |
815 | * bit 32 is the LSB of (addr+4). | |
816 | * That combined with the little endian byte order of Intel gives the | |
817 | * following bit order in memory: | |
818 | * 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 \ | |
819 | * 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 | |
820 | */ | |
821 | ||
50b9b475 | 822 | static inline int find_first_zero_bit_le(void *vaddr, unsigned int size) |
1da177e4 | 823 | { |
0abbf05c | 824 | unsigned long bytes, bits; |
1da177e4 LT |
825 | |
826 | if (!size) | |
827 | return 0; | |
0abbf05c MS |
828 | bytes = __ffz_word_loop(vaddr, size); |
829 | bits = __ffz_word(bytes*8, __load_ulong_le(vaddr, bytes)); | |
830 | return (bits < size) ? bits : size; | |
1da177e4 | 831 | } |
a2812e17 | 832 | #define find_first_zero_bit_le find_first_zero_bit_le |
1da177e4 | 833 | |
50b9b475 | 834 | static inline int find_next_zero_bit_le(void *vaddr, unsigned long size, |
0abbf05c | 835 | unsigned long offset) |
1da177e4 | 836 | { |
afff7e2b | 837 | unsigned long *addr = vaddr, *p; |
0abbf05c | 838 | unsigned long bit, set; |
1da177e4 LT |
839 | |
840 | if (offset >= size) | |
841 | return size; | |
01c2475f | 842 | bit = offset & (BITS_PER_LONG - 1); |
afff7e2b MS |
843 | offset -= bit; |
844 | size -= offset; | |
01c2475f | 845 | p = addr + offset / BITS_PER_LONG; |
1da177e4 | 846 | if (bit) { |
afff7e2b | 847 | /* |
01c2475f | 848 | * s390 version of ffz returns BITS_PER_LONG |
afff7e2b MS |
849 | * if no zero bit is present in the word. |
850 | */ | |
152382af | 851 | set = __ffz_word(bit, __load_ulong_le(p, 0) >> bit); |
afff7e2b MS |
852 | if (set >= size) |
853 | return size + offset; | |
01c2475f | 854 | if (set < BITS_PER_LONG) |
afff7e2b | 855 | return set + offset; |
01c2475f AM |
856 | offset += BITS_PER_LONG; |
857 | size -= BITS_PER_LONG; | |
afff7e2b | 858 | p++; |
1da177e4 | 859 | } |
50b9b475 | 860 | return offset + find_first_zero_bit_le(p, size); |
1da177e4 | 861 | } |
a2812e17 | 862 | #define find_next_zero_bit_le find_next_zero_bit_le |
1da177e4 | 863 | |
50b9b475 | 864 | static inline unsigned long find_first_bit_le(void *vaddr, unsigned long size) |
67fe9251 HC |
865 | { |
866 | unsigned long bytes, bits; | |
867 | ||
868 | if (!size) | |
869 | return 0; | |
870 | bytes = __ffs_word_loop(vaddr, size); | |
871 | bits = __ffs_word(bytes*8, __load_ulong_le(vaddr, bytes)); | |
872 | return (bits < size) ? bits : size; | |
873 | } | |
a2812e17 | 874 | #define find_first_bit_le find_first_bit_le |
67fe9251 | 875 | |
50b9b475 | 876 | static inline int find_next_bit_le(void *vaddr, unsigned long size, |
67fe9251 HC |
877 | unsigned long offset) |
878 | { | |
879 | unsigned long *addr = vaddr, *p; | |
880 | unsigned long bit, set; | |
881 | ||
882 | if (offset >= size) | |
883 | return size; | |
01c2475f | 884 | bit = offset & (BITS_PER_LONG - 1); |
67fe9251 HC |
885 | offset -= bit; |
886 | size -= offset; | |
01c2475f | 887 | p = addr + offset / BITS_PER_LONG; |
67fe9251 HC |
888 | if (bit) { |
889 | /* | |
01c2475f | 890 | * s390 version of ffz returns BITS_PER_LONG |
67fe9251 HC |
891 | * if no zero bit is present in the word. |
892 | */ | |
152382af | 893 | set = __ffs_word(0, __load_ulong_le(p, 0) & (~0UL << bit)); |
67fe9251 HC |
894 | if (set >= size) |
895 | return size + offset; | |
01c2475f | 896 | if (set < BITS_PER_LONG) |
67fe9251 | 897 | return set + offset; |
01c2475f AM |
898 | offset += BITS_PER_LONG; |
899 | size -= BITS_PER_LONG; | |
67fe9251 HC |
900 | p++; |
901 | } | |
50b9b475 AM |
902 | return offset + find_first_bit_le(p, size); |
903 | } | |
a2812e17 | 904 | #define find_next_bit_le find_next_bit_le |
50b9b475 | 905 | |
802caabb AM |
906 | #include <asm-generic/bitops/le.h> |
907 | ||
148817ba | 908 | #include <asm-generic/bitops/ext2-atomic-setbit.h> |
67fe9251 | 909 | |
1da177e4 | 910 | #endif /* _S390_BITOPS_H */ |