[deliverable/linux.git] / arch / s390 / include / asm / bitops.h

/*
 *    Copyright IBM Corp. 1999,2013
 *
 *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
 *
 * The description below was taken in large parts from the powerpc
 * bitops header file:
 * Within a word, bits are numbered LSB first.  Lot's of places make
 * this assumption by directly testing bits with (val & (1<<nr)).
 * This can cause confusion for large (> 1 word) bitmaps on a
 * big-endian system because, unlike little endian, the number of each
 * bit depends on the word size.
 *
 * The bitop functions are defined to work on unsigned longs, so for an
 * s390x system the bits end up numbered:
 *   |63..............0|127............64|191...........128|255...........196|
 * and on s390:
 *   |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
 *
 * There are a few little-endian macros used mostly for filesystem
 * bitmaps, these work on similar bit arrays layouts, but
 * byte-oriented:
 *   |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
 *
 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
 * number field needs to be reversed compared to the big-endian bit
 * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
 *
 * We also have special functions which work with an MSB0 encoding:
 * on an s390x system the bits are numbered:
 *   |0..............63|64............127|128...........191|192...........255|
 * and on s390:
 *   |0.....31|31....63|64....95|96...127|128..159|160..191|192..223|224..255|
 *
 * The main difference is that bit 0-63 (64b) or 0-31 (32b) in the bit
 * number field needs to be reversed compared to the LSB0 encoded bit
 * fields. This can be achieved by XOR with 0x3f (64b) or 0x1f (32b).
 *
 */

#ifndef _S390_BITOPS_H
#define _S390_BITOPS_H

#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif

#include <linux/typecheck.h>
#include <linux/compiler.h>

#ifndef CONFIG_64BIT

#define __BITOPS_OR		"or"
#define __BITOPS_AND		"nr"
#define __BITOPS_XOR		"xr"

#define __BITOPS_LOOP(__addr, __val, __op_string)		\
({								\
	unsigned long __old, __new;				\
								\
	typecheck(unsigned long *, (__addr));			\
	asm volatile(						\
		"	l	%0,%2\n"			\
		"0:	lr	%1,%0\n"			\
		__op_string "	%1,%3\n"			\
		"	cs	%0,%1,%2\n"			\
		"	jl	0b"				\
		: "=&d" (__old), "=&d" (__new), "+Q" (*(__addr))\
		: "d" (__val)					\
		: "cc");					\
	__old;							\
})

#else /* CONFIG_64BIT */

#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES

#define __BITOPS_OR		"laog"
#define __BITOPS_AND		"lang"
#define __BITOPS_XOR		"laxg"

#define __BITOPS_LOOP(__addr, __val, __op_string)		\
({								\
	unsigned long __old;					\
								\
	typecheck(unsigned long *, (__addr));			\
	asm volatile(						\
		__op_string "	%0,%2,%1\n"			\
		: "=d" (__old),	"+Q" (*(__addr))		\
		: "d" (__val)					\
		: "cc");					\
	__old;							\
})

#else /* CONFIG_HAVE_MARCH_Z196_FEATURES */

#define __BITOPS_OR		"ogr"
#define __BITOPS_AND		"ngr"
#define __BITOPS_XOR		"xgr"

#define __BITOPS_LOOP(__addr, __val, __op_string)		\
({								\
	unsigned long __old, __new;				\
								\
	typecheck(unsigned long *, (__addr));			\
	asm volatile(						\
		"	lg	%0,%2\n"			\
		"0:	lgr	%1,%0\n"			\
		__op_string "	%1,%3\n"			\
		"	csg	%0,%1,%2\n"			\
		"	jl	0b"				\
		: "=&d" (__old), "=&d" (__new), "+Q" (*(__addr))\
		: "d" (__val)					\
		: "cc");					\
	__old;							\
})

#endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */

#endif /* CONFIG_64BIT */

#define __BITOPS_WORDS(bits) (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)

static inline unsigned long *
__bitops_word(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long addr;

	addr = (unsigned long)ptr + ((nr ^ (nr & (BITS_PER_LONG - 1))) >> 3);
	return (unsigned long *)addr;
}

static inline unsigned char *
__bitops_byte(unsigned long nr, volatile unsigned long *ptr)
{
	return ((unsigned char *)ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
}

static inline void set_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long *addr = __bitops_word(nr, ptr);
	unsigned long mask;

#ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
	if (__builtin_constant_p(nr)) {
		unsigned char *caddr = __bitops_byte(nr, ptr);

		asm volatile(
			"oi	%0,%b1\n"
			: "+Q" (*caddr)
			: "i" (1 << (nr & 7))
			: "cc");
		return;
	}
#endif
	mask = 1UL << (nr & (BITS_PER_LONG - 1));
	__BITOPS_LOOP(addr, mask, __BITOPS_OR);
}

static inline void clear_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long *addr = __bitops_word(nr, ptr);
	unsigned long mask;

#ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
	if (__builtin_constant_p(nr)) {
		unsigned char *caddr = __bitops_byte(nr, ptr);

		asm volatile(
			"ni	%0,%b1\n"
			: "+Q" (*caddr)
			: "i" (~(1 << (nr & 7)))
			: "cc");
		return;
	}
#endif
	mask = ~(1UL << (nr & (BITS_PER_LONG - 1)));
	__BITOPS_LOOP(addr, mask, __BITOPS_AND);
}

static inline void change_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long *addr = __bitops_word(nr, ptr);
	unsigned long mask;

#ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
	if (__builtin_constant_p(nr)) {
		unsigned char *caddr = __bitops_byte(nr, ptr);

		asm volatile(
			"xi	%0,%b1\n"
			: "+Q" (*caddr)
			: "i" (1 << (nr & 7))
			: "cc");
		return;
	}
#endif
	mask = 1UL << (nr & (BITS_PER_LONG - 1));
	__BITOPS_LOOP(addr, mask, __BITOPS_XOR);
}

static inline int
test_and_set_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long *addr = __bitops_word(nr, ptr);
	unsigned long old, mask;

	mask = 1UL << (nr & (BITS_PER_LONG - 1));
	old = __BITOPS_LOOP(addr, mask, __BITOPS_OR);
	barrier();
	return (old & mask) != 0;
}

static inline int
test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long *addr = __bitops_word(nr, ptr);
	unsigned long old, mask;

	mask = ~(1UL << (nr & (BITS_PER_LONG - 1)));
	old = __BITOPS_LOOP(addr, mask, __BITOPS_AND);
	barrier();
	return (old & ~mask) != 0;
}

static inline int
test_and_change_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned long *addr = __bitops_word(nr, ptr);
	unsigned long old, mask;

	mask = 1UL << (nr & (BITS_PER_LONG - 1));
	old = __BITOPS_LOOP(addr, mask, __BITOPS_XOR);
	barrier();
	return (old & mask) != 0;
}

static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned char *addr = __bitops_byte(nr, ptr);

	*addr |= 1 << (nr & 7);
}

static inline void 
__clear_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned char *addr = __bitops_byte(nr, ptr);

	*addr &= ~(1 << (nr & 7));
}

static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned char *addr = __bitops_byte(nr, ptr);

	*addr ^= 1 << (nr & 7);
}

static inline int
__test_and_set_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned char *addr = __bitops_byte(nr, ptr);
	unsigned char ch;

	ch = *addr;
	*addr |= 1 << (nr & 7);
	return (ch >> (nr & 7)) & 1;
}

static inline int
__test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned char *addr = __bitops_byte(nr, ptr);
	unsigned char ch;

	ch = *addr;
	*addr &= ~(1 << (nr & 7));
	return (ch >> (nr & 7)) & 1;
}

static inline int
__test_and_change_bit(unsigned long nr, volatile unsigned long *ptr)
{
	unsigned char *addr = __bitops_byte(nr, ptr);
	unsigned char ch;

	ch = *addr;
	*addr ^= 1 << (nr & 7);
	return (ch >> (nr & 7)) & 1;
}

static inline int test_bit(unsigned long nr, const volatile unsigned long *ptr)
{
	const volatile unsigned char *addr;

	addr = ((const volatile unsigned char *)ptr);
	addr += (nr ^ (BITS_PER_LONG - 8)) >> 3;
	return (*addr >> (nr & 7)) & 1;
}

/*
 * ATTENTION:
 * find_first_bit_left() and find_next_bit_left() use MSB0 encoding.
 */
unsigned long find_first_bit_left(const unsigned long *addr, unsigned long size);
unsigned long find_next_bit_left(const unsigned long *addr, unsigned long size,
				 unsigned long offset);

#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/ffz.h>
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic-setbit.h>

#endif /* _S390_BITOPS_H */
Commit	Line	Data
1da177e4	1	/*
746479cd	2	* Copyright IBM Corp. 1999,2013
1da177e4	3	*
746479cd HC	4	* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
	5	*
	6	* The description below was taken in large parts from the powerpc
	7	* bitops header file:
	8	* Within a word, bits are numbered LSB first. Lot's of places make
	9	* this assumption by directly testing bits with (val & (1<<nr)).
	10	* This can cause confusion for large (> 1 word) bitmaps on a
	11	* big-endian system because, unlike little endian, the number of each
	12	* bit depends on the word size.
	13	*
	14	* The bitop functions are defined to work on unsigned longs, so for an
	15	* s390x system the bits end up numbered:
	16	* \|63..............0\|127............64\|191...........128\|255...........196\|
	17	* and on s390:
	18	* \|31.....0\|63....31\|95....64\|127...96\|159..128\|191..160\|223..192\|255..224\|
	19	*
	20	* There are a few little-endian macros used mostly for filesystem
	21	* bitmaps, these work on similar bit arrays layouts, but
	22	* byte-oriented:
	23	* \|7...0\|15...8\|23...16\|31...24\|39...32\|47...40\|55...48\|63...56\|
	24	*
	25	* The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
	26	* number field needs to be reversed compared to the big-endian bit
	27	* fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
	28	*
	29	* We also have special functions which work with an MSB0 encoding:
	30	* on an s390x system the bits are numbered:
	31	* \|0..............63\|64............127\|128...........191\|192...........255\|
	32	* and on s390:
	33	* \|0.....31\|31....63\|64....95\|96...127\|128..159\|160..191\|192..223\|224..255\|
	34	*
	35	* The main difference is that bit 0-63 (64b) or 0-31 (32b) in the bit
	36	* number field needs to be reversed compared to the LSB0 encoded bit
	37	* fields. This can be achieved by XOR with 0x3f (64b) or 0x1f (32b).
1da177e4 LT	38	*
1da177e4 LT	39	*/
c406abd3	40
a53c8fab HC	41	#ifndef _S390_BITOPS_H
	42	#define _S390_BITOPS_H
	43
0624517d JS	44	#ifndef _LINUX_BITOPS_H
	45	#error only <linux/bitops.h> can be included directly
	46	#endif
	47
370b0b5f	48	#include <linux/typecheck.h>
1da177e4 LT	49	#include <linux/compiler.h>
1da177e4 LT	50
f4815ac6	51	#ifndef CONFIG_64BIT
1da177e4	52
1da177e4 LT	53	#define __BITOPS_OR "or"
	54	#define __BITOPS_AND "nr"
	55	#define __BITOPS_XOR "xr"
	56
e344e52c HC	57	#define __BITOPS_LOOP(__addr, __val, __op_string) \
	58	({ \
	59	unsigned long __old, __new; \
	60	\
370b0b5f	61	typecheck(unsigned long *, (__addr)); \
94c12cc7 MS	62	asm volatile( \
	63	" l %0,%2\n" \
	64	"0: lr %1,%0\n" \
	65	__op_string " %1,%3\n" \
	66	" cs %0,%1,%2\n" \
	67	" jl 0b" \
370b0b5f HC	68	: "=&d" (__old), "=&d" (__new), "+Q" (*(__addr))\
370b0b5f HC	69	: "d" (__val) \
e344e52c HC	70	: "cc"); \
	71	__old; \
	72	})
94c12cc7	73
f4815ac6	74	#else /* CONFIG_64BIT */
1da177e4	75
e344e52c HC	76	#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
	77
	78	#define __BITOPS_OR "laog"
	79	#define __BITOPS_AND "lang"
	80	#define __BITOPS_XOR "laxg"
	81
	82	#define __BITOPS_LOOP(__addr, __val, __op_string) \
	83	({ \
	84	unsigned long __old; \
	85	\
370b0b5f	86	typecheck(unsigned long *, (__addr)); \
e344e52c HC	87	asm volatile( \
e344e52c HC	88	__op_string " %0,%2,%1\n" \
370b0b5f	89	: "=d" (__old), "+Q" (*(__addr)) \
e344e52c HC	90	: "d" (__val) \
	91	: "cc"); \
	92	__old; \
	93	})
	94
	95	#else /* CONFIG_HAVE_MARCH_Z196_FEATURES */
	96
1da177e4 LT	97	#define __BITOPS_OR "ogr"
	98	#define __BITOPS_AND "ngr"
	99	#define __BITOPS_XOR "xgr"
	100
e344e52c HC	101	#define __BITOPS_LOOP(__addr, __val, __op_string) \
	102	({ \
	103	unsigned long __old, __new; \
	104	\
370b0b5f	105	typecheck(unsigned long *, (__addr)); \
94c12cc7 MS	106	asm volatile( \
	107	" lg %0,%2\n" \
	108	"0: lgr %1,%0\n" \
	109	__op_string " %1,%3\n" \
	110	" csg %0,%1,%2\n" \
	111	" jl 0b" \
370b0b5f HC	112	: "=&d" (__old), "=&d" (__new), "+Q" (*(__addr))\
370b0b5f HC	113	: "d" (__val) \
e344e52c HC	114	: "cc"); \
	115	__old; \
	116	})
	117
	118	#endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */
94c12cc7	119
f4815ac6	120	#endif /* CONFIG_64BIT */
1da177e4	121
01c2475f	122	#define __BITOPS_WORDS(bits) (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
1da177e4	123
370b0b5f HC	124	static inline unsigned long *
	125	__bitops_word(unsigned long nr, volatile unsigned long *ptr)
	126	{
	127	unsigned long addr;
	128
	129	addr = (unsigned long)ptr + ((nr ^ (nr & (BITS_PER_LONG - 1))) >> 3);
	130	return (unsigned long *)addr;
	131	}
	132
	133	static inline unsigned char *
	134	__bitops_byte(unsigned long nr, volatile unsigned long *ptr)
	135	{
	136	return ((unsigned char *)ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
	137	}
	138
	139	static inline void set_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	140	{
370b0b5f HC	141	unsigned long *addr = __bitops_word(nr, ptr);
370b0b5f HC	142	unsigned long mask;
1da177e4	143
4ae80325 HC	144	#ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
	145	if (__builtin_constant_p(nr)) {
	146	unsigned char *caddr = __bitops_byte(nr, ptr);
	147
	148	asm volatile(
	149	"oi %0,%b1\n"
	150	: "+Q" (*caddr)
	151	: "i" (1 << (nr & 7))
	152	: "cc");
	153	return;
	154	}
	155	#endif
01c2475f	156	mask = 1UL << (nr & (BITS_PER_LONG - 1));
e344e52c	157	__BITOPS_LOOP(addr, mask, __BITOPS_OR);
1da177e4 LT	158	}
1da177e4 LT	159
370b0b5f	160	static inline void clear_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	161	{
370b0b5f HC	162	unsigned long *addr = __bitops_word(nr, ptr);
370b0b5f HC	163	unsigned long mask;
1da177e4	164
4ae80325 HC	165	#ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
	166	if (__builtin_constant_p(nr)) {
	167	unsigned char *caddr = __bitops_byte(nr, ptr);
	168
	169	asm volatile(
	170	"ni %0,%b1\n"
	171	: "+Q" (*caddr)
	172	: "i" (~(1 << (nr & 7)))
	173	: "cc");
	174	return;
	175	}
	176	#endif
01c2475f	177	mask = ~(1UL << (nr & (BITS_PER_LONG - 1)));
e344e52c	178	__BITOPS_LOOP(addr, mask, __BITOPS_AND);
1da177e4 LT	179	}
1da177e4 LT	180
370b0b5f	181	static inline void change_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	182	{
370b0b5f HC	183	unsigned long *addr = __bitops_word(nr, ptr);
370b0b5f HC	184	unsigned long mask;
1da177e4	185
4ae80325 HC	186	#ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
	187	if (__builtin_constant_p(nr)) {
	188	unsigned char *caddr = __bitops_byte(nr, ptr);
	189
	190	asm volatile(
	191	"xi %0,%b1\n"
	192	: "+Q" (*caddr)
	193	: "i" (1 << (nr & 7))
	194	: "cc");
	195	return;
	196	}
	197	#endif
01c2475f	198	mask = 1UL << (nr & (BITS_PER_LONG - 1));
e344e52c	199	__BITOPS_LOOP(addr, mask, __BITOPS_XOR);
1da177e4 LT	200	}
1da177e4 LT	201
1da177e4	202	static inline int
370b0b5f	203	test_and_set_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	204	{
370b0b5f HC	205	unsigned long *addr = __bitops_word(nr, ptr);
370b0b5f HC	206	unsigned long old, mask;
1da177e4	207
01c2475f	208	mask = 1UL << (nr & (BITS_PER_LONG - 1));
e344e52c	209	old = __BITOPS_LOOP(addr, mask, __BITOPS_OR);
5294ee00	210	barrier();
1da177e4 LT	211	return (old & mask) != 0;
	212	}
	213
1da177e4	214	static inline int
370b0b5f	215	test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	216	{
370b0b5f HC	217	unsigned long *addr = __bitops_word(nr, ptr);
370b0b5f HC	218	unsigned long old, mask;
1da177e4	219
01c2475f	220	mask = ~(1UL << (nr & (BITS_PER_LONG - 1)));
e344e52c	221	old = __BITOPS_LOOP(addr, mask, __BITOPS_AND);
5294ee00	222	barrier();
e344e52c	223	return (old & ~mask) != 0;
1da177e4 LT	224	}
1da177e4 LT	225
1da177e4	226	static inline int
370b0b5f	227	test_and_change_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	228	{
370b0b5f HC	229	unsigned long *addr = __bitops_word(nr, ptr);
370b0b5f HC	230	unsigned long old, mask;
1da177e4	231
01c2475f	232	mask = 1UL << (nr & (BITS_PER_LONG - 1));
e344e52c	233	old = __BITOPS_LOOP(addr, mask, __BITOPS_XOR);
5294ee00	234	barrier();
1da177e4 LT	235	return (old & mask) != 0;
1da177e4 LT	236	}
1da177e4	237
1da177e4 LT	238	static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4 LT	239	{
370b0b5f	240	unsigned char *addr = __bitops_byte(nr, ptr);
1da177e4	241
370b0b5f	242	*addr \|= 1 << (nr & 7);
1da177e4 LT	243	}
1da177e4 LT	244
1da177e4 LT	245	static inline void
	246	__clear_bit(unsigned long nr, volatile unsigned long *ptr)
	247	{
370b0b5f	248	unsigned char *addr = __bitops_byte(nr, ptr);
1da177e4	249
370b0b5f	250	*addr &= ~(1 << (nr & 7));
1da177e4 LT	251	}
1da177e4 LT	252
1da177e4 LT	253	static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4 LT	254	{
370b0b5f	255	unsigned char *addr = __bitops_byte(nr, ptr);
1da177e4	256
370b0b5f	257	*addr ^= 1 << (nr & 7);
1da177e4 LT	258	}
1da177e4 LT	259
1da177e4	260	static inline int
370b0b5f	261	__test_and_set_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	262	{
370b0b5f	263	unsigned char *addr = __bitops_byte(nr, ptr);
1da177e4 LT	264	unsigned char ch;
1da177e4 LT	265
370b0b5f HC	266	ch = *addr;
370b0b5f HC	267	*addr \|= 1 << (nr & 7);
1da177e4 LT	268	return (ch >> (nr & 7)) & 1;
1da177e4 LT	269	}
1da177e4	270
1da177e4	271	static inline int
370b0b5f	272	__test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	273	{
370b0b5f	274	unsigned char *addr = __bitops_byte(nr, ptr);
1da177e4 LT	275	unsigned char ch;
1da177e4 LT	276
370b0b5f HC	277	ch = *addr;
370b0b5f HC	278	*addr &= ~(1 << (nr & 7));
1da177e4 LT	279	return (ch >> (nr & 7)) & 1;
1da177e4 LT	280	}
1da177e4	281
1da177e4	282	static inline int
370b0b5f	283	__test_and_change_bit(unsigned long nr, volatile unsigned long *ptr)
1da177e4	284	{
370b0b5f	285	unsigned char *addr = __bitops_byte(nr, ptr);
1da177e4 LT	286	unsigned char ch;
1da177e4 LT	287
370b0b5f HC	288	ch = *addr;
370b0b5f HC	289	*addr ^= 1 << (nr & 7);
1da177e4 LT	290	return (ch >> (nr & 7)) & 1;
1da177e4 LT	291	}
1da177e4	292
370b0b5f	293	static inline int test_bit(unsigned long nr, const volatile unsigned long *ptr)
1da177e4	294	{
370b0b5f	295	const volatile unsigned char *addr;
1da177e4	296
370b0b5f HC	297	addr = ((const volatile unsigned char *)ptr);
	298	addr += (nr ^ (BITS_PER_LONG - 8)) >> 3;
	299	return (*addr >> (nr & 7)) & 1;
1da177e4 LT	300	}
1da177e4 LT	301
afff7e2b	302	/*
746479cd HC	303	* ATTENTION:
746479cd HC	304	* find_first_bit_left() and find_next_bit_left() use MSB0 encoding.
e56e4e87	305	*/
746479cd HC	306	unsigned long find_first_bit_left(const unsigned long *addr, unsigned long size);
	307	unsigned long find_next_bit_left(const unsigned long *addr, unsigned long size,
	308	unsigned long offset);
e56e4e87	309
746479cd HC	310	#include <asm-generic/bitops/__ffs.h>
746479cd HC	311	#include <asm-generic/bitops/ffs.h>
56a6b1eb	312	#include <asm-generic/bitops/__fls.h>
746479cd	313	#include <asm-generic/bitops/fls.h>
7e33db4e	314	#include <asm-generic/bitops/fls64.h>
746479cd HC	315	#include <asm-generic/bitops/ffz.h>
746479cd HC	316	#include <asm-generic/bitops/find.h>
7e33db4e	317	#include <asm-generic/bitops/hweight.h>
26333576	318	#include <asm-generic/bitops/lock.h>
746479cd	319	#include <asm-generic/bitops/sched.h>
802caabb	320	#include <asm-generic/bitops/le.h>
148817ba	321	#include <asm-generic/bitops/ext2-atomic-setbit.h>
67fe9251	322
1da177e4	323	#endif /* _S390_BITOPS_H */