[deliverable/linux.git] / arch / s390 / include / asm / mmu_context.h

/*
 *  S390 version
 *
 *  Derived from "include/asm-i386/mmu_context.h"
 */

#ifndef __S390_MMU_CONTEXT_H
#define __S390_MMU_CONTEXT_H

#include <asm/pgalloc.h>
#include <asm/uaccess.h>
#include <asm/tlbflush.h>
#include <asm/ctl_reg.h>

static inline int init_new_context(struct task_struct *tsk,
				   struct mm_struct *mm)
{
	spin_lock_init(&mm->context.pgtable_lock);
	INIT_LIST_HEAD(&mm->context.pgtable_list);
	spin_lock_init(&mm->context.gmap_lock);
	INIT_LIST_HEAD(&mm->context.gmap_list);
	cpumask_clear(&mm->context.cpu_attach_mask);
	atomic_set(&mm->context.flush_count, 0);
	mm->context.flush_mm = 0;
#ifdef CONFIG_PGSTE
	mm->context.alloc_pgste = page_table_allocate_pgste;
	mm->context.has_pgste = 0;
	mm->context.use_skey = 0;
#endif
	switch (mm->context.asce_limit) {
	case 1UL << 42:
		/*
		 * forked 3-level task, fall through to set new asce with new
		 * mm->pgd
		 */
	case 0:
		/* context created by exec, set asce limit to 4TB */
		mm->context.asce_limit = STACK_TOP_MAX;
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_REGION3;
		break;
	case 1UL << 53:
		/* forked 4-level task, set new asce with new mm->pgd */
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_REGION2;
		break;
	case 1UL << 31:
		/* forked 2-level compat task, set new asce with new mm->pgd */
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
		/* pgd_alloc() did not increase mm->nr_pmds */
		mm_inc_nr_pmds(mm);
	}
	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
	return 0;
}

#define destroy_context(mm)             do { } while (0)

static inline void set_user_asce(struct mm_struct *mm)
{
	S390_lowcore.user_asce = mm->context.asce;
	if (current->thread.mm_segment.ar4)
		__ctl_load(S390_lowcore.user_asce, 7, 7);
	set_cpu_flag(CIF_ASCE);
}

static inline void clear_user_asce(void)
{
	S390_lowcore.user_asce = S390_lowcore.kernel_asce;

	__ctl_load(S390_lowcore.user_asce, 1, 1);
	__ctl_load(S390_lowcore.user_asce, 7, 7);
}

static inline void load_kernel_asce(void)
{
	unsigned long asce;

	__ctl_store(asce, 1, 1);
	if (asce != S390_lowcore.kernel_asce)
		__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	set_cpu_flag(CIF_ASCE);
}

static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	int cpu = smp_processor_id();

	S390_lowcore.user_asce = next->context.asce;
	if (prev == next)
		return;
	cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
	cpumask_set_cpu(cpu, mm_cpumask(next));
	/* Clear old ASCE by loading the kernel ASCE. */
	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	__ctl_load(S390_lowcore.kernel_asce, 7, 7);
	cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
}

#define finish_arch_post_lock_switch finish_arch_post_lock_switch
static inline void finish_arch_post_lock_switch(void)
{
	struct task_struct *tsk = current;
	struct mm_struct *mm = tsk->mm;

	load_kernel_asce();
	if (mm) {
		preempt_disable();
		while (atomic_read(&mm->context.flush_count))
			cpu_relax();

		if (mm->context.flush_mm)
			__tlb_flush_mm(mm);
		preempt_enable();
	}
	set_fs(current->thread.mm_segment);
}

#define enter_lazy_tlb(mm,tsk)	do { } while (0)
#define deactivate_mm(tsk,mm)	do { } while (0)

static inline void activate_mm(struct mm_struct *prev,
                               struct mm_struct *next)
{
	switch_mm(prev, next, current);
	set_user_asce(next);
}

static inline void arch_dup_mmap(struct mm_struct *oldmm,
				 struct mm_struct *mm)
{
}

static inline void arch_exit_mmap(struct mm_struct *mm)
{
}

static inline void arch_unmap(struct mm_struct *mm,
			struct vm_area_struct *vma,
			unsigned long start, unsigned long end)
{
}

static inline void arch_bprm_mm_init(struct mm_struct *mm,
				     struct vm_area_struct *vma)
{
}

static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
		bool write, bool execute, bool foreign)
{
	/* by default, allow everything */
	return true;
}

static inline bool arch_pte_access_permitted(pte_t pte, bool write)
{
	/* by default, allow everything */
	return true;
}
#endif /* __S390_MMU_CONTEXT_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* S390 version
	3	*
	4	* Derived from "include/asm-i386/mmu_context.h"
	5	*/
	6
	7	#ifndef __S390_MMU_CONTEXT_H
	8	#define __S390_MMU_CONTEXT_H
	9
c1821c2e	10	#include <asm/pgalloc.h>
146e4b3c	11	#include <asm/uaccess.h>
050eef36	12	#include <asm/tlbflush.h>
a0616cde	13	#include <asm/ctl_reg.h>
d6dd61c8	14
6f457e1a MS	15	static inline int init_new_context(struct task_struct *tsk,
	16	struct mm_struct *mm)
	17	{
8ecb1a59	18	spin_lock_init(&mm->context.pgtable_lock);
3446c13b	19	INIT_LIST_HEAD(&mm->context.pgtable_list);
8ecb1a59	20	spin_lock_init(&mm->context.gmap_lock);
3446c13b	21	INIT_LIST_HEAD(&mm->context.gmap_list);
1b948d6c	22	cpumask_clear(&mm->context.cpu_attach_mask);
64f31d58	23	atomic_set(&mm->context.flush_count, 0);
050eef36	24	mm->context.flush_mm = 0;
0b46e0a3 MS	25	#ifdef CONFIG_PGSTE
0b46e0a3 MS	26	mm->context.alloc_pgste = page_table_allocate_pgste;
3eabaee9	27	mm->context.has_pgste = 0;
693ffc08	28	mm->context.use_skey = 0;
0b46e0a3	29	#endif
723cacbd GS	30	switch (mm->context.asce_limit) {
	31	case 1UL << 42:
	32	/*
	33	* forked 3-level task, fall through to set new asce with new
	34	* mm->pgd
	35	*/
	36	case 0:
3446c13b	37	/* context created by exec, set asce limit to 4TB */
3446c13b	38	mm->context.asce_limit = STACK_TOP_MAX;
723cacbd GS	39	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	40	_ASCE_USER_BITS \| _ASCE_TYPE_REGION3;
	41	break;
	42	case 1UL << 53:
	43	/* forked 4-level task, set new asce with new mm->pgd */
	44	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	45	_ASCE_USER_BITS \| _ASCE_TYPE_REGION2;
	46	break;
	47	case 1UL << 31:
	48	/* forked 2-level compat task, set new asce with new mm->pgd */
	49	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	50	_ASCE_USER_BITS \| _ASCE_TYPE_SEGMENT;
	51	/* pgd_alloc() did not increase mm->nr_pmds */
3446c13b MS	52	mm_inc_nr_pmds(mm);
3446c13b MS	53	}
6252d702	54	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
6f457e1a MS	55	return 0;
6f457e1a MS	56	}
1da177e4 LT	57
	58	#define destroy_context(mm) do { } while (0)
	59
beef560b	60	static inline void set_user_asce(struct mm_struct *mm)
1da177e4	61	{
723cacbd	62	S390_lowcore.user_asce = mm->context.asce;
f8b13505 MS	63	if (current->thread.mm_segment.ar4)
f8b13505 MS	64	__ctl_load(S390_lowcore.user_asce, 7, 7);
d3a73acb	65	set_cpu_flag(CIF_ASCE);
1da177e4 LT	66	}
1da177e4 LT	67
beef560b	68	static inline void clear_user_asce(void)
02a8f3ab MS	69	{
02a8f3ab MS	70	S390_lowcore.user_asce = S390_lowcore.kernel_asce;
457f2180	71
beef560b	72	__ctl_load(S390_lowcore.user_asce, 1, 1);
457f2180 HC	73	__ctl_load(S390_lowcore.user_asce, 7, 7);
	74	}
	75
beef560b	76	static inline void load_kernel_asce(void)
457f2180 HC	77	{
	78	unsigned long asce;
	79
	80	__ctl_store(asce, 1, 1);
	81	if (asce != S390_lowcore.kernel_asce)
	82	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
d3a73acb	83	set_cpu_flag(CIF_ASCE);
02a8f3ab MS	84	}
02a8f3ab MS	85
1da177e4	86	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
c1821c2e	87	struct task_struct *tsk)
1da177e4	88	{
53e857f3 MS	89	int cpu = smp_processor_id();
53e857f3 MS	90
723cacbd	91	S390_lowcore.user_asce = next->context.asce;
53e857f3 MS	92	if (prev == next)
53e857f3 MS	93	return;
64f31d58 MS	94	cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
64f31d58 MS	95	cpumask_set_cpu(cpu, mm_cpumask(next));
beef560b MS	96	/* Clear old ASCE by loading the kernel ASCE. */
	97	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	98	__ctl_load(S390_lowcore.kernel_asce, 7, 7);
64f31d58	99	cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
53e857f3 MS	100	}
	101
	102	#define finish_arch_post_lock_switch finish_arch_post_lock_switch
	103	static inline void finish_arch_post_lock_switch(void)
	104	{
	105	struct task_struct *tsk = current;
	106	struct mm_struct *mm = tsk->mm;
	107
f8b13505 MS	108	load_kernel_asce();
	109	if (mm) {
	110	preempt_disable();
64f31d58	111	while (atomic_read(&mm->context.flush_count))
f8b13505 MS	112	cpu_relax();
f8b13505 MS	113
f8b13505 MS	114	if (mm->context.flush_mm)
	115	__tlb_flush_mm(mm);
	116	preempt_enable();
	117	}
	118	set_fs(current->thread.mm_segment);
1da177e4 LT	119	}
1da177e4 LT	120
3610cce8	121	#define enter_lazy_tlb(mm,tsk) do { } while (0)
1da177e4 LT	122	#define deactivate_mm(tsk,mm) do { } while (0)
1da177e4 LT	123
4448aaf0	124	static inline void activate_mm(struct mm_struct *prev,
1da177e4 LT	125	struct mm_struct *next)
1da177e4 LT	126	{
beef560b	127	switch_mm(prev, next, current);
beef560b	128	set_user_asce(next);
1da177e4 LT	129	}
1da177e4 LT	130
0f6f281b MS	131	static inline void arch_dup_mmap(struct mm_struct *oldmm,
	132	struct mm_struct *mm)
	133	{
0f6f281b MS	134	}
	135
	136	static inline void arch_exit_mmap(struct mm_struct *mm)
	137	{
	138	}
	139
62e88b1c DH	140	static inline void arch_unmap(struct mm_struct *mm,
	141	struct vm_area_struct *vma,
	142	unsigned long start, unsigned long end)
	143	{
	144	}
	145
	146	static inline void arch_bprm_mm_init(struct mm_struct *mm,
	147	struct vm_area_struct *vma)
	148	{
	149	}
	150
1b2ee126	151	static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
d61172b4	152	bool write, bool execute, bool foreign)
33a709b2 DH	153	{
	154	/* by default, allow everything */
	155	return true;
	156	}
	157
	158	static inline bool arch_pte_access_permitted(pte_t pte, bool write)
	159	{
	160	/* by default, allow everything */
	161	return true;
	162	}
c1821c2e	163	#endif /* __S390_MMU_CONTEXT_H */