[deliverable/linux.git] / arch / s390 / include / asm / mmu_context.h

/*
 *  S390 version
 *
 *  Derived from "include/asm-i386/mmu_context.h"
 */

#ifndef __S390_MMU_CONTEXT_H
#define __S390_MMU_CONTEXT_H

#include <asm/pgalloc.h>
#include <asm/uaccess.h>
#include <asm/tlbflush.h>
#include <asm/ctl_reg.h>

static inline int init_new_context(struct task_struct *tsk,
				   struct mm_struct *mm)
{
	spin_lock_init(&mm->context.list_lock);
	INIT_LIST_HEAD(&mm->context.pgtable_list);
	INIT_LIST_HEAD(&mm->context.gmap_list);
	cpumask_clear(&mm->context.cpu_attach_mask);
	atomic_set(&mm->context.attach_count, 0);
	mm->context.flush_mm = 0;
#ifdef CONFIG_PGSTE
	mm->context.alloc_pgste = page_table_allocate_pgste;
	mm->context.has_pgste = 0;
	mm->context.use_skey = 0;
#endif
	switch (mm->context.asce_limit) {
	case 1UL << 42:
		/*
		 * forked 3-level task, fall through to set new asce with new
		 * mm->pgd
		 */
	case 0:
		/* context created by exec, set asce limit to 4TB */
		mm->context.asce_limit = STACK_TOP_MAX;
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_REGION3;
		break;
	case 1UL << 53:
		/* forked 4-level task, set new asce with new mm->pgd */
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_REGION2;
		break;
	case 1UL << 31:
		/* forked 2-level compat task, set new asce with new mm->pgd */
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
		/* pgd_alloc() did not increase mm->nr_pmds */
		mm_inc_nr_pmds(mm);
	}
	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
	return 0;
}

#define destroy_context(mm)             do { } while (0)

static inline void set_user_asce(struct mm_struct *mm)
{
	S390_lowcore.user_asce = mm->context.asce;
	if (current->thread.mm_segment.ar4)
		__ctl_load(S390_lowcore.user_asce, 7, 7);
	set_cpu_flag(CIF_ASCE);
}

static inline void clear_user_asce(void)
{
	S390_lowcore.user_asce = S390_lowcore.kernel_asce;

	__ctl_load(S390_lowcore.user_asce, 1, 1);
	__ctl_load(S390_lowcore.user_asce, 7, 7);
}

static inline void load_kernel_asce(void)
{
	unsigned long asce;

	__ctl_store(asce, 1, 1);
	if (asce != S390_lowcore.kernel_asce)
		__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	set_cpu_flag(CIF_ASCE);
}

static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	int cpu = smp_processor_id();

	S390_lowcore.user_asce = next->context.asce;
	if (prev == next)
		return;
	if (MACHINE_HAS_TLB_LC)
		cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
	/* Clear old ASCE by loading the kernel ASCE. */
	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	__ctl_load(S390_lowcore.kernel_asce, 7, 7);
	atomic_inc(&next->context.attach_count);
	atomic_dec(&prev->context.attach_count);
	if (MACHINE_HAS_TLB_LC)
		cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
}

#define finish_arch_post_lock_switch finish_arch_post_lock_switch
static inline void finish_arch_post_lock_switch(void)
{
	struct task_struct *tsk = current;
	struct mm_struct *mm = tsk->mm;

	load_kernel_asce();
	if (mm) {
		preempt_disable();
		while (atomic_read(&mm->context.attach_count) >> 16)
			cpu_relax();

		cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
		if (mm->context.flush_mm)
			__tlb_flush_mm(mm);
		preempt_enable();
	}
	set_fs(current->thread.mm_segment);
}

#define enter_lazy_tlb(mm,tsk)	do { } while (0)
#define deactivate_mm(tsk,mm)	do { } while (0)

static inline void activate_mm(struct mm_struct *prev,
                               struct mm_struct *next)
{
	switch_mm(prev, next, current);
	cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
	set_user_asce(next);
}

static inline void arch_dup_mmap(struct mm_struct *oldmm,
				 struct mm_struct *mm)
{
}

static inline void arch_exit_mmap(struct mm_struct *mm)
{
}

static inline void arch_unmap(struct mm_struct *mm,
			struct vm_area_struct *vma,
			unsigned long start, unsigned long end)
{
}

static inline void arch_bprm_mm_init(struct mm_struct *mm,
				     struct vm_area_struct *vma)
{
}

static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
		bool write, bool execute, bool foreign)
{
	/* by default, allow everything */
	return true;
}

static inline bool arch_pte_access_permitted(pte_t pte, bool write)
{
	/* by default, allow everything */
	return true;
}
#endif /* __S390_MMU_CONTEXT_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* S390 version
	3	*
	4	* Derived from "include/asm-i386/mmu_context.h"
	5	*/
	6
	7	#ifndef __S390_MMU_CONTEXT_H
	8	#define __S390_MMU_CONTEXT_H
	9
c1821c2e	10	#include <asm/pgalloc.h>
146e4b3c	11	#include <asm/uaccess.h>
050eef36	12	#include <asm/tlbflush.h>
a0616cde	13	#include <asm/ctl_reg.h>
d6dd61c8	14
6f457e1a MS	15	static inline int init_new_context(struct task_struct *tsk,
	16	struct mm_struct *mm)
	17	{
3446c13b MS	18	spin_lock_init(&mm->context.list_lock);
	19	INIT_LIST_HEAD(&mm->context.pgtable_list);
	20	INIT_LIST_HEAD(&mm->context.gmap_list);
1b948d6c	21	cpumask_clear(&mm->context.cpu_attach_mask);
050eef36 MS	22	atomic_set(&mm->context.attach_count, 0);
050eef36 MS	23	mm->context.flush_mm = 0;
0b46e0a3 MS	24	#ifdef CONFIG_PGSTE
0b46e0a3 MS	25	mm->context.alloc_pgste = page_table_allocate_pgste;
3eabaee9	26	mm->context.has_pgste = 0;
693ffc08	27	mm->context.use_skey = 0;
0b46e0a3	28	#endif
723cacbd GS	29	switch (mm->context.asce_limit) {
	30	case 1UL << 42:
	31	/*
	32	* forked 3-level task, fall through to set new asce with new
	33	* mm->pgd
	34	*/
	35	case 0:
3446c13b	36	/* context created by exec, set asce limit to 4TB */
3446c13b	37	mm->context.asce_limit = STACK_TOP_MAX;
723cacbd GS	38	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	39	_ASCE_USER_BITS \| _ASCE_TYPE_REGION3;
	40	break;
	41	case 1UL << 53:
	42	/* forked 4-level task, set new asce with new mm->pgd */
	43	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	44	_ASCE_USER_BITS \| _ASCE_TYPE_REGION2;
	45	break;
	46	case 1UL << 31:
	47	/* forked 2-level compat task, set new asce with new mm->pgd */
	48	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	49	_ASCE_USER_BITS \| _ASCE_TYPE_SEGMENT;
	50	/* pgd_alloc() did not increase mm->nr_pmds */
3446c13b MS	51	mm_inc_nr_pmds(mm);
3446c13b MS	52	}
6252d702	53	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
6f457e1a MS	54	return 0;
6f457e1a MS	55	}
1da177e4 LT	56
	57	#define destroy_context(mm) do { } while (0)
	58
beef560b	59	static inline void set_user_asce(struct mm_struct *mm)
1da177e4	60	{
723cacbd	61	S390_lowcore.user_asce = mm->context.asce;
f8b13505 MS	62	if (current->thread.mm_segment.ar4)
f8b13505 MS	63	__ctl_load(S390_lowcore.user_asce, 7, 7);
d3a73acb	64	set_cpu_flag(CIF_ASCE);
1da177e4 LT	65	}
1da177e4 LT	66
beef560b	67	static inline void clear_user_asce(void)
02a8f3ab MS	68	{
02a8f3ab MS	69	S390_lowcore.user_asce = S390_lowcore.kernel_asce;
457f2180	70
beef560b	71	__ctl_load(S390_lowcore.user_asce, 1, 1);
457f2180 HC	72	__ctl_load(S390_lowcore.user_asce, 7, 7);
	73	}
	74
beef560b	75	static inline void load_kernel_asce(void)
457f2180 HC	76	{
	77	unsigned long asce;
	78
	79	__ctl_store(asce, 1, 1);
	80	if (asce != S390_lowcore.kernel_asce)
	81	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
d3a73acb	82	set_cpu_flag(CIF_ASCE);
02a8f3ab MS	83	}
02a8f3ab MS	84
1da177e4	85	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
c1821c2e	86	struct task_struct *tsk)
1da177e4	87	{
53e857f3 MS	88	int cpu = smp_processor_id();
53e857f3 MS	89
723cacbd	90	S390_lowcore.user_asce = next->context.asce;
53e857f3 MS	91	if (prev == next)
53e857f3 MS	92	return;
1b948d6c MS	93	if (MACHINE_HAS_TLB_LC)
1b948d6c MS	94	cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
beef560b MS	95	/* Clear old ASCE by loading the kernel ASCE. */
	96	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	97	__ctl_load(S390_lowcore.kernel_asce, 7, 7);
beef560b	98	atomic_inc(&next->context.attach_count);
050eef36	99	atomic_dec(&prev->context.attach_count);
1b948d6c MS	100	if (MACHINE_HAS_TLB_LC)
1b948d6c MS	101	cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
53e857f3 MS	102	}
	103
	104	#define finish_arch_post_lock_switch finish_arch_post_lock_switch
	105	static inline void finish_arch_post_lock_switch(void)
	106	{
	107	struct task_struct *tsk = current;
	108	struct mm_struct *mm = tsk->mm;
	109
f8b13505 MS	110	load_kernel_asce();
	111	if (mm) {
	112	preempt_disable();
	113	while (atomic_read(&mm->context.attach_count) >> 16)
	114	cpu_relax();
	115
	116	cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
	117	if (mm->context.flush_mm)
	118	__tlb_flush_mm(mm);
	119	preempt_enable();
	120	}
	121	set_fs(current->thread.mm_segment);
1da177e4 LT	122	}
1da177e4 LT	123
3610cce8	124	#define enter_lazy_tlb(mm,tsk) do { } while (0)
1da177e4 LT	125	#define deactivate_mm(tsk,mm) do { } while (0)
1da177e4 LT	126
4448aaf0	127	static inline void activate_mm(struct mm_struct *prev,
1da177e4 LT	128	struct mm_struct *next)
1da177e4 LT	129	{
beef560b MS	130	switch_mm(prev, next, current);
	131	cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
	132	set_user_asce(next);
1da177e4 LT	133	}
1da177e4 LT	134
0f6f281b MS	135	static inline void arch_dup_mmap(struct mm_struct *oldmm,
	136	struct mm_struct *mm)
	137	{
0f6f281b MS	138	}
	139
	140	static inline void arch_exit_mmap(struct mm_struct *mm)
	141	{
	142	}
	143
62e88b1c DH	144	static inline void arch_unmap(struct mm_struct *mm,
	145	struct vm_area_struct *vma,
	146	unsigned long start, unsigned long end)
	147	{
	148	}
	149
	150	static inline void arch_bprm_mm_init(struct mm_struct *mm,
	151	struct vm_area_struct *vma)
	152	{
	153	}
	154
1b2ee126	155	static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
d61172b4	156	bool write, bool execute, bool foreign)
33a709b2 DH	157	{
	158	/* by default, allow everything */
	159	return true;
	160	}
	161
	162	static inline bool arch_pte_access_permitted(pte_t pte, bool write)
	163	{
	164	/* by default, allow everything */
	165	return true;
	166	}
c1821c2e	167	#endif /* __S390_MMU_CONTEXT_H */