Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999, 2000 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com) |
5 | * Ulrich Weigand (weigand@de.ibm.com) | |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
7 | * | |
8 | * Derived from "include/asm-i386/pgtable.h" | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_S390_PGTABLE_H | |
12 | #define _ASM_S390_PGTABLE_H | |
13 | ||
1da177e4 | 14 | /* |
a1c843b8 MS |
15 | * The Linux memory management assumes a three-level page table setup. |
16 | * For s390 64 bit we use up to four of the five levels the hardware | |
17 | * provides (region first tables are not used). | |
1da177e4 LT |
18 | * |
19 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
20 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
21 | * into the pgd entry) | |
22 | * | |
23 | * This file contains the functions and defines necessary to modify and use | |
24 | * the S390 page table tree. | |
25 | */ | |
26 | #ifndef __ASSEMBLY__ | |
9789db08 | 27 | #include <linux/sched.h> |
2dcea57a | 28 | #include <linux/mm_types.h> |
abf09bed | 29 | #include <linux/page-flags.h> |
527e30b4 | 30 | #include <linux/radix-tree.h> |
1da177e4 | 31 | #include <asm/bug.h> |
b2fa47e6 | 32 | #include <asm/page.h> |
1da177e4 | 33 | |
1da177e4 LT |
34 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
35 | extern void paging_init(void); | |
2b67fc46 | 36 | extern void vmem_map_init(void); |
1da177e4 LT |
37 | |
38 | /* | |
39 | * The S390 doesn't have any external MMU info: the kernel page | |
40 | * tables contain all the necessary information. | |
41 | */ | |
4b3073e1 | 42 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
b113da65 | 43 | #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) |
1da177e4 LT |
44 | |
45 | /* | |
238ec4ef | 46 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
47 | * for zero-mapped memory areas etc.. |
48 | */ | |
238ec4ef MS |
49 | |
50 | extern unsigned long empty_zero_page; | |
51 | extern unsigned long zero_page_mask; | |
52 | ||
53 | #define ZERO_PAGE(vaddr) \ | |
54 | (virt_to_page((void *)(empty_zero_page + \ | |
55 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
816422ad | 56 | #define __HAVE_COLOR_ZERO_PAGE |
238ec4ef | 57 | |
4f2e2903 | 58 | /* TODO: s390 cannot support io_remap_pfn_range... */ |
1da177e4 LT |
59 | #endif /* !__ASSEMBLY__ */ |
60 | ||
61 | /* | |
62 | * PMD_SHIFT determines the size of the area a second-level page | |
63 | * table can map | |
64 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
65 | */ | |
5a79859a HC |
66 | #define PMD_SHIFT 20 |
67 | #define PUD_SHIFT 31 | |
68 | #define PGDIR_SHIFT 42 | |
1da177e4 LT |
69 | |
70 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
71 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
72 | #define PUD_SIZE (1UL << PUD_SHIFT) |
73 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
74 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
75 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
76 | |
77 | /* | |
78 | * entries per page directory level: the S390 is two-level, so | |
79 | * we don't really have any PMD directory physically. | |
80 | * for S390 segment-table entries are combined to one PGD | |
81 | * that leads to 1024 pte per pgd | |
82 | */ | |
146e4b3c | 83 | #define PTRS_PER_PTE 256 |
146e4b3c | 84 | #define PTRS_PER_PMD 2048 |
5a216a20 | 85 | #define PTRS_PER_PUD 2048 |
146e4b3c | 86 | #define PTRS_PER_PGD 2048 |
1da177e4 | 87 | |
d016bf7e | 88 | #define FIRST_USER_ADDRESS 0UL |
d455a369 | 89 | |
1da177e4 LT |
90 | #define pte_ERROR(e) \ |
91 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
92 | #define pmd_ERROR(e) \ | |
93 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
94 | #define pud_ERROR(e) \ |
95 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
96 | #define pgd_ERROR(e) \ |
97 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
98 | ||
99 | #ifndef __ASSEMBLY__ | |
100 | /* | |
a1c843b8 MS |
101 | * The vmalloc and module area will always be on the topmost area of the |
102 | * kernel mapping. We reserve 128GB (64bit) for vmalloc and modules. | |
c972cc60 HC |
103 | * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where |
104 | * modules will reside. That makes sure that inter module branches always | |
105 | * happen without trampolines and in addition the placement within a 2GB frame | |
106 | * is branch prediction unit friendly. | |
8b62bc96 | 107 | */ |
239a6425 | 108 | extern unsigned long VMALLOC_START; |
14045ebf MS |
109 | extern unsigned long VMALLOC_END; |
110 | extern struct page *vmemmap; | |
239a6425 | 111 | |
14045ebf | 112 | #define VMEM_MAX_PHYS ((unsigned long) vmemmap) |
5fd9c6e2 | 113 | |
c972cc60 HC |
114 | extern unsigned long MODULES_VADDR; |
115 | extern unsigned long MODULES_END; | |
116 | #define MODULES_VADDR MODULES_VADDR | |
117 | #define MODULES_END MODULES_END | |
118 | #define MODULES_LEN (1UL << 31) | |
c972cc60 | 119 | |
c933146a HC |
120 | static inline int is_module_addr(void *addr) |
121 | { | |
c933146a HC |
122 | BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); |
123 | if (addr < (void *)MODULES_VADDR) | |
124 | return 0; | |
125 | if (addr > (void *)MODULES_END) | |
126 | return 0; | |
c933146a HC |
127 | return 1; |
128 | } | |
129 | ||
1da177e4 | 130 | /* |
1da177e4 | 131 | * A 64 bit pagetable entry of S390 has following format: |
6a985c61 | 132 | * | PFRA |0IPC| OS | |
1da177e4 LT |
133 | * 0000000000111111111122222222223333333333444444444455555555556666 |
134 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
135 | * | |
136 | * I Page-Invalid Bit: Page is not available for address-translation | |
137 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 138 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
139 | * |
140 | * A 64 bit segmenttable entry of S390 has following format: | |
141 | * | P-table origin | TT | |
142 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
143 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
144 | * | |
145 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
146 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
147 | * P Page-Protection Bit: Store access not possible for page | |
148 | * TT Type 00 | |
149 | * | |
150 | * A 64 bit region table entry of S390 has following format: | |
151 | * | S-table origin | TF TTTL | |
152 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
153 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
154 | * | |
155 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
156 | * TT Type 01 | |
157 | * TF | |
190a1d72 | 158 | * TL Table length |
1da177e4 LT |
159 | * |
160 | * The 64 bit regiontable origin of S390 has following format: | |
161 | * | region table origon | DTTL | |
162 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
163 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
164 | * | |
165 | * X Space-Switch event: | |
166 | * G Segment-Invalid Bit: | |
167 | * P Private-Space Bit: | |
168 | * S Storage-Alteration: | |
169 | * R Real space | |
170 | * TL Table-Length: | |
171 | * | |
172 | * A storage key has the following format: | |
173 | * | ACC |F|R|C|0| | |
174 | * 0 3 4 5 6 7 | |
175 | * ACC: access key | |
176 | * F : fetch protection bit | |
177 | * R : referenced bit | |
178 | * C : changed bit | |
179 | */ | |
180 | ||
181 | /* Hardware bits in the page table entry */ | |
e5098611 | 182 | #define _PAGE_PROTECT 0x200 /* HW read-only bit */ |
83377484 | 183 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ |
e5098611 | 184 | #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ |
3610cce8 MS |
185 | |
186 | /* Software bits in the page table entry */ | |
e5098611 | 187 | #define _PAGE_PRESENT 0x001 /* SW pte present bit */ |
e5098611 MS |
188 | #define _PAGE_YOUNG 0x004 /* SW pte young bit */ |
189 | #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ | |
0944fe3f MS |
190 | #define _PAGE_READ 0x010 /* SW pte read bit */ |
191 | #define _PAGE_WRITE 0x020 /* SW pte write bit */ | |
192 | #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ | |
b31288fa | 193 | #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ |
a08cb629 | 194 | #define __HAVE_ARCH_PTE_SPECIAL |
1da177e4 | 195 | |
5614dd92 MS |
196 | #ifdef CONFIG_MEM_SOFT_DIRTY |
197 | #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ | |
198 | #else | |
199 | #define _PAGE_SOFT_DIRTY 0x000 | |
200 | #endif | |
201 | ||
138c9021 | 202 | /* Set of bits not changed in pte_modify */ |
6a5c1482 | 203 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ |
5614dd92 | 204 | _PAGE_YOUNG | _PAGE_SOFT_DIRTY) |
53492b1d | 205 | |
83377484 | 206 | /* |
6e76d4b2 KS |
207 | * handle_pte_fault uses pte_present and pte_none to find out the pte type |
208 | * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to | |
209 | * distinguish present from not-present ptes. It is changed only with the page | |
210 | * table lock held. | |
83377484 | 211 | * |
e5098611 | 212 | * The following table gives the different possible bit combinations for |
a1c843b8 MS |
213 | * the pte hardware and software bits in the last 12 bits of a pte |
214 | * (. unassigned bit, x don't care, t swap type): | |
83377484 | 215 | * |
0944fe3f MS |
216 | * 842100000000 |
217 | * 000084210000 | |
218 | * 000000008421 | |
a1c843b8 MS |
219 | * .IR.uswrdy.p |
220 | * empty .10.00000000 | |
221 | * swap .11..ttttt.0 | |
222 | * prot-none, clean, old .11.xx0000.1 | |
223 | * prot-none, clean, young .11.xx0001.1 | |
224 | * prot-none, dirty, old .10.xx0010.1 | |
225 | * prot-none, dirty, young .10.xx0011.1 | |
226 | * read-only, clean, old .11.xx0100.1 | |
227 | * read-only, clean, young .01.xx0101.1 | |
228 | * read-only, dirty, old .11.xx0110.1 | |
229 | * read-only, dirty, young .01.xx0111.1 | |
230 | * read-write, clean, old .11.xx1100.1 | |
231 | * read-write, clean, young .01.xx1101.1 | |
232 | * read-write, dirty, old .10.xx1110.1 | |
233 | * read-write, dirty, young .00.xx1111.1 | |
234 | * HW-bits: R read-only, I invalid | |
235 | * SW-bits: p present, y young, d dirty, r read, w write, s special, | |
236 | * u unused, l large | |
e5098611 | 237 | * |
a1c843b8 MS |
238 | * pte_none is true for the bit pattern .10.00000000, pte == 0x400 |
239 | * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 | |
240 | * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 | |
83377484 MS |
241 | */ |
242 | ||
3610cce8 MS |
243 | /* Bits in the segment/region table address-space-control-element */ |
244 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
245 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
246 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
247 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
248 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
249 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
250 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
251 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
252 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
253 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
254 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
255 | ||
256 | /* Bits in the region table entry */ | |
257 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
e5098611 MS |
258 | #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ |
259 | #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ | |
3610cce8 MS |
260 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ |
261 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
262 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
263 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
264 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
265 | ||
266 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
e5098611 | 267 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) |
3610cce8 | 268 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) |
e5098611 | 269 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) |
3610cce8 | 270 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) |
e5098611 | 271 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) |
3610cce8 | 272 | |
18da2369 | 273 | #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ |
1819ed1f | 274 | #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ |
18da2369 | 275 | |
1da177e4 | 276 | /* Bits in the segment table entry */ |
0944fe3f | 277 | #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL |
152125b7 | 278 | #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL |
ea81531d | 279 | #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ |
3610cce8 | 280 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
e5098611 MS |
281 | #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ |
282 | #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ | |
1da177e4 | 283 | |
3610cce8 | 284 | #define _SEGMENT_ENTRY (0) |
e5098611 | 285 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) |
3610cce8 | 286 | |
152125b7 MS |
287 | #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ |
288 | #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ | |
289 | #define _SEGMENT_ENTRY_SPLIT 0x0800 /* THP splitting bit */ | |
290 | #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ | |
152125b7 MS |
291 | #define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */ |
292 | #define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */ | |
0944fe3f | 293 | |
5614dd92 MS |
294 | #ifdef CONFIG_MEM_SOFT_DIRTY |
295 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ | |
296 | #else | |
297 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ | |
298 | #endif | |
299 | ||
0944fe3f MS |
300 | /* |
301 | * Segment table entry encoding (R = read-only, I = invalid, y = young bit): | |
152125b7 MS |
302 | * dy..R...I...wr |
303 | * prot-none, clean, old 00..1...1...00 | |
304 | * prot-none, clean, young 01..1...1...00 | |
305 | * prot-none, dirty, old 10..1...1...00 | |
306 | * prot-none, dirty, young 11..1...1...00 | |
307 | * read-only, clean, old 00..1...1...01 | |
308 | * read-only, clean, young 01..1...0...01 | |
309 | * read-only, dirty, old 10..1...1...01 | |
310 | * read-only, dirty, young 11..1...0...01 | |
311 | * read-write, clean, old 00..1...1...11 | |
312 | * read-write, clean, young 01..1...0...11 | |
313 | * read-write, dirty, old 10..0...1...11 | |
314 | * read-write, dirty, young 11..0...0...11 | |
0944fe3f MS |
315 | * The segment table origin is used to distinguish empty (origin==0) from |
316 | * read-write, old segment table entries (origin!=0) | |
a1c843b8 MS |
317 | * HW-bits: R read-only, I invalid |
318 | * SW-bits: y young, d dirty, r read, w write | |
0944fe3f | 319 | */ |
e5098611 | 320 | |
152125b7 | 321 | #define _SEGMENT_ENTRY_SPLIT_BIT 11 /* THP splitting bit number */ |
1ae1c1d0 | 322 | |
6c61cfe9 | 323 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
324 | #define PGSTE_ACC_BITS 0xf000000000000000UL |
325 | #define PGSTE_FP_BIT 0x0800000000000000UL | |
326 | #define PGSTE_PCL_BIT 0x0080000000000000UL | |
327 | #define PGSTE_HR_BIT 0x0040000000000000UL | |
328 | #define PGSTE_HC_BIT 0x0020000000000000UL | |
329 | #define PGSTE_GR_BIT 0x0004000000000000UL | |
330 | #define PGSTE_GC_BIT 0x0002000000000000UL | |
0a61b222 MS |
331 | #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ |
332 | #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ | |
6c61cfe9 | 333 | |
b31288fa KW |
334 | /* Guest Page State used for virtualization */ |
335 | #define _PGSTE_GPS_ZERO 0x0000000080000000UL | |
336 | #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL | |
337 | #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL | |
338 | #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL | |
339 | ||
1da177e4 | 340 | /* |
3610cce8 MS |
341 | * A user page table pointer has the space-switch-event bit, the |
342 | * private-space-control bit and the storage-alteration-event-control | |
343 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 344 | */ |
3610cce8 MS |
345 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
346 | _ASCE_ALT_EVENT) | |
1da177e4 | 347 | |
1da177e4 | 348 | /* |
9282ed92 | 349 | * Page protection definitions. |
1da177e4 | 350 | */ |
e5098611 | 351 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID) |
0944fe3f MS |
352 | #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \ |
353 | _PAGE_INVALID | _PAGE_PROTECT) | |
354 | #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
355 | _PAGE_INVALID | _PAGE_PROTECT) | |
356 | ||
357 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
358 | _PAGE_YOUNG | _PAGE_DIRTY) | |
359 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
360 | _PAGE_YOUNG | _PAGE_DIRTY) | |
361 | #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ | |
362 | _PAGE_PROTECT) | |
1da177e4 LT |
363 | |
364 | /* | |
043d0708 MS |
365 | * On s390 the page table entry has an invalid bit and a read-only bit. |
366 | * Read permission implies execute permission and write permission | |
367 | * implies read permission. | |
1da177e4 LT |
368 | */ |
369 | /*xwr*/ | |
9282ed92 | 370 | #define __P000 PAGE_NONE |
e5098611 MS |
371 | #define __P001 PAGE_READ |
372 | #define __P010 PAGE_READ | |
373 | #define __P011 PAGE_READ | |
374 | #define __P100 PAGE_READ | |
375 | #define __P101 PAGE_READ | |
376 | #define __P110 PAGE_READ | |
377 | #define __P111 PAGE_READ | |
9282ed92 GS |
378 | |
379 | #define __S000 PAGE_NONE | |
e5098611 MS |
380 | #define __S001 PAGE_READ |
381 | #define __S010 PAGE_WRITE | |
382 | #define __S011 PAGE_WRITE | |
383 | #define __S100 PAGE_READ | |
384 | #define __S101 PAGE_READ | |
385 | #define __S110 PAGE_WRITE | |
386 | #define __S111 PAGE_WRITE | |
1da177e4 | 387 | |
106c992a GS |
388 | /* |
389 | * Segment entry (large page) protection definitions. | |
390 | */ | |
e5098611 MS |
391 | #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ |
392 | _SEGMENT_ENTRY_PROTECT) | |
152125b7 MS |
393 | #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \ |
394 | _SEGMENT_ENTRY_READ) | |
395 | #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \ | |
396 | _SEGMENT_ENTRY_WRITE) | |
106c992a | 397 | |
b2fa47e6 MS |
398 | static inline int mm_has_pgste(struct mm_struct *mm) |
399 | { | |
400 | #ifdef CONFIG_PGSTE | |
401 | if (unlikely(mm->context.has_pgste)) | |
402 | return 1; | |
403 | #endif | |
404 | return 0; | |
405 | } | |
65eef335 | 406 | |
0b46e0a3 MS |
407 | static inline int mm_alloc_pgste(struct mm_struct *mm) |
408 | { | |
409 | #ifdef CONFIG_PGSTE | |
410 | if (unlikely(mm->context.alloc_pgste)) | |
411 | return 1; | |
412 | #endif | |
413 | return 0; | |
414 | } | |
415 | ||
2faee8ff DD |
416 | /* |
417 | * In the case that a guest uses storage keys | |
418 | * faults should no longer be backed by zero pages | |
419 | */ | |
420 | #define mm_forbids_zeropage mm_use_skey | |
65eef335 DD |
421 | static inline int mm_use_skey(struct mm_struct *mm) |
422 | { | |
423 | #ifdef CONFIG_PGSTE | |
424 | if (mm->context.use_skey) | |
425 | return 1; | |
426 | #endif | |
427 | return 0; | |
428 | } | |
429 | ||
1da177e4 LT |
430 | /* |
431 | * pgd/pmd/pte query functions | |
432 | */ | |
5a216a20 MS |
433 | static inline int pgd_present(pgd_t pgd) |
434 | { | |
6252d702 MS |
435 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
436 | return 1; | |
5a216a20 MS |
437 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
438 | } | |
439 | ||
440 | static inline int pgd_none(pgd_t pgd) | |
441 | { | |
6252d702 MS |
442 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
443 | return 0; | |
e5098611 | 444 | return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; |
5a216a20 MS |
445 | } |
446 | ||
447 | static inline int pgd_bad(pgd_t pgd) | |
448 | { | |
6252d702 MS |
449 | /* |
450 | * With dynamic page table levels the pgd can be a region table | |
451 | * entry or a segment table entry. Check for the bit that are | |
452 | * invalid for either table entry. | |
453 | */ | |
5a216a20 | 454 | unsigned long mask = |
e5098611 | 455 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
456 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
457 | return (pgd_val(pgd) & mask) != 0; | |
458 | } | |
190a1d72 MS |
459 | |
460 | static inline int pud_present(pud_t pud) | |
1da177e4 | 461 | { |
6252d702 MS |
462 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
463 | return 1; | |
0d017923 | 464 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
465 | } |
466 | ||
190a1d72 | 467 | static inline int pud_none(pud_t pud) |
1da177e4 | 468 | { |
6252d702 MS |
469 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
470 | return 0; | |
e5098611 | 471 | return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL; |
1da177e4 LT |
472 | } |
473 | ||
18da2369 HC |
474 | static inline int pud_large(pud_t pud) |
475 | { | |
476 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) | |
477 | return 0; | |
478 | return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); | |
479 | } | |
480 | ||
190a1d72 | 481 | static inline int pud_bad(pud_t pud) |
1da177e4 | 482 | { |
6252d702 MS |
483 | /* |
484 | * With dynamic page table levels the pud can be a region table | |
485 | * entry or a segment table entry. Check for the bit that are | |
486 | * invalid for either table entry. | |
487 | */ | |
5a216a20 | 488 | unsigned long mask = |
e5098611 | 489 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
490 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
491 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
492 | } |
493 | ||
4448aaf0 | 494 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 495 | { |
e5098611 | 496 | return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
497 | } |
498 | ||
4448aaf0 | 499 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 500 | { |
e5098611 | 501 | return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
502 | } |
503 | ||
378b1e7a HC |
504 | static inline int pmd_large(pmd_t pmd) |
505 | { | |
e5098611 | 506 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; |
378b1e7a HC |
507 | } |
508 | ||
7cded342 | 509 | static inline unsigned long pmd_pfn(pmd_t pmd) |
0944fe3f | 510 | { |
152125b7 MS |
511 | unsigned long origin_mask; |
512 | ||
513 | origin_mask = _SEGMENT_ENTRY_ORIGIN; | |
514 | if (pmd_large(pmd)) | |
515 | origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; | |
516 | return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT; | |
0944fe3f MS |
517 | } |
518 | ||
4448aaf0 | 519 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 520 | { |
0944fe3f MS |
521 | if (pmd_large(pmd)) |
522 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; | |
0944fe3f | 523 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; |
1da177e4 LT |
524 | } |
525 | ||
75077afb GS |
526 | #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH |
527 | extern void pmdp_splitting_flush(struct vm_area_struct *vma, | |
528 | unsigned long addr, pmd_t *pmdp); | |
529 | ||
1ae1c1d0 GS |
530 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
531 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
532 | unsigned long address, pmd_t *pmdp, | |
533 | pmd_t entry, int dirty); | |
534 | ||
535 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
536 | extern int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
537 | unsigned long address, pmd_t *pmdp); | |
538 | ||
539 | #define __HAVE_ARCH_PMD_WRITE | |
540 | static inline int pmd_write(pmd_t pmd) | |
541 | { | |
152125b7 MS |
542 | return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; |
543 | } | |
544 | ||
545 | static inline int pmd_dirty(pmd_t pmd) | |
546 | { | |
547 | int dirty = 1; | |
548 | if (pmd_large(pmd)) | |
549 | dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; | |
550 | return dirty; | |
1ae1c1d0 GS |
551 | } |
552 | ||
553 | static inline int pmd_young(pmd_t pmd) | |
554 | { | |
152125b7 MS |
555 | int young = 1; |
556 | if (pmd_large(pmd)) | |
0944fe3f | 557 | young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; |
0944fe3f | 558 | return young; |
1ae1c1d0 GS |
559 | } |
560 | ||
e5098611 | 561 | static inline int pte_present(pte_t pte) |
1da177e4 | 562 | { |
e5098611 MS |
563 | /* Bit pattern: (pte & 0x001) == 0x001 */ |
564 | return (pte_val(pte) & _PAGE_PRESENT) != 0; | |
1da177e4 LT |
565 | } |
566 | ||
e5098611 | 567 | static inline int pte_none(pte_t pte) |
1da177e4 | 568 | { |
e5098611 MS |
569 | /* Bit pattern: pte == 0x400 */ |
570 | return pte_val(pte) == _PAGE_INVALID; | |
1da177e4 LT |
571 | } |
572 | ||
b31288fa KW |
573 | static inline int pte_swap(pte_t pte) |
574 | { | |
a1c843b8 MS |
575 | /* Bit pattern: (pte & 0x201) == 0x200 */ |
576 | return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) | |
577 | == _PAGE_PROTECT; | |
b31288fa KW |
578 | } |
579 | ||
7e675137 NP |
580 | static inline int pte_special(pte_t pte) |
581 | { | |
a08cb629 | 582 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
583 | } |
584 | ||
ba8a9229 | 585 | #define __HAVE_ARCH_PTE_SAME |
b2fa47e6 MS |
586 | static inline int pte_same(pte_t a, pte_t b) |
587 | { | |
588 | return pte_val(a) == pte_val(b); | |
589 | } | |
1da177e4 | 590 | |
b54565b8 MS |
591 | #ifdef CONFIG_NUMA_BALANCING |
592 | static inline int pte_protnone(pte_t pte) | |
593 | { | |
594 | return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); | |
595 | } | |
596 | ||
597 | static inline int pmd_protnone(pmd_t pmd) | |
598 | { | |
599 | /* pmd_large(pmd) implies pmd_present(pmd) */ | |
600 | return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); | |
601 | } | |
602 | #endif | |
603 | ||
5614dd92 MS |
604 | static inline int pte_soft_dirty(pte_t pte) |
605 | { | |
606 | return pte_val(pte) & _PAGE_SOFT_DIRTY; | |
607 | } | |
608 | #define pte_swp_soft_dirty pte_soft_dirty | |
609 | ||
610 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
611 | { | |
612 | pte_val(pte) |= _PAGE_SOFT_DIRTY; | |
613 | return pte; | |
614 | } | |
615 | #define pte_swp_mksoft_dirty pte_mksoft_dirty | |
616 | ||
617 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
618 | { | |
619 | pte_val(pte) &= ~_PAGE_SOFT_DIRTY; | |
620 | return pte; | |
621 | } | |
622 | #define pte_swp_clear_soft_dirty pte_clear_soft_dirty | |
623 | ||
624 | static inline int pmd_soft_dirty(pmd_t pmd) | |
625 | { | |
626 | return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; | |
627 | } | |
628 | ||
629 | static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) | |
630 | { | |
631 | pmd_val(pmd) |= _SEGMENT_ENTRY_SOFT_DIRTY; | |
632 | return pmd; | |
633 | } | |
634 | ||
635 | static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) | |
636 | { | |
637 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_SOFT_DIRTY; | |
638 | return pmd; | |
639 | } | |
640 | ||
b2fa47e6 | 641 | static inline pgste_t pgste_get_lock(pte_t *ptep) |
5b7baf05 | 642 | { |
b2fa47e6 | 643 | unsigned long new = 0; |
5b7baf05 | 644 | #ifdef CONFIG_PGSTE |
b2fa47e6 MS |
645 | unsigned long old; |
646 | ||
5b7baf05 | 647 | preempt_disable(); |
b2fa47e6 MS |
648 | asm( |
649 | " lg %0,%2\n" | |
650 | "0: lgr %1,%0\n" | |
0d0dafc1 MS |
651 | " nihh %0,0xff7f\n" /* clear PCL bit in old */ |
652 | " oihh %1,0x0080\n" /* set PCL bit in new */ | |
b2fa47e6 MS |
653 | " csg %0,%1,%2\n" |
654 | " jl 0b\n" | |
655 | : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 | 656 | : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); |
5b7baf05 | 657 | #endif |
b2fa47e6 | 658 | return __pgste(new); |
5b7baf05 CB |
659 | } |
660 | ||
b2fa47e6 | 661 | static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) |
5b7baf05 CB |
662 | { |
663 | #ifdef CONFIG_PGSTE | |
b2fa47e6 | 664 | asm( |
0d0dafc1 | 665 | " nihh %1,0xff7f\n" /* clear PCL bit */ |
b2fa47e6 MS |
666 | " stg %1,%0\n" |
667 | : "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 CB |
668 | : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) |
669 | : "cc", "memory"); | |
5b7baf05 CB |
670 | preempt_enable(); |
671 | #endif | |
672 | } | |
673 | ||
d56c893d MS |
674 | static inline pgste_t pgste_get(pte_t *ptep) |
675 | { | |
676 | unsigned long pgste = 0; | |
677 | #ifdef CONFIG_PGSTE | |
678 | pgste = *(unsigned long *)(ptep + PTRS_PER_PTE); | |
679 | #endif | |
680 | return __pgste(pgste); | |
681 | } | |
682 | ||
3a82603b CB |
683 | static inline void pgste_set(pte_t *ptep, pgste_t pgste) |
684 | { | |
685 | #ifdef CONFIG_PGSTE | |
686 | *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; | |
687 | #endif | |
688 | } | |
689 | ||
65eef335 DD |
690 | static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, |
691 | struct mm_struct *mm) | |
5b7baf05 CB |
692 | { |
693 | #ifdef CONFIG_PGSTE | |
0944fe3f | 694 | unsigned long address, bits, skey; |
b2fa47e6 | 695 | |
65eef335 | 696 | if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) |
09b53883 | 697 | return pgste; |
a43a9d93 | 698 | address = pte_val(*ptep) & PAGE_MASK; |
0944fe3f | 699 | skey = (unsigned long) page_get_storage_key(address); |
b2fa47e6 | 700 | bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); |
b2fa47e6 | 701 | /* Transfer page changed & referenced bit to guest bits in pgste */ |
0d0dafc1 | 702 | pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ |
b2fa47e6 | 703 | /* Copy page access key and fetch protection bit to pgste */ |
0944fe3f MS |
704 | pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT); |
705 | pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; | |
b2fa47e6 MS |
706 | #endif |
707 | return pgste; | |
708 | ||
709 | } | |
710 | ||
65eef335 DD |
711 | static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, |
712 | struct mm_struct *mm) | |
b2fa47e6 MS |
713 | { |
714 | #ifdef CONFIG_PGSTE | |
a43a9d93 | 715 | unsigned long address; |
338679f7 | 716 | unsigned long nkey; |
b2fa47e6 | 717 | |
65eef335 | 718 | if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID) |
09b53883 | 719 | return; |
338679f7 | 720 | VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); |
09b53883 | 721 | address = pte_val(entry) & PAGE_MASK; |
338679f7 CB |
722 | /* |
723 | * Set page access key and fetch protection bit from pgste. | |
724 | * The guest C/R information is still in the PGSTE, set real | |
725 | * key C/R to 0. | |
726 | */ | |
fe489bf4 | 727 | nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; |
0a61b222 | 728 | nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48; |
338679f7 | 729 | page_set_storage_key(address, nkey, 0); |
5b7baf05 CB |
730 | #endif |
731 | } | |
732 | ||
0a61b222 | 733 | static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) |
abf09bed | 734 | { |
0a61b222 MS |
735 | if ((pte_val(entry) & _PAGE_PRESENT) && |
736 | (pte_val(entry) & _PAGE_WRITE) && | |
737 | !(pte_val(entry) & _PAGE_INVALID)) { | |
738 | if (!MACHINE_HAS_ESOP) { | |
739 | /* | |
740 | * Without enhanced suppression-on-protection force | |
741 | * the dirty bit on for all writable ptes. | |
742 | */ | |
743 | pte_val(entry) |= _PAGE_DIRTY; | |
744 | pte_val(entry) &= ~_PAGE_PROTECT; | |
745 | } | |
746 | if (!(pte_val(entry) & _PAGE_PROTECT)) | |
747 | /* This pte allows write access, set user-dirty */ | |
748 | pgste_val(pgste) |= PGSTE_UC_BIT; | |
abf09bed MS |
749 | } |
750 | *ptep = entry; | |
0a61b222 | 751 | return pgste; |
abf09bed MS |
752 | } |
753 | ||
e5992f2e MS |
754 | /** |
755 | * struct gmap_struct - guest address space | |
527e30b4 | 756 | * @crst_list: list of all crst tables used in the guest address space |
e5992f2e | 757 | * @mm: pointer to the parent mm_struct |
527e30b4 MS |
758 | * @guest_to_host: radix tree with guest to host address translation |
759 | * @host_to_guest: radix tree with pointer to segment table entries | |
760 | * @guest_table_lock: spinlock to protect all entries in the guest page table | |
e5992f2e | 761 | * @table: pointer to the page directory |
480e5926 | 762 | * @asce: address space control element for gmap page table |
24eb3a82 | 763 | * @pfault_enabled: defines if pfaults are applicable for the guest |
e5992f2e MS |
764 | */ |
765 | struct gmap { | |
766 | struct list_head list; | |
527e30b4 | 767 | struct list_head crst_list; |
e5992f2e | 768 | struct mm_struct *mm; |
527e30b4 MS |
769 | struct radix_tree_root guest_to_host; |
770 | struct radix_tree_root host_to_guest; | |
771 | spinlock_t guest_table_lock; | |
e5992f2e | 772 | unsigned long *table; |
480e5926 | 773 | unsigned long asce; |
c6c956b8 | 774 | unsigned long asce_end; |
2c70fe44 | 775 | void *private; |
24eb3a82 | 776 | bool pfault_enabled; |
e5992f2e MS |
777 | }; |
778 | ||
d3383632 MS |
779 | /** |
780 | * struct gmap_notifier - notify function block for page invalidation | |
781 | * @notifier_call: address of callback function | |
782 | */ | |
783 | struct gmap_notifier { | |
784 | struct list_head list; | |
6e0a0431 | 785 | void (*notifier_call)(struct gmap *gmap, unsigned long gaddr); |
d3383632 MS |
786 | }; |
787 | ||
c6c956b8 | 788 | struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit); |
e5992f2e MS |
789 | void gmap_free(struct gmap *gmap); |
790 | void gmap_enable(struct gmap *gmap); | |
791 | void gmap_disable(struct gmap *gmap); | |
792 | int gmap_map_segment(struct gmap *gmap, unsigned long from, | |
d3383632 | 793 | unsigned long to, unsigned long len); |
e5992f2e | 794 | int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); |
6e0a0431 MS |
795 | unsigned long __gmap_translate(struct gmap *, unsigned long gaddr); |
796 | unsigned long gmap_translate(struct gmap *, unsigned long gaddr); | |
527e30b4 MS |
797 | int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr); |
798 | int gmap_fault(struct gmap *, unsigned long gaddr, unsigned int fault_flags); | |
6e0a0431 MS |
799 | void gmap_discard(struct gmap *, unsigned long from, unsigned long to); |
800 | void __gmap_zap(struct gmap *, unsigned long gaddr); | |
a0bf4f14 DD |
801 | bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *); |
802 | ||
e5992f2e | 803 | |
d3383632 MS |
804 | void gmap_register_ipte_notifier(struct gmap_notifier *); |
805 | void gmap_unregister_ipte_notifier(struct gmap_notifier *); | |
806 | int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); | |
9da4e380 | 807 | void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *); |
d3383632 MS |
808 | |
809 | static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, | |
55dbbdd9 | 810 | unsigned long addr, |
d3383632 MS |
811 | pte_t *ptep, pgste_t pgste) |
812 | { | |
813 | #ifdef CONFIG_PGSTE | |
0d0dafc1 MS |
814 | if (pgste_val(pgste) & PGSTE_IN_BIT) { |
815 | pgste_val(pgste) &= ~PGSTE_IN_BIT; | |
9da4e380 | 816 | gmap_do_ipte_notify(mm, addr, ptep); |
d3383632 MS |
817 | } |
818 | #endif | |
819 | return pgste; | |
820 | } | |
821 | ||
b2fa47e6 MS |
822 | /* |
823 | * Certain architectures need to do special things when PTEs | |
824 | * within a page table are directly modified. Thus, the following | |
825 | * hook is made available. | |
826 | */ | |
827 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
828 | pte_t *ptep, pte_t entry) | |
829 | { | |
830 | pgste_t pgste; | |
831 | ||
832 | if (mm_has_pgste(mm)) { | |
833 | pgste = pgste_get_lock(ptep); | |
b31288fa | 834 | pgste_val(pgste) &= ~_PGSTE_GPS_ZERO; |
65eef335 | 835 | pgste_set_key(ptep, pgste, entry, mm); |
0a61b222 | 836 | pgste = pgste_set_pte(ptep, pgste, entry); |
b2fa47e6 | 837 | pgste_set_unlock(ptep, pgste); |
abf09bed | 838 | } else { |
b2fa47e6 | 839 | *ptep = entry; |
abf09bed | 840 | } |
b2fa47e6 MS |
841 | } |
842 | ||
1da177e4 LT |
843 | /* |
844 | * query functions pte_write/pte_dirty/pte_young only work if | |
845 | * pte_present() is true. Undefined behaviour if not.. | |
846 | */ | |
4448aaf0 | 847 | static inline int pte_write(pte_t pte) |
1da177e4 | 848 | { |
e5098611 | 849 | return (pte_val(pte) & _PAGE_WRITE) != 0; |
1da177e4 LT |
850 | } |
851 | ||
4448aaf0 | 852 | static inline int pte_dirty(pte_t pte) |
1da177e4 | 853 | { |
e5098611 | 854 | return (pte_val(pte) & _PAGE_DIRTY) != 0; |
1da177e4 LT |
855 | } |
856 | ||
4448aaf0 | 857 | static inline int pte_young(pte_t pte) |
1da177e4 | 858 | { |
0944fe3f | 859 | return (pte_val(pte) & _PAGE_YOUNG) != 0; |
1da177e4 LT |
860 | } |
861 | ||
b31288fa KW |
862 | #define __HAVE_ARCH_PTE_UNUSED |
863 | static inline int pte_unused(pte_t pte) | |
864 | { | |
865 | return pte_val(pte) & _PAGE_UNUSED; | |
866 | } | |
867 | ||
1da177e4 LT |
868 | /* |
869 | * pgd/pmd/pte modification functions | |
870 | */ | |
871 | ||
b2fa47e6 | 872 | static inline void pgd_clear(pgd_t *pgd) |
5a216a20 | 873 | { |
6252d702 MS |
874 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
875 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
876 | } |
877 | ||
b2fa47e6 | 878 | static inline void pud_clear(pud_t *pud) |
1da177e4 | 879 | { |
6252d702 MS |
880 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
881 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
882 | } |
883 | ||
b2fa47e6 | 884 | static inline void pmd_clear(pmd_t *pmdp) |
1da177e4 | 885 | { |
e5098611 | 886 | pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
887 | } |
888 | ||
4448aaf0 | 889 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 890 | { |
e5098611 | 891 | pte_val(*ptep) = _PAGE_INVALID; |
1da177e4 LT |
892 | } |
893 | ||
894 | /* | |
895 | * The following pte modification functions only work if | |
896 | * pte_present() is true. Undefined behaviour if not.. | |
897 | */ | |
4448aaf0 | 898 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 899 | { |
138c9021 | 900 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 | 901 | pte_val(pte) |= pgprot_val(newprot); |
0944fe3f MS |
902 | /* |
903 | * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the | |
904 | * invalid bit set, clear it again for readable, young pages | |
905 | */ | |
906 | if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) | |
907 | pte_val(pte) &= ~_PAGE_INVALID; | |
908 | /* | |
909 | * newprot for PAGE_READ and PAGE_WRITE has the page protection | |
910 | * bit set, clear it again for writable, dirty pages | |
911 | */ | |
e5098611 MS |
912 | if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) |
913 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
914 | return pte; |
915 | } | |
916 | ||
4448aaf0 | 917 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 918 | { |
e5098611 MS |
919 | pte_val(pte) &= ~_PAGE_WRITE; |
920 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
921 | return pte; |
922 | } | |
923 | ||
4448aaf0 | 924 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 | 925 | { |
e5098611 MS |
926 | pte_val(pte) |= _PAGE_WRITE; |
927 | if (pte_val(pte) & _PAGE_DIRTY) | |
928 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
929 | return pte; |
930 | } | |
931 | ||
4448aaf0 | 932 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 | 933 | { |
e5098611 MS |
934 | pte_val(pte) &= ~_PAGE_DIRTY; |
935 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
936 | return pte; |
937 | } | |
938 | ||
4448aaf0 | 939 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 | 940 | { |
5614dd92 | 941 | pte_val(pte) |= _PAGE_DIRTY | _PAGE_SOFT_DIRTY; |
e5098611 MS |
942 | if (pte_val(pte) & _PAGE_WRITE) |
943 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
944 | return pte; |
945 | } | |
946 | ||
4448aaf0 | 947 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 | 948 | { |
e5098611 | 949 | pte_val(pte) &= ~_PAGE_YOUNG; |
0944fe3f | 950 | pte_val(pte) |= _PAGE_INVALID; |
1da177e4 LT |
951 | return pte; |
952 | } | |
953 | ||
4448aaf0 | 954 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 | 955 | { |
0944fe3f MS |
956 | pte_val(pte) |= _PAGE_YOUNG; |
957 | if (pte_val(pte) & _PAGE_READ) | |
958 | pte_val(pte) &= ~_PAGE_INVALID; | |
1da177e4 LT |
959 | return pte; |
960 | } | |
961 | ||
7e675137 NP |
962 | static inline pte_t pte_mkspecial(pte_t pte) |
963 | { | |
a08cb629 | 964 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
965 | return pte; |
966 | } | |
967 | ||
84afdcee HC |
968 | #ifdef CONFIG_HUGETLB_PAGE |
969 | static inline pte_t pte_mkhuge(pte_t pte) | |
970 | { | |
e5098611 | 971 | pte_val(pte) |= _PAGE_LARGE; |
84afdcee HC |
972 | return pte; |
973 | } | |
974 | #endif | |
975 | ||
9282ed92 | 976 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 977 | { |
53e857f3 MS |
978 | unsigned long pto = (unsigned long) ptep; |
979 | ||
53e857f3 MS |
980 | /* Invalidation + global TLB flush for the pte */ |
981 | asm volatile( | |
982 | " ipte %2,%3" | |
983 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
984 | } | |
985 | ||
1b948d6c MS |
986 | static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep) |
987 | { | |
988 | unsigned long pto = (unsigned long) ptep; | |
989 | ||
1b948d6c MS |
990 | /* Invalidation + local TLB flush for the pte */ |
991 | asm volatile( | |
992 | " .insn rrf,0xb2210000,%2,%3,0,1" | |
993 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
994 | } | |
995 | ||
cfb0b241 HC |
996 | static inline void __ptep_ipte_range(unsigned long address, int nr, pte_t *ptep) |
997 | { | |
998 | unsigned long pto = (unsigned long) ptep; | |
999 | ||
cfb0b241 HC |
1000 | /* Invalidate a range of ptes + global TLB flush of the ptes */ |
1001 | do { | |
1002 | asm volatile( | |
1003 | " .insn rrf,0xb2210000,%2,%0,%1,0" | |
1004 | : "+a" (address), "+a" (nr) : "a" (pto) : "memory"); | |
1005 | } while (nr != 255); | |
1006 | } | |
1007 | ||
53e857f3 MS |
1008 | static inline void ptep_flush_direct(struct mm_struct *mm, |
1009 | unsigned long address, pte_t *ptep) | |
1010 | { | |
1b948d6c MS |
1011 | int active, count; |
1012 | ||
53e857f3 MS |
1013 | if (pte_val(*ptep) & _PAGE_INVALID) |
1014 | return; | |
1b948d6c MS |
1015 | active = (mm == current->active_mm) ? 1 : 0; |
1016 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1017 | if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && | |
1018 | cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) | |
1019 | __ptep_ipte_local(address, ptep); | |
1020 | else | |
1021 | __ptep_ipte(address, ptep); | |
1022 | atomic_sub(0x10000, &mm->context.attach_count); | |
9282ed92 GS |
1023 | } |
1024 | ||
5c474a1e MS |
1025 | static inline void ptep_flush_lazy(struct mm_struct *mm, |
1026 | unsigned long address, pte_t *ptep) | |
1027 | { | |
53e857f3 | 1028 | int active, count; |
5c474a1e | 1029 | |
53e857f3 MS |
1030 | if (pte_val(*ptep) & _PAGE_INVALID) |
1031 | return; | |
1032 | active = (mm == current->active_mm) ? 1 : 0; | |
1033 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1034 | if ((count & 0xffff) <= active) { | |
1035 | pte_val(*ptep) |= _PAGE_INVALID; | |
5c474a1e | 1036 | mm->context.flush_mm = 1; |
53e857f3 MS |
1037 | } else |
1038 | __ptep_ipte(address, ptep); | |
1039 | atomic_sub(0x10000, &mm->context.attach_count); | |
5c474a1e MS |
1040 | } |
1041 | ||
0a61b222 MS |
1042 | /* |
1043 | * Get (and clear) the user dirty bit for a pte. | |
1044 | */ | |
1045 | static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, | |
1046 | unsigned long addr, | |
1047 | pte_t *ptep) | |
1048 | { | |
1049 | pgste_t pgste; | |
1050 | pte_t pte; | |
1051 | int dirty; | |
1052 | ||
1053 | if (!mm_has_pgste(mm)) | |
1054 | return 0; | |
1055 | pgste = pgste_get_lock(ptep); | |
1056 | dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT); | |
1057 | pgste_val(pgste) &= ~PGSTE_UC_BIT; | |
1058 | pte = *ptep; | |
1059 | if (dirty && (pte_val(pte) & _PAGE_PRESENT)) { | |
55dbbdd9 | 1060 | pgste = pgste_ipte_notify(mm, addr, ptep, pgste); |
0a61b222 MS |
1061 | __ptep_ipte(addr, ptep); |
1062 | if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE)) | |
1063 | pte_val(pte) |= _PAGE_PROTECT; | |
1064 | else | |
1065 | pte_val(pte) |= _PAGE_INVALID; | |
1066 | *ptep = pte; | |
1067 | } | |
1068 | pgste_set_unlock(ptep, pgste); | |
1069 | return dirty; | |
1070 | } | |
1071 | ||
0944fe3f MS |
1072 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
1073 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
1074 | unsigned long addr, pte_t *ptep) | |
1075 | { | |
1076 | pgste_t pgste; | |
3e03d4c4 | 1077 | pte_t pte, oldpte; |
0944fe3f MS |
1078 | int young; |
1079 | ||
1080 | if (mm_has_pgste(vma->vm_mm)) { | |
1081 | pgste = pgste_get_lock(ptep); | |
55dbbdd9 | 1082 | pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste); |
0944fe3f MS |
1083 | } |
1084 | ||
3e03d4c4 | 1085 | oldpte = pte = *ptep; |
53e857f3 | 1086 | ptep_flush_direct(vma->vm_mm, addr, ptep); |
0944fe3f MS |
1087 | young = pte_young(pte); |
1088 | pte = pte_mkold(pte); | |
1089 | ||
1090 | if (mm_has_pgste(vma->vm_mm)) { | |
3e03d4c4 | 1091 | pgste = pgste_update_all(&oldpte, pgste, vma->vm_mm); |
0a61b222 | 1092 | pgste = pgste_set_pte(ptep, pgste, pte); |
0944fe3f MS |
1093 | pgste_set_unlock(ptep, pgste); |
1094 | } else | |
1095 | *ptep = pte; | |
1096 | ||
1097 | return young; | |
1098 | } | |
1099 | ||
1100 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
1101 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
1102 | unsigned long address, pte_t *ptep) | |
1103 | { | |
1104 | return ptep_test_and_clear_young(vma, address, ptep); | |
1105 | } | |
1106 | ||
ba8a9229 MS |
1107 | /* |
1108 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
1109 | * both clear the TLB for the unmapped pte. The reason is that | |
1110 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
1111 | * to modify an active pte. The sequence is | |
1112 | * 1) ptep_get_and_clear | |
1113 | * 2) set_pte_at | |
1114 | * 3) flush_tlb_range | |
1115 | * On s390 the tlb needs to get flushed with the modification of the pte | |
1116 | * if the pte is active. The only way how this can be implemented is to | |
1117 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
1118 | * is a nop. | |
1119 | */ | |
1120 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
b2fa47e6 MS |
1121 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
1122 | unsigned long address, pte_t *ptep) | |
1123 | { | |
1124 | pgste_t pgste; | |
1125 | pte_t pte; | |
1126 | ||
d3383632 | 1127 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1128 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1129 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1130 | } |
b2fa47e6 MS |
1131 | |
1132 | pte = *ptep; | |
5c474a1e | 1133 | ptep_flush_lazy(mm, address, ptep); |
e5098611 | 1134 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 MS |
1135 | |
1136 | if (mm_has_pgste(mm)) { | |
65eef335 | 1137 | pgste = pgste_update_all(&pte, pgste, mm); |
b2fa47e6 MS |
1138 | pgste_set_unlock(ptep, pgste); |
1139 | } | |
1140 | return pte; | |
1141 | } | |
1142 | ||
1143 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
1144 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, | |
1145 | unsigned long address, | |
1146 | pte_t *ptep) | |
1147 | { | |
d3383632 | 1148 | pgste_t pgste; |
b2fa47e6 MS |
1149 | pte_t pte; |
1150 | ||
d3383632 MS |
1151 | if (mm_has_pgste(mm)) { |
1152 | pgste = pgste_get_lock(ptep); | |
55dbbdd9 | 1153 | pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1154 | } |
b2fa47e6 MS |
1155 | |
1156 | pte = *ptep; | |
5c474a1e | 1157 | ptep_flush_lazy(mm, address, ptep); |
b56433cb | 1158 | |
3a82603b | 1159 | if (mm_has_pgste(mm)) { |
65eef335 | 1160 | pgste = pgste_update_all(&pte, pgste, mm); |
3a82603b CB |
1161 | pgste_set(ptep, pgste); |
1162 | } | |
b2fa47e6 MS |
1163 | return pte; |
1164 | } | |
1165 | ||
1166 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, | |
1167 | unsigned long address, | |
1168 | pte_t *ptep, pte_t pte) | |
1169 | { | |
b56433cb CB |
1170 | pgste_t pgste; |
1171 | ||
abf09bed | 1172 | if (mm_has_pgste(mm)) { |
d56c893d | 1173 | pgste = pgste_get(ptep); |
65eef335 | 1174 | pgste_set_key(ptep, pgste, pte, mm); |
0a61b222 | 1175 | pgste = pgste_set_pte(ptep, pgste, pte); |
b56433cb | 1176 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1177 | } else |
1178 | *ptep = pte; | |
b2fa47e6 | 1179 | } |
ba8a9229 MS |
1180 | |
1181 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
1182 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
1183 | unsigned long address, pte_t *ptep) | |
1184 | { | |
b2fa47e6 MS |
1185 | pgste_t pgste; |
1186 | pte_t pte; | |
1187 | ||
d3383632 | 1188 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1189 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1190 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
d3383632 | 1191 | } |
b2fa47e6 MS |
1192 | |
1193 | pte = *ptep; | |
53e857f3 | 1194 | ptep_flush_direct(vma->vm_mm, address, ptep); |
e5098611 | 1195 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 MS |
1196 | |
1197 | if (mm_has_pgste(vma->vm_mm)) { | |
b31288fa KW |
1198 | if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) == |
1199 | _PGSTE_GPS_USAGE_UNUSED) | |
1200 | pte_val(pte) |= _PAGE_UNUSED; | |
65eef335 | 1201 | pgste = pgste_update_all(&pte, pgste, vma->vm_mm); |
b2fa47e6 MS |
1202 | pgste_set_unlock(ptep, pgste); |
1203 | } | |
1da177e4 LT |
1204 | return pte; |
1205 | } | |
1206 | ||
ba8a9229 MS |
1207 | /* |
1208 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
1209 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
1210 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
1211 | * cannot be accessed while the batched unmap is running. In this case | |
1212 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
1213 | */ | |
1214 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
1215 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
b2fa47e6 | 1216 | unsigned long address, |
ba8a9229 | 1217 | pte_t *ptep, int full) |
1da177e4 | 1218 | { |
b2fa47e6 MS |
1219 | pgste_t pgste; |
1220 | pte_t pte; | |
1221 | ||
a055f66a | 1222 | if (!full && mm_has_pgste(mm)) { |
b2fa47e6 | 1223 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1224 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1225 | } |
ba8a9229 | 1226 | |
b2fa47e6 MS |
1227 | pte = *ptep; |
1228 | if (!full) | |
5c474a1e | 1229 | ptep_flush_lazy(mm, address, ptep); |
e5098611 | 1230 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 | 1231 | |
a055f66a | 1232 | if (!full && mm_has_pgste(mm)) { |
65eef335 | 1233 | pgste = pgste_update_all(&pte, pgste, mm); |
b2fa47e6 MS |
1234 | pgste_set_unlock(ptep, pgste); |
1235 | } | |
ba8a9229 | 1236 | return pte; |
1da177e4 LT |
1237 | } |
1238 | ||
ba8a9229 | 1239 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
b2fa47e6 MS |
1240 | static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, |
1241 | unsigned long address, pte_t *ptep) | |
1242 | { | |
1243 | pgste_t pgste; | |
1244 | pte_t pte = *ptep; | |
1245 | ||
1246 | if (pte_write(pte)) { | |
d3383632 | 1247 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1248 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1249 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1250 | } |
b2fa47e6 | 1251 | |
5c474a1e | 1252 | ptep_flush_lazy(mm, address, ptep); |
abf09bed | 1253 | pte = pte_wrprotect(pte); |
b2fa47e6 | 1254 | |
abf09bed | 1255 | if (mm_has_pgste(mm)) { |
0a61b222 | 1256 | pgste = pgste_set_pte(ptep, pgste, pte); |
b2fa47e6 | 1257 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1258 | } else |
1259 | *ptep = pte; | |
b2fa47e6 MS |
1260 | } |
1261 | return pte; | |
1262 | } | |
ba8a9229 MS |
1263 | |
1264 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
b2fa47e6 MS |
1265 | static inline int ptep_set_access_flags(struct vm_area_struct *vma, |
1266 | unsigned long address, pte_t *ptep, | |
1267 | pte_t entry, int dirty) | |
1268 | { | |
1269 | pgste_t pgste; | |
395e6aa1 | 1270 | pte_t oldpte; |
b2fa47e6 | 1271 | |
395e6aa1 MS |
1272 | oldpte = *ptep; |
1273 | if (pte_same(oldpte, entry)) | |
b2fa47e6 | 1274 | return 0; |
d3383632 | 1275 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1276 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1277 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
d3383632 | 1278 | } |
b2fa47e6 | 1279 | |
53e857f3 | 1280 | ptep_flush_direct(vma->vm_mm, address, ptep); |
b2fa47e6 | 1281 | |
abf09bed | 1282 | if (mm_has_pgste(vma->vm_mm)) { |
395e6aa1 MS |
1283 | if (pte_val(oldpte) & _PAGE_INVALID) |
1284 | pgste_set_key(ptep, pgste, entry, vma->vm_mm); | |
0a61b222 | 1285 | pgste = pgste_set_pte(ptep, pgste, entry); |
b2fa47e6 | 1286 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1287 | } else |
1288 | *ptep = entry; | |
b2fa47e6 MS |
1289 | return 1; |
1290 | } | |
1da177e4 | 1291 | |
1da177e4 LT |
1292 | /* |
1293 | * Conversion functions: convert a page and protection to a page entry, | |
1294 | * and a page entry and page directory to the page they refer to. | |
1295 | */ | |
1296 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1297 | { | |
1298 | pte_t __pte; | |
1299 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
0944fe3f | 1300 | return pte_mkyoung(__pte); |
1da177e4 LT |
1301 | } |
1302 | ||
2dcea57a HC |
1303 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1304 | { | |
0b2b6e1d | 1305 | unsigned long physpage = page_to_phys(page); |
abf09bed | 1306 | pte_t __pte = mk_pte_phys(physpage, pgprot); |
1da177e4 | 1307 | |
e5098611 MS |
1308 | if (pte_write(__pte) && PageDirty(page)) |
1309 | __pte = pte_mkdirty(__pte); | |
abf09bed | 1310 | return __pte; |
2dcea57a HC |
1311 | } |
1312 | ||
190a1d72 MS |
1313 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1314 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
1315 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1316 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1317 | |
190a1d72 MS |
1318 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1319 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1320 | |
190a1d72 MS |
1321 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1322 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 1323 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1324 | |
5a216a20 MS |
1325 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
1326 | { | |
6252d702 MS |
1327 | pud_t *pud = (pud_t *) pgd; |
1328 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1329 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
1330 | return pud + pud_index(address); |
1331 | } | |
1da177e4 | 1332 | |
190a1d72 | 1333 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1334 | { |
6252d702 MS |
1335 | pmd_t *pmd = (pmd_t *) pud; |
1336 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
1337 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1338 | return pmd + pmd_index(address); |
1da177e4 LT |
1339 | } |
1340 | ||
190a1d72 MS |
1341 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1342 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1343 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1344 | |
152125b7 | 1345 | #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) |
1da177e4 | 1346 | |
190a1d72 MS |
1347 | /* Find an entry in the lowest level page table.. */ |
1348 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1349 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 | 1350 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1da177e4 | 1351 | #define pte_unmap(pte) do { } while (0) |
1da177e4 | 1352 | |
106c992a | 1353 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) |
1ae1c1d0 GS |
1354 | static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) |
1355 | { | |
d8e7a33d | 1356 | /* |
e5098611 | 1357 | * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx) |
d8e7a33d GS |
1358 | * Convert to segment table entry format. |
1359 | */ | |
1360 | if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) | |
1361 | return pgprot_val(SEGMENT_NONE); | |
e5098611 MS |
1362 | if (pgprot_val(pgprot) == pgprot_val(PAGE_READ)) |
1363 | return pgprot_val(SEGMENT_READ); | |
1364 | return pgprot_val(SEGMENT_WRITE); | |
1ae1c1d0 GS |
1365 | } |
1366 | ||
152125b7 | 1367 | static inline pmd_t pmd_wrprotect(pmd_t pmd) |
0944fe3f | 1368 | { |
152125b7 MS |
1369 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; |
1370 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1371 | return pmd; | |
1372 | } | |
1373 | ||
1374 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
1375 | { | |
1376 | pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; | |
1377 | if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1378 | return pmd; | |
1379 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1380 | return pmd; | |
1381 | } | |
1382 | ||
1383 | static inline pmd_t pmd_mkclean(pmd_t pmd) | |
1384 | { | |
1385 | if (pmd_large(pmd)) { | |
1386 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; | |
0944fe3f | 1387 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; |
152125b7 MS |
1388 | } |
1389 | return pmd; | |
1390 | } | |
1391 | ||
1392 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
1393 | { | |
1394 | if (pmd_large(pmd)) { | |
5614dd92 MS |
1395 | pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY | |
1396 | _SEGMENT_ENTRY_SOFT_DIRTY; | |
152125b7 MS |
1397 | if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) |
1398 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1399 | } | |
1400 | return pmd; | |
1401 | } | |
1402 | ||
1403 | static inline pmd_t pmd_mkyoung(pmd_t pmd) | |
1404 | { | |
1405 | if (pmd_large(pmd)) { | |
0944fe3f | 1406 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
152125b7 MS |
1407 | if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) |
1408 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; | |
0944fe3f | 1409 | } |
0944fe3f MS |
1410 | return pmd; |
1411 | } | |
1412 | ||
1413 | static inline pmd_t pmd_mkold(pmd_t pmd) | |
1414 | { | |
152125b7 | 1415 | if (pmd_large(pmd)) { |
0944fe3f MS |
1416 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; |
1417 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1418 | } | |
0944fe3f MS |
1419 | return pmd; |
1420 | } | |
1421 | ||
1ae1c1d0 GS |
1422 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
1423 | { | |
152125b7 MS |
1424 | if (pmd_large(pmd)) { |
1425 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | | |
1426 | _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | | |
5614dd92 MS |
1427 | _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SPLIT | |
1428 | _SEGMENT_ENTRY_SOFT_DIRTY; | |
152125b7 MS |
1429 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1430 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1431 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1432 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) | |
1433 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1434 | return pmd; | |
1435 | } | |
1436 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN; | |
1ae1c1d0 GS |
1437 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1438 | return pmd; | |
1439 | } | |
1440 | ||
106c992a | 1441 | static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) |
1ae1c1d0 | 1442 | { |
106c992a GS |
1443 | pmd_t __pmd; |
1444 | pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); | |
152125b7 | 1445 | return __pmd; |
1ae1c1d0 GS |
1446 | } |
1447 | ||
106c992a GS |
1448 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ |
1449 | ||
1b948d6c MS |
1450 | static inline void __pmdp_csp(pmd_t *pmdp) |
1451 | { | |
1452 | register unsigned long reg2 asm("2") = pmd_val(*pmdp); | |
1453 | register unsigned long reg3 asm("3") = pmd_val(*pmdp) | | |
1454 | _SEGMENT_ENTRY_INVALID; | |
1455 | register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5; | |
1456 | ||
1457 | asm volatile( | |
1458 | " csp %1,%3" | |
1459 | : "=m" (*pmdp) | |
1460 | : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc"); | |
1461 | } | |
1462 | ||
1463 | static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp) | |
1464 | { | |
1465 | unsigned long sto; | |
1466 | ||
1467 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1468 | asm volatile( | |
1469 | " .insn rrf,0xb98e0000,%2,%3,0,0" | |
1470 | : "=m" (*pmdp) | |
1471 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1472 | : "cc" ); | |
1473 | } | |
1474 | ||
1475 | static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp) | |
1476 | { | |
1477 | unsigned long sto; | |
1478 | ||
1479 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1480 | asm volatile( | |
1481 | " .insn rrf,0xb98e0000,%2,%3,0,1" | |
1482 | : "=m" (*pmdp) | |
1483 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1484 | : "cc" ); | |
1485 | } | |
1486 | ||
1487 | static inline void pmdp_flush_direct(struct mm_struct *mm, | |
1488 | unsigned long address, pmd_t *pmdp) | |
1489 | { | |
1490 | int active, count; | |
1491 | ||
1492 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) | |
1493 | return; | |
1494 | if (!MACHINE_HAS_IDTE) { | |
1495 | __pmdp_csp(pmdp); | |
1496 | return; | |
1497 | } | |
1498 | active = (mm == current->active_mm) ? 1 : 0; | |
1499 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1500 | if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && | |
1501 | cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) | |
1502 | __pmdp_idte_local(address, pmdp); | |
1503 | else | |
1504 | __pmdp_idte(address, pmdp); | |
1505 | atomic_sub(0x10000, &mm->context.attach_count); | |
1506 | } | |
1507 | ||
3eabaee9 MS |
1508 | static inline void pmdp_flush_lazy(struct mm_struct *mm, |
1509 | unsigned long address, pmd_t *pmdp) | |
1510 | { | |
53e857f3 | 1511 | int active, count; |
3eabaee9 | 1512 | |
1b948d6c MS |
1513 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) |
1514 | return; | |
53e857f3 MS |
1515 | active = (mm == current->active_mm) ? 1 : 0; |
1516 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1517 | if ((count & 0xffff) <= active) { | |
1518 | pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID; | |
3eabaee9 | 1519 | mm->context.flush_mm = 1; |
1b948d6c MS |
1520 | } else if (MACHINE_HAS_IDTE) |
1521 | __pmdp_idte(address, pmdp); | |
1522 | else | |
1523 | __pmdp_csp(pmdp); | |
53e857f3 | 1524 | atomic_sub(0x10000, &mm->context.attach_count); |
3eabaee9 MS |
1525 | } |
1526 | ||
106c992a GS |
1527 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1528 | ||
1529 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
6b0b50b0 AK |
1530 | extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
1531 | pgtable_t pgtable); | |
106c992a GS |
1532 | |
1533 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
6b0b50b0 | 1534 | extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
106c992a GS |
1535 | |
1536 | static inline int pmd_trans_splitting(pmd_t pmd) | |
1537 | { | |
152125b7 MS |
1538 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) && |
1539 | (pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT); | |
106c992a GS |
1540 | } |
1541 | ||
1542 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1543 | pmd_t *pmdp, pmd_t entry) | |
1544 | { | |
106c992a GS |
1545 | *pmdp = entry; |
1546 | } | |
1547 | ||
1548 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1549 | { | |
1550 | pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; | |
152125b7 MS |
1551 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
1552 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1ae1c1d0 GS |
1553 | return pmd; |
1554 | } | |
1555 | ||
1ae1c1d0 GS |
1556 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1557 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1558 | unsigned long address, pmd_t *pmdp) | |
1559 | { | |
0944fe3f | 1560 | pmd_t pmd; |
1ae1c1d0 | 1561 | |
0944fe3f | 1562 | pmd = *pmdp; |
1b948d6c | 1563 | pmdp_flush_direct(vma->vm_mm, address, pmdp); |
0944fe3f MS |
1564 | *pmdp = pmd_mkold(pmd); |
1565 | return pmd_young(pmd); | |
1ae1c1d0 GS |
1566 | } |
1567 | ||
8809aa2d AK |
1568 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
1569 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
1570 | unsigned long address, pmd_t *pmdp) | |
1ae1c1d0 GS |
1571 | { |
1572 | pmd_t pmd = *pmdp; | |
1573 | ||
1b948d6c | 1574 | pmdp_flush_direct(mm, address, pmdp); |
1ae1c1d0 GS |
1575 | pmd_clear(pmdp); |
1576 | return pmd; | |
1577 | } | |
1578 | ||
8809aa2d AK |
1579 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1580 | static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm, | |
1581 | unsigned long address, | |
1582 | pmd_t *pmdp, int full) | |
fcbe08d6 MS |
1583 | { |
1584 | pmd_t pmd = *pmdp; | |
1585 | ||
1586 | if (!full) | |
1587 | pmdp_flush_lazy(mm, address, pmdp); | |
1588 | pmd_clear(pmdp); | |
1589 | return pmd; | |
1590 | } | |
1591 | ||
8809aa2d AK |
1592 | #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH |
1593 | static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, | |
1594 | unsigned long address, pmd_t *pmdp) | |
1ae1c1d0 | 1595 | { |
8809aa2d | 1596 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
1ae1c1d0 GS |
1597 | } |
1598 | ||
1599 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1600 | static inline void pmdp_invalidate(struct vm_area_struct *vma, | |
1601 | unsigned long address, pmd_t *pmdp) | |
1602 | { | |
1b948d6c | 1603 | pmdp_flush_direct(vma->vm_mm, address, pmdp); |
1ae1c1d0 GS |
1604 | } |
1605 | ||
be328650 GS |
1606 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1607 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
1608 | unsigned long address, pmd_t *pmdp) | |
1609 | { | |
1610 | pmd_t pmd = *pmdp; | |
1611 | ||
1612 | if (pmd_write(pmd)) { | |
1b948d6c | 1613 | pmdp_flush_direct(mm, address, pmdp); |
be328650 GS |
1614 | set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); |
1615 | } | |
1616 | } | |
1617 | ||
f28b6ff8 AK |
1618 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1619 | unsigned long address, | |
1620 | pmd_t *pmdp) | |
1621 | { | |
8809aa2d | 1622 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
f28b6ff8 AK |
1623 | } |
1624 | #define pmdp_collapse_flush pmdp_collapse_flush | |
1625 | ||
1ae1c1d0 GS |
1626 | #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) |
1627 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) | |
1628 | ||
1629 | static inline int pmd_trans_huge(pmd_t pmd) | |
1630 | { | |
1631 | return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; | |
1632 | } | |
1633 | ||
1634 | static inline int has_transparent_hugepage(void) | |
1635 | { | |
1636 | return MACHINE_HAS_HPAGE ? 1 : 0; | |
1637 | } | |
75077afb GS |
1638 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1639 | ||
1da177e4 | 1640 | /* |
1da177e4 LT |
1641 | * 64 bit swap entry format: |
1642 | * A page-table entry has some bits we have to treat in a special way. | |
4e0a6412 | 1643 | * Bits 52 and bit 55 have to be zero, otherwise a specification |
1da177e4 | 1644 | * exception will occur instead of a page translation exception. The |
4e0a6412 | 1645 | * specification exception has the bad habit not to store necessary |
1da177e4 | 1646 | * information in the lowcore. |
a1c843b8 MS |
1647 | * Bits 54 and 63 are used to indicate the page type. |
1648 | * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 | |
1649 | * This leaves the bits 0-51 and bits 56-62 to store type and offset. | |
1650 | * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 | |
1651 | * for the offset. | |
1652 | * | offset |01100|type |00| | |
1653 | * |0000000000111111111122222222223333333333444444444455|55555|55566|66| | |
1654 | * |0123456789012345678901234567890123456789012345678901|23456|78901|23| | |
1da177e4 | 1655 | */ |
5a79859a | 1656 | |
a1c843b8 MS |
1657 | #define __SWP_OFFSET_MASK ((1UL << 52) - 1) |
1658 | #define __SWP_OFFSET_SHIFT 12 | |
1659 | #define __SWP_TYPE_MASK ((1UL << 5) - 1) | |
1660 | #define __SWP_TYPE_SHIFT 2 | |
5a79859a | 1661 | |
4448aaf0 | 1662 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1663 | { |
1664 | pte_t pte; | |
a1c843b8 MS |
1665 | |
1666 | pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; | |
1667 | pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; | |
1668 | pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; | |
1da177e4 LT |
1669 | return pte; |
1670 | } | |
1671 | ||
a1c843b8 MS |
1672 | static inline unsigned long __swp_type(swp_entry_t entry) |
1673 | { | |
1674 | return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; | |
1675 | } | |
1676 | ||
1677 | static inline unsigned long __swp_offset(swp_entry_t entry) | |
1678 | { | |
1679 | return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; | |
1680 | } | |
1681 | ||
1682 | static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) | |
1683 | { | |
1684 | return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; | |
1685 | } | |
1da177e4 LT |
1686 | |
1687 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1688 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1689 | ||
1da177e4 LT |
1690 | #endif /* !__ASSEMBLY__ */ |
1691 | ||
1692 | #define kern_addr_valid(addr) (1) | |
1693 | ||
17f34580 HC |
1694 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1695 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1696 | extern int s390_enable_sie(void); |
3ac8e380 | 1697 | extern int s390_enable_skey(void); |
a13cff31 | 1698 | extern void s390_reset_cmma(struct mm_struct *mm); |
f4eb07c1 | 1699 | |
1f6b83e5 MS |
1700 | /* s390 has a private copy of get unmapped area to deal with cache synonyms */ |
1701 | #define HAVE_ARCH_UNMAPPED_AREA | |
1702 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
1703 | ||
1da177e4 LT |
1704 | /* |
1705 | * No page table caches to initialise | |
1706 | */ | |
765a0cac HC |
1707 | static inline void pgtable_cache_init(void) { } |
1708 | static inline void check_pgt_cache(void) { } | |
1da177e4 | 1709 | |
1da177e4 LT |
1710 | #include <asm-generic/pgtable.h> |
1711 | ||
1712 | #endif /* _S390_PAGE_H */ |