Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999, 2000 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com) |
5 | * Ulrich Weigand (weigand@de.ibm.com) | |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
7 | * | |
8 | * Derived from "include/asm-i386/pgtable.h" | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_S390_PGTABLE_H | |
12 | #define _ASM_S390_PGTABLE_H | |
13 | ||
1da177e4 | 14 | /* |
a1c843b8 MS |
15 | * The Linux memory management assumes a three-level page table setup. |
16 | * For s390 64 bit we use up to four of the five levels the hardware | |
17 | * provides (region first tables are not used). | |
1da177e4 LT |
18 | * |
19 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
20 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
21 | * into the pgd entry) | |
22 | * | |
23 | * This file contains the functions and defines necessary to modify and use | |
24 | * the S390 page table tree. | |
25 | */ | |
26 | #ifndef __ASSEMBLY__ | |
9789db08 | 27 | #include <linux/sched.h> |
2dcea57a | 28 | #include <linux/mm_types.h> |
abf09bed | 29 | #include <linux/page-flags.h> |
527e30b4 | 30 | #include <linux/radix-tree.h> |
1da177e4 | 31 | #include <asm/bug.h> |
b2fa47e6 | 32 | #include <asm/page.h> |
1da177e4 | 33 | |
1da177e4 LT |
34 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
35 | extern void paging_init(void); | |
2b67fc46 | 36 | extern void vmem_map_init(void); |
1da177e4 LT |
37 | |
38 | /* | |
39 | * The S390 doesn't have any external MMU info: the kernel page | |
40 | * tables contain all the necessary information. | |
41 | */ | |
4b3073e1 | 42 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
b113da65 | 43 | #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) |
1da177e4 LT |
44 | |
45 | /* | |
238ec4ef | 46 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
47 | * for zero-mapped memory areas etc.. |
48 | */ | |
238ec4ef MS |
49 | |
50 | extern unsigned long empty_zero_page; | |
51 | extern unsigned long zero_page_mask; | |
52 | ||
53 | #define ZERO_PAGE(vaddr) \ | |
54 | (virt_to_page((void *)(empty_zero_page + \ | |
55 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
816422ad | 56 | #define __HAVE_COLOR_ZERO_PAGE |
238ec4ef | 57 | |
4f2e2903 | 58 | /* TODO: s390 cannot support io_remap_pfn_range... */ |
1da177e4 LT |
59 | #endif /* !__ASSEMBLY__ */ |
60 | ||
61 | /* | |
62 | * PMD_SHIFT determines the size of the area a second-level page | |
63 | * table can map | |
64 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
65 | */ | |
5a79859a HC |
66 | #define PMD_SHIFT 20 |
67 | #define PUD_SHIFT 31 | |
68 | #define PGDIR_SHIFT 42 | |
1da177e4 LT |
69 | |
70 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
71 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
72 | #define PUD_SIZE (1UL << PUD_SHIFT) |
73 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
74 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
75 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
76 | |
77 | /* | |
78 | * entries per page directory level: the S390 is two-level, so | |
79 | * we don't really have any PMD directory physically. | |
80 | * for S390 segment-table entries are combined to one PGD | |
81 | * that leads to 1024 pte per pgd | |
82 | */ | |
146e4b3c | 83 | #define PTRS_PER_PTE 256 |
146e4b3c | 84 | #define PTRS_PER_PMD 2048 |
5a216a20 | 85 | #define PTRS_PER_PUD 2048 |
146e4b3c | 86 | #define PTRS_PER_PGD 2048 |
1da177e4 | 87 | |
d016bf7e | 88 | #define FIRST_USER_ADDRESS 0UL |
d455a369 | 89 | |
1da177e4 LT |
90 | #define pte_ERROR(e) \ |
91 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
92 | #define pmd_ERROR(e) \ | |
93 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
94 | #define pud_ERROR(e) \ |
95 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
96 | #define pgd_ERROR(e) \ |
97 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
98 | ||
99 | #ifndef __ASSEMBLY__ | |
100 | /* | |
a1c843b8 MS |
101 | * The vmalloc and module area will always be on the topmost area of the |
102 | * kernel mapping. We reserve 128GB (64bit) for vmalloc and modules. | |
c972cc60 HC |
103 | * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where |
104 | * modules will reside. That makes sure that inter module branches always | |
105 | * happen without trampolines and in addition the placement within a 2GB frame | |
106 | * is branch prediction unit friendly. | |
8b62bc96 | 107 | */ |
239a6425 | 108 | extern unsigned long VMALLOC_START; |
14045ebf MS |
109 | extern unsigned long VMALLOC_END; |
110 | extern struct page *vmemmap; | |
239a6425 | 111 | |
14045ebf | 112 | #define VMEM_MAX_PHYS ((unsigned long) vmemmap) |
5fd9c6e2 | 113 | |
c972cc60 HC |
114 | extern unsigned long MODULES_VADDR; |
115 | extern unsigned long MODULES_END; | |
116 | #define MODULES_VADDR MODULES_VADDR | |
117 | #define MODULES_END MODULES_END | |
118 | #define MODULES_LEN (1UL << 31) | |
c972cc60 | 119 | |
c933146a HC |
120 | static inline int is_module_addr(void *addr) |
121 | { | |
c933146a HC |
122 | BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); |
123 | if (addr < (void *)MODULES_VADDR) | |
124 | return 0; | |
125 | if (addr > (void *)MODULES_END) | |
126 | return 0; | |
c933146a HC |
127 | return 1; |
128 | } | |
129 | ||
1da177e4 | 130 | /* |
1da177e4 | 131 | * A 64 bit pagetable entry of S390 has following format: |
6a985c61 | 132 | * | PFRA |0IPC| OS | |
1da177e4 LT |
133 | * 0000000000111111111122222222223333333333444444444455555555556666 |
134 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
135 | * | |
136 | * I Page-Invalid Bit: Page is not available for address-translation | |
137 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 138 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
139 | * |
140 | * A 64 bit segmenttable entry of S390 has following format: | |
141 | * | P-table origin | TT | |
142 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
143 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
144 | * | |
145 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
146 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
147 | * P Page-Protection Bit: Store access not possible for page | |
148 | * TT Type 00 | |
149 | * | |
150 | * A 64 bit region table entry of S390 has following format: | |
151 | * | S-table origin | TF TTTL | |
152 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
153 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
154 | * | |
155 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
156 | * TT Type 01 | |
157 | * TF | |
190a1d72 | 158 | * TL Table length |
1da177e4 LT |
159 | * |
160 | * The 64 bit regiontable origin of S390 has following format: | |
161 | * | region table origon | DTTL | |
162 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
163 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
164 | * | |
165 | * X Space-Switch event: | |
166 | * G Segment-Invalid Bit: | |
167 | * P Private-Space Bit: | |
168 | * S Storage-Alteration: | |
169 | * R Real space | |
170 | * TL Table-Length: | |
171 | * | |
172 | * A storage key has the following format: | |
173 | * | ACC |F|R|C|0| | |
174 | * 0 3 4 5 6 7 | |
175 | * ACC: access key | |
176 | * F : fetch protection bit | |
177 | * R : referenced bit | |
178 | * C : changed bit | |
179 | */ | |
180 | ||
181 | /* Hardware bits in the page table entry */ | |
e5098611 | 182 | #define _PAGE_PROTECT 0x200 /* HW read-only bit */ |
83377484 | 183 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ |
e5098611 | 184 | #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ |
3610cce8 MS |
185 | |
186 | /* Software bits in the page table entry */ | |
e5098611 | 187 | #define _PAGE_PRESENT 0x001 /* SW pte present bit */ |
e5098611 MS |
188 | #define _PAGE_YOUNG 0x004 /* SW pte young bit */ |
189 | #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ | |
0944fe3f MS |
190 | #define _PAGE_READ 0x010 /* SW pte read bit */ |
191 | #define _PAGE_WRITE 0x020 /* SW pte write bit */ | |
192 | #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ | |
b31288fa | 193 | #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ |
a08cb629 | 194 | #define __HAVE_ARCH_PTE_SPECIAL |
1da177e4 | 195 | |
5614dd92 MS |
196 | #ifdef CONFIG_MEM_SOFT_DIRTY |
197 | #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ | |
198 | #else | |
199 | #define _PAGE_SOFT_DIRTY 0x000 | |
200 | #endif | |
201 | ||
138c9021 | 202 | /* Set of bits not changed in pte_modify */ |
6a5c1482 | 203 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ |
5614dd92 | 204 | _PAGE_YOUNG | _PAGE_SOFT_DIRTY) |
53492b1d | 205 | |
83377484 | 206 | /* |
6e76d4b2 KS |
207 | * handle_pte_fault uses pte_present and pte_none to find out the pte type |
208 | * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to | |
209 | * distinguish present from not-present ptes. It is changed only with the page | |
210 | * table lock held. | |
83377484 | 211 | * |
e5098611 | 212 | * The following table gives the different possible bit combinations for |
a1c843b8 MS |
213 | * the pte hardware and software bits in the last 12 bits of a pte |
214 | * (. unassigned bit, x don't care, t swap type): | |
83377484 | 215 | * |
0944fe3f MS |
216 | * 842100000000 |
217 | * 000084210000 | |
218 | * 000000008421 | |
a1c843b8 MS |
219 | * .IR.uswrdy.p |
220 | * empty .10.00000000 | |
221 | * swap .11..ttttt.0 | |
222 | * prot-none, clean, old .11.xx0000.1 | |
223 | * prot-none, clean, young .11.xx0001.1 | |
224 | * prot-none, dirty, old .10.xx0010.1 | |
225 | * prot-none, dirty, young .10.xx0011.1 | |
226 | * read-only, clean, old .11.xx0100.1 | |
227 | * read-only, clean, young .01.xx0101.1 | |
228 | * read-only, dirty, old .11.xx0110.1 | |
229 | * read-only, dirty, young .01.xx0111.1 | |
230 | * read-write, clean, old .11.xx1100.1 | |
231 | * read-write, clean, young .01.xx1101.1 | |
232 | * read-write, dirty, old .10.xx1110.1 | |
233 | * read-write, dirty, young .00.xx1111.1 | |
234 | * HW-bits: R read-only, I invalid | |
235 | * SW-bits: p present, y young, d dirty, r read, w write, s special, | |
236 | * u unused, l large | |
e5098611 | 237 | * |
a1c843b8 MS |
238 | * pte_none is true for the bit pattern .10.00000000, pte == 0x400 |
239 | * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 | |
240 | * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 | |
83377484 MS |
241 | */ |
242 | ||
3610cce8 MS |
243 | /* Bits in the segment/region table address-space-control-element */ |
244 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
245 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
246 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
247 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
248 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
249 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
250 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
251 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
252 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
253 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
254 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
255 | ||
256 | /* Bits in the region table entry */ | |
257 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
e5098611 MS |
258 | #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ |
259 | #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ | |
3610cce8 MS |
260 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ |
261 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
262 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
263 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
264 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
265 | ||
266 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
e5098611 | 267 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) |
3610cce8 | 268 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) |
e5098611 | 269 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) |
3610cce8 | 270 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) |
e5098611 | 271 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) |
3610cce8 | 272 | |
18da2369 | 273 | #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ |
1819ed1f | 274 | #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ |
18da2369 | 275 | |
1da177e4 | 276 | /* Bits in the segment table entry */ |
0944fe3f | 277 | #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL |
152125b7 | 278 | #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL |
ea81531d | 279 | #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ |
3610cce8 | 280 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
e5098611 MS |
281 | #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ |
282 | #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ | |
1da177e4 | 283 | |
3610cce8 | 284 | #define _SEGMENT_ENTRY (0) |
e5098611 | 285 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) |
3610cce8 | 286 | |
152125b7 MS |
287 | #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ |
288 | #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ | |
152125b7 | 289 | #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ |
152125b7 MS |
290 | #define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */ |
291 | #define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */ | |
0944fe3f | 292 | |
5614dd92 MS |
293 | #ifdef CONFIG_MEM_SOFT_DIRTY |
294 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ | |
295 | #else | |
296 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ | |
297 | #endif | |
298 | ||
0944fe3f MS |
299 | /* |
300 | * Segment table entry encoding (R = read-only, I = invalid, y = young bit): | |
152125b7 MS |
301 | * dy..R...I...wr |
302 | * prot-none, clean, old 00..1...1...00 | |
303 | * prot-none, clean, young 01..1...1...00 | |
304 | * prot-none, dirty, old 10..1...1...00 | |
305 | * prot-none, dirty, young 11..1...1...00 | |
306 | * read-only, clean, old 00..1...1...01 | |
307 | * read-only, clean, young 01..1...0...01 | |
308 | * read-only, dirty, old 10..1...1...01 | |
309 | * read-only, dirty, young 11..1...0...01 | |
310 | * read-write, clean, old 00..1...1...11 | |
311 | * read-write, clean, young 01..1...0...11 | |
312 | * read-write, dirty, old 10..0...1...11 | |
313 | * read-write, dirty, young 11..0...0...11 | |
0944fe3f MS |
314 | * The segment table origin is used to distinguish empty (origin==0) from |
315 | * read-write, old segment table entries (origin!=0) | |
a1c843b8 MS |
316 | * HW-bits: R read-only, I invalid |
317 | * SW-bits: y young, d dirty, r read, w write | |
0944fe3f | 318 | */ |
e5098611 | 319 | |
6c61cfe9 | 320 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
321 | #define PGSTE_ACC_BITS 0xf000000000000000UL |
322 | #define PGSTE_FP_BIT 0x0800000000000000UL | |
323 | #define PGSTE_PCL_BIT 0x0080000000000000UL | |
324 | #define PGSTE_HR_BIT 0x0040000000000000UL | |
325 | #define PGSTE_HC_BIT 0x0020000000000000UL | |
326 | #define PGSTE_GR_BIT 0x0004000000000000UL | |
327 | #define PGSTE_GC_BIT 0x0002000000000000UL | |
0a61b222 MS |
328 | #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ |
329 | #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ | |
6c61cfe9 | 330 | |
b31288fa KW |
331 | /* Guest Page State used for virtualization */ |
332 | #define _PGSTE_GPS_ZERO 0x0000000080000000UL | |
333 | #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL | |
334 | #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL | |
335 | #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL | |
336 | ||
1da177e4 | 337 | /* |
3610cce8 MS |
338 | * A user page table pointer has the space-switch-event bit, the |
339 | * private-space-control bit and the storage-alteration-event-control | |
340 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 341 | */ |
3610cce8 MS |
342 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
343 | _ASCE_ALT_EVENT) | |
1da177e4 | 344 | |
1da177e4 | 345 | /* |
9282ed92 | 346 | * Page protection definitions. |
1da177e4 | 347 | */ |
e5098611 | 348 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID) |
0944fe3f MS |
349 | #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \ |
350 | _PAGE_INVALID | _PAGE_PROTECT) | |
351 | #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
352 | _PAGE_INVALID | _PAGE_PROTECT) | |
353 | ||
354 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
355 | _PAGE_YOUNG | _PAGE_DIRTY) | |
356 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
357 | _PAGE_YOUNG | _PAGE_DIRTY) | |
358 | #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ | |
359 | _PAGE_PROTECT) | |
1da177e4 LT |
360 | |
361 | /* | |
043d0708 MS |
362 | * On s390 the page table entry has an invalid bit and a read-only bit. |
363 | * Read permission implies execute permission and write permission | |
364 | * implies read permission. | |
1da177e4 LT |
365 | */ |
366 | /*xwr*/ | |
9282ed92 | 367 | #define __P000 PAGE_NONE |
e5098611 MS |
368 | #define __P001 PAGE_READ |
369 | #define __P010 PAGE_READ | |
370 | #define __P011 PAGE_READ | |
371 | #define __P100 PAGE_READ | |
372 | #define __P101 PAGE_READ | |
373 | #define __P110 PAGE_READ | |
374 | #define __P111 PAGE_READ | |
9282ed92 GS |
375 | |
376 | #define __S000 PAGE_NONE | |
e5098611 MS |
377 | #define __S001 PAGE_READ |
378 | #define __S010 PAGE_WRITE | |
379 | #define __S011 PAGE_WRITE | |
380 | #define __S100 PAGE_READ | |
381 | #define __S101 PAGE_READ | |
382 | #define __S110 PAGE_WRITE | |
383 | #define __S111 PAGE_WRITE | |
1da177e4 | 384 | |
106c992a GS |
385 | /* |
386 | * Segment entry (large page) protection definitions. | |
387 | */ | |
e5098611 MS |
388 | #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ |
389 | _SEGMENT_ENTRY_PROTECT) | |
152125b7 MS |
390 | #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \ |
391 | _SEGMENT_ENTRY_READ) | |
392 | #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \ | |
393 | _SEGMENT_ENTRY_WRITE) | |
106c992a | 394 | |
b2fa47e6 MS |
395 | static inline int mm_has_pgste(struct mm_struct *mm) |
396 | { | |
397 | #ifdef CONFIG_PGSTE | |
398 | if (unlikely(mm->context.has_pgste)) | |
399 | return 1; | |
400 | #endif | |
401 | return 0; | |
402 | } | |
65eef335 | 403 | |
0b46e0a3 MS |
404 | static inline int mm_alloc_pgste(struct mm_struct *mm) |
405 | { | |
406 | #ifdef CONFIG_PGSTE | |
407 | if (unlikely(mm->context.alloc_pgste)) | |
408 | return 1; | |
409 | #endif | |
410 | return 0; | |
411 | } | |
412 | ||
2faee8ff DD |
413 | /* |
414 | * In the case that a guest uses storage keys | |
415 | * faults should no longer be backed by zero pages | |
416 | */ | |
417 | #define mm_forbids_zeropage mm_use_skey | |
65eef335 DD |
418 | static inline int mm_use_skey(struct mm_struct *mm) |
419 | { | |
420 | #ifdef CONFIG_PGSTE | |
421 | if (mm->context.use_skey) | |
422 | return 1; | |
423 | #endif | |
424 | return 0; | |
425 | } | |
426 | ||
1da177e4 LT |
427 | /* |
428 | * pgd/pmd/pte query functions | |
429 | */ | |
5a216a20 MS |
430 | static inline int pgd_present(pgd_t pgd) |
431 | { | |
6252d702 MS |
432 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
433 | return 1; | |
5a216a20 MS |
434 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
435 | } | |
436 | ||
437 | static inline int pgd_none(pgd_t pgd) | |
438 | { | |
6252d702 MS |
439 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
440 | return 0; | |
e5098611 | 441 | return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; |
5a216a20 MS |
442 | } |
443 | ||
444 | static inline int pgd_bad(pgd_t pgd) | |
445 | { | |
6252d702 MS |
446 | /* |
447 | * With dynamic page table levels the pgd can be a region table | |
448 | * entry or a segment table entry. Check for the bit that are | |
449 | * invalid for either table entry. | |
450 | */ | |
5a216a20 | 451 | unsigned long mask = |
e5098611 | 452 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
453 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
454 | return (pgd_val(pgd) & mask) != 0; | |
455 | } | |
190a1d72 MS |
456 | |
457 | static inline int pud_present(pud_t pud) | |
1da177e4 | 458 | { |
6252d702 MS |
459 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
460 | return 1; | |
0d017923 | 461 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
462 | } |
463 | ||
190a1d72 | 464 | static inline int pud_none(pud_t pud) |
1da177e4 | 465 | { |
6252d702 MS |
466 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
467 | return 0; | |
e5098611 | 468 | return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL; |
1da177e4 LT |
469 | } |
470 | ||
18da2369 HC |
471 | static inline int pud_large(pud_t pud) |
472 | { | |
473 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) | |
474 | return 0; | |
475 | return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); | |
476 | } | |
477 | ||
190a1d72 | 478 | static inline int pud_bad(pud_t pud) |
1da177e4 | 479 | { |
6252d702 MS |
480 | /* |
481 | * With dynamic page table levels the pud can be a region table | |
482 | * entry or a segment table entry. Check for the bit that are | |
483 | * invalid for either table entry. | |
484 | */ | |
5a216a20 | 485 | unsigned long mask = |
e5098611 | 486 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
487 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
488 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
489 | } |
490 | ||
4448aaf0 | 491 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 492 | { |
e5098611 | 493 | return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
494 | } |
495 | ||
4448aaf0 | 496 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 497 | { |
e5098611 | 498 | return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
499 | } |
500 | ||
378b1e7a HC |
501 | static inline int pmd_large(pmd_t pmd) |
502 | { | |
e5098611 | 503 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; |
378b1e7a HC |
504 | } |
505 | ||
7cded342 | 506 | static inline unsigned long pmd_pfn(pmd_t pmd) |
0944fe3f | 507 | { |
152125b7 MS |
508 | unsigned long origin_mask; |
509 | ||
510 | origin_mask = _SEGMENT_ENTRY_ORIGIN; | |
511 | if (pmd_large(pmd)) | |
512 | origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; | |
513 | return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT; | |
0944fe3f MS |
514 | } |
515 | ||
4448aaf0 | 516 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 517 | { |
0944fe3f MS |
518 | if (pmd_large(pmd)) |
519 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; | |
0944fe3f | 520 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; |
1da177e4 LT |
521 | } |
522 | ||
1ae1c1d0 GS |
523 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
524 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
525 | unsigned long address, pmd_t *pmdp, | |
526 | pmd_t entry, int dirty); | |
527 | ||
528 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
529 | extern int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
530 | unsigned long address, pmd_t *pmdp); | |
531 | ||
532 | #define __HAVE_ARCH_PMD_WRITE | |
533 | static inline int pmd_write(pmd_t pmd) | |
534 | { | |
152125b7 MS |
535 | return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; |
536 | } | |
537 | ||
538 | static inline int pmd_dirty(pmd_t pmd) | |
539 | { | |
540 | int dirty = 1; | |
541 | if (pmd_large(pmd)) | |
542 | dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; | |
543 | return dirty; | |
1ae1c1d0 GS |
544 | } |
545 | ||
546 | static inline int pmd_young(pmd_t pmd) | |
547 | { | |
152125b7 MS |
548 | int young = 1; |
549 | if (pmd_large(pmd)) | |
0944fe3f | 550 | young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; |
0944fe3f | 551 | return young; |
1ae1c1d0 GS |
552 | } |
553 | ||
e5098611 | 554 | static inline int pte_present(pte_t pte) |
1da177e4 | 555 | { |
e5098611 MS |
556 | /* Bit pattern: (pte & 0x001) == 0x001 */ |
557 | return (pte_val(pte) & _PAGE_PRESENT) != 0; | |
1da177e4 LT |
558 | } |
559 | ||
e5098611 | 560 | static inline int pte_none(pte_t pte) |
1da177e4 | 561 | { |
e5098611 MS |
562 | /* Bit pattern: pte == 0x400 */ |
563 | return pte_val(pte) == _PAGE_INVALID; | |
1da177e4 LT |
564 | } |
565 | ||
b31288fa KW |
566 | static inline int pte_swap(pte_t pte) |
567 | { | |
a1c843b8 MS |
568 | /* Bit pattern: (pte & 0x201) == 0x200 */ |
569 | return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) | |
570 | == _PAGE_PROTECT; | |
b31288fa KW |
571 | } |
572 | ||
7e675137 NP |
573 | static inline int pte_special(pte_t pte) |
574 | { | |
a08cb629 | 575 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
576 | } |
577 | ||
ba8a9229 | 578 | #define __HAVE_ARCH_PTE_SAME |
b2fa47e6 MS |
579 | static inline int pte_same(pte_t a, pte_t b) |
580 | { | |
581 | return pte_val(a) == pte_val(b); | |
582 | } | |
1da177e4 | 583 | |
b54565b8 MS |
584 | #ifdef CONFIG_NUMA_BALANCING |
585 | static inline int pte_protnone(pte_t pte) | |
586 | { | |
587 | return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); | |
588 | } | |
589 | ||
590 | static inline int pmd_protnone(pmd_t pmd) | |
591 | { | |
592 | /* pmd_large(pmd) implies pmd_present(pmd) */ | |
593 | return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); | |
594 | } | |
595 | #endif | |
596 | ||
5614dd92 MS |
597 | static inline int pte_soft_dirty(pte_t pte) |
598 | { | |
599 | return pte_val(pte) & _PAGE_SOFT_DIRTY; | |
600 | } | |
601 | #define pte_swp_soft_dirty pte_soft_dirty | |
602 | ||
603 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
604 | { | |
605 | pte_val(pte) |= _PAGE_SOFT_DIRTY; | |
606 | return pte; | |
607 | } | |
608 | #define pte_swp_mksoft_dirty pte_mksoft_dirty | |
609 | ||
610 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
611 | { | |
612 | pte_val(pte) &= ~_PAGE_SOFT_DIRTY; | |
613 | return pte; | |
614 | } | |
615 | #define pte_swp_clear_soft_dirty pte_clear_soft_dirty | |
616 | ||
617 | static inline int pmd_soft_dirty(pmd_t pmd) | |
618 | { | |
619 | return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; | |
620 | } | |
621 | ||
622 | static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) | |
623 | { | |
624 | pmd_val(pmd) |= _SEGMENT_ENTRY_SOFT_DIRTY; | |
625 | return pmd; | |
626 | } | |
627 | ||
628 | static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) | |
629 | { | |
630 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_SOFT_DIRTY; | |
631 | return pmd; | |
632 | } | |
633 | ||
b2fa47e6 | 634 | static inline pgste_t pgste_get_lock(pte_t *ptep) |
5b7baf05 | 635 | { |
b2fa47e6 | 636 | unsigned long new = 0; |
5b7baf05 | 637 | #ifdef CONFIG_PGSTE |
b2fa47e6 MS |
638 | unsigned long old; |
639 | ||
5b7baf05 | 640 | preempt_disable(); |
b2fa47e6 MS |
641 | asm( |
642 | " lg %0,%2\n" | |
643 | "0: lgr %1,%0\n" | |
0d0dafc1 MS |
644 | " nihh %0,0xff7f\n" /* clear PCL bit in old */ |
645 | " oihh %1,0x0080\n" /* set PCL bit in new */ | |
b2fa47e6 MS |
646 | " csg %0,%1,%2\n" |
647 | " jl 0b\n" | |
648 | : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 | 649 | : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); |
5b7baf05 | 650 | #endif |
b2fa47e6 | 651 | return __pgste(new); |
5b7baf05 CB |
652 | } |
653 | ||
b2fa47e6 | 654 | static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) |
5b7baf05 CB |
655 | { |
656 | #ifdef CONFIG_PGSTE | |
b2fa47e6 | 657 | asm( |
0d0dafc1 | 658 | " nihh %1,0xff7f\n" /* clear PCL bit */ |
b2fa47e6 MS |
659 | " stg %1,%0\n" |
660 | : "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 CB |
661 | : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) |
662 | : "cc", "memory"); | |
5b7baf05 CB |
663 | preempt_enable(); |
664 | #endif | |
665 | } | |
666 | ||
d56c893d MS |
667 | static inline pgste_t pgste_get(pte_t *ptep) |
668 | { | |
669 | unsigned long pgste = 0; | |
670 | #ifdef CONFIG_PGSTE | |
671 | pgste = *(unsigned long *)(ptep + PTRS_PER_PTE); | |
672 | #endif | |
673 | return __pgste(pgste); | |
674 | } | |
675 | ||
3a82603b CB |
676 | static inline void pgste_set(pte_t *ptep, pgste_t pgste) |
677 | { | |
678 | #ifdef CONFIG_PGSTE | |
679 | *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; | |
680 | #endif | |
681 | } | |
682 | ||
65eef335 DD |
683 | static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, |
684 | struct mm_struct *mm) | |
5b7baf05 CB |
685 | { |
686 | #ifdef CONFIG_PGSTE | |
0944fe3f | 687 | unsigned long address, bits, skey; |
b2fa47e6 | 688 | |
65eef335 | 689 | if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) |
09b53883 | 690 | return pgste; |
a43a9d93 | 691 | address = pte_val(*ptep) & PAGE_MASK; |
0944fe3f | 692 | skey = (unsigned long) page_get_storage_key(address); |
b2fa47e6 | 693 | bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); |
b2fa47e6 | 694 | /* Transfer page changed & referenced bit to guest bits in pgste */ |
0d0dafc1 | 695 | pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ |
b2fa47e6 | 696 | /* Copy page access key and fetch protection bit to pgste */ |
0944fe3f MS |
697 | pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT); |
698 | pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; | |
b2fa47e6 MS |
699 | #endif |
700 | return pgste; | |
701 | ||
702 | } | |
703 | ||
65eef335 DD |
704 | static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, |
705 | struct mm_struct *mm) | |
b2fa47e6 MS |
706 | { |
707 | #ifdef CONFIG_PGSTE | |
a43a9d93 | 708 | unsigned long address; |
338679f7 | 709 | unsigned long nkey; |
b2fa47e6 | 710 | |
65eef335 | 711 | if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID) |
09b53883 | 712 | return; |
338679f7 | 713 | VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); |
09b53883 | 714 | address = pte_val(entry) & PAGE_MASK; |
338679f7 CB |
715 | /* |
716 | * Set page access key and fetch protection bit from pgste. | |
717 | * The guest C/R information is still in the PGSTE, set real | |
718 | * key C/R to 0. | |
719 | */ | |
fe489bf4 | 720 | nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; |
0a61b222 | 721 | nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48; |
338679f7 | 722 | page_set_storage_key(address, nkey, 0); |
5b7baf05 CB |
723 | #endif |
724 | } | |
725 | ||
0a61b222 | 726 | static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) |
abf09bed | 727 | { |
0a61b222 MS |
728 | if ((pte_val(entry) & _PAGE_PRESENT) && |
729 | (pte_val(entry) & _PAGE_WRITE) && | |
730 | !(pte_val(entry) & _PAGE_INVALID)) { | |
731 | if (!MACHINE_HAS_ESOP) { | |
732 | /* | |
733 | * Without enhanced suppression-on-protection force | |
734 | * the dirty bit on for all writable ptes. | |
735 | */ | |
736 | pte_val(entry) |= _PAGE_DIRTY; | |
737 | pte_val(entry) &= ~_PAGE_PROTECT; | |
738 | } | |
739 | if (!(pte_val(entry) & _PAGE_PROTECT)) | |
740 | /* This pte allows write access, set user-dirty */ | |
741 | pgste_val(pgste) |= PGSTE_UC_BIT; | |
abf09bed MS |
742 | } |
743 | *ptep = entry; | |
0a61b222 | 744 | return pgste; |
abf09bed MS |
745 | } |
746 | ||
e5992f2e MS |
747 | /** |
748 | * struct gmap_struct - guest address space | |
527e30b4 | 749 | * @crst_list: list of all crst tables used in the guest address space |
e5992f2e | 750 | * @mm: pointer to the parent mm_struct |
527e30b4 MS |
751 | * @guest_to_host: radix tree with guest to host address translation |
752 | * @host_to_guest: radix tree with pointer to segment table entries | |
753 | * @guest_table_lock: spinlock to protect all entries in the guest page table | |
e5992f2e | 754 | * @table: pointer to the page directory |
480e5926 | 755 | * @asce: address space control element for gmap page table |
24eb3a82 | 756 | * @pfault_enabled: defines if pfaults are applicable for the guest |
e5992f2e MS |
757 | */ |
758 | struct gmap { | |
759 | struct list_head list; | |
527e30b4 | 760 | struct list_head crst_list; |
e5992f2e | 761 | struct mm_struct *mm; |
527e30b4 MS |
762 | struct radix_tree_root guest_to_host; |
763 | struct radix_tree_root host_to_guest; | |
764 | spinlock_t guest_table_lock; | |
e5992f2e | 765 | unsigned long *table; |
480e5926 | 766 | unsigned long asce; |
c6c956b8 | 767 | unsigned long asce_end; |
2c70fe44 | 768 | void *private; |
24eb3a82 | 769 | bool pfault_enabled; |
e5992f2e MS |
770 | }; |
771 | ||
d3383632 MS |
772 | /** |
773 | * struct gmap_notifier - notify function block for page invalidation | |
774 | * @notifier_call: address of callback function | |
775 | */ | |
776 | struct gmap_notifier { | |
777 | struct list_head list; | |
6e0a0431 | 778 | void (*notifier_call)(struct gmap *gmap, unsigned long gaddr); |
d3383632 MS |
779 | }; |
780 | ||
c6c956b8 | 781 | struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit); |
e5992f2e MS |
782 | void gmap_free(struct gmap *gmap); |
783 | void gmap_enable(struct gmap *gmap); | |
784 | void gmap_disable(struct gmap *gmap); | |
785 | int gmap_map_segment(struct gmap *gmap, unsigned long from, | |
d3383632 | 786 | unsigned long to, unsigned long len); |
e5992f2e | 787 | int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); |
6e0a0431 MS |
788 | unsigned long __gmap_translate(struct gmap *, unsigned long gaddr); |
789 | unsigned long gmap_translate(struct gmap *, unsigned long gaddr); | |
527e30b4 MS |
790 | int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr); |
791 | int gmap_fault(struct gmap *, unsigned long gaddr, unsigned int fault_flags); | |
6e0a0431 MS |
792 | void gmap_discard(struct gmap *, unsigned long from, unsigned long to); |
793 | void __gmap_zap(struct gmap *, unsigned long gaddr); | |
a0bf4f14 DD |
794 | bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *); |
795 | ||
e5992f2e | 796 | |
d3383632 MS |
797 | void gmap_register_ipte_notifier(struct gmap_notifier *); |
798 | void gmap_unregister_ipte_notifier(struct gmap_notifier *); | |
799 | int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); | |
9da4e380 | 800 | void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *); |
d3383632 MS |
801 | |
802 | static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, | |
55dbbdd9 | 803 | unsigned long addr, |
d3383632 MS |
804 | pte_t *ptep, pgste_t pgste) |
805 | { | |
806 | #ifdef CONFIG_PGSTE | |
0d0dafc1 MS |
807 | if (pgste_val(pgste) & PGSTE_IN_BIT) { |
808 | pgste_val(pgste) &= ~PGSTE_IN_BIT; | |
9da4e380 | 809 | gmap_do_ipte_notify(mm, addr, ptep); |
d3383632 MS |
810 | } |
811 | #endif | |
812 | return pgste; | |
813 | } | |
814 | ||
b2fa47e6 MS |
815 | /* |
816 | * Certain architectures need to do special things when PTEs | |
817 | * within a page table are directly modified. Thus, the following | |
818 | * hook is made available. | |
819 | */ | |
820 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
821 | pte_t *ptep, pte_t entry) | |
822 | { | |
823 | pgste_t pgste; | |
824 | ||
825 | if (mm_has_pgste(mm)) { | |
826 | pgste = pgste_get_lock(ptep); | |
b31288fa | 827 | pgste_val(pgste) &= ~_PGSTE_GPS_ZERO; |
65eef335 | 828 | pgste_set_key(ptep, pgste, entry, mm); |
0a61b222 | 829 | pgste = pgste_set_pte(ptep, pgste, entry); |
b2fa47e6 | 830 | pgste_set_unlock(ptep, pgste); |
abf09bed | 831 | } else { |
b2fa47e6 | 832 | *ptep = entry; |
abf09bed | 833 | } |
b2fa47e6 MS |
834 | } |
835 | ||
1da177e4 LT |
836 | /* |
837 | * query functions pte_write/pte_dirty/pte_young only work if | |
838 | * pte_present() is true. Undefined behaviour if not.. | |
839 | */ | |
4448aaf0 | 840 | static inline int pte_write(pte_t pte) |
1da177e4 | 841 | { |
e5098611 | 842 | return (pte_val(pte) & _PAGE_WRITE) != 0; |
1da177e4 LT |
843 | } |
844 | ||
4448aaf0 | 845 | static inline int pte_dirty(pte_t pte) |
1da177e4 | 846 | { |
e5098611 | 847 | return (pte_val(pte) & _PAGE_DIRTY) != 0; |
1da177e4 LT |
848 | } |
849 | ||
4448aaf0 | 850 | static inline int pte_young(pte_t pte) |
1da177e4 | 851 | { |
0944fe3f | 852 | return (pte_val(pte) & _PAGE_YOUNG) != 0; |
1da177e4 LT |
853 | } |
854 | ||
b31288fa KW |
855 | #define __HAVE_ARCH_PTE_UNUSED |
856 | static inline int pte_unused(pte_t pte) | |
857 | { | |
858 | return pte_val(pte) & _PAGE_UNUSED; | |
859 | } | |
860 | ||
1da177e4 LT |
861 | /* |
862 | * pgd/pmd/pte modification functions | |
863 | */ | |
864 | ||
b2fa47e6 | 865 | static inline void pgd_clear(pgd_t *pgd) |
5a216a20 | 866 | { |
6252d702 MS |
867 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
868 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
869 | } |
870 | ||
b2fa47e6 | 871 | static inline void pud_clear(pud_t *pud) |
1da177e4 | 872 | { |
6252d702 MS |
873 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
874 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
875 | } |
876 | ||
b2fa47e6 | 877 | static inline void pmd_clear(pmd_t *pmdp) |
1da177e4 | 878 | { |
e5098611 | 879 | pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
880 | } |
881 | ||
4448aaf0 | 882 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 883 | { |
e5098611 | 884 | pte_val(*ptep) = _PAGE_INVALID; |
1da177e4 LT |
885 | } |
886 | ||
887 | /* | |
888 | * The following pte modification functions only work if | |
889 | * pte_present() is true. Undefined behaviour if not.. | |
890 | */ | |
4448aaf0 | 891 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 892 | { |
138c9021 | 893 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 | 894 | pte_val(pte) |= pgprot_val(newprot); |
0944fe3f MS |
895 | /* |
896 | * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the | |
897 | * invalid bit set, clear it again for readable, young pages | |
898 | */ | |
899 | if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) | |
900 | pte_val(pte) &= ~_PAGE_INVALID; | |
901 | /* | |
902 | * newprot for PAGE_READ and PAGE_WRITE has the page protection | |
903 | * bit set, clear it again for writable, dirty pages | |
904 | */ | |
e5098611 MS |
905 | if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) |
906 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
907 | return pte; |
908 | } | |
909 | ||
4448aaf0 | 910 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 911 | { |
e5098611 MS |
912 | pte_val(pte) &= ~_PAGE_WRITE; |
913 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
914 | return pte; |
915 | } | |
916 | ||
4448aaf0 | 917 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 | 918 | { |
e5098611 MS |
919 | pte_val(pte) |= _PAGE_WRITE; |
920 | if (pte_val(pte) & _PAGE_DIRTY) | |
921 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
922 | return pte; |
923 | } | |
924 | ||
4448aaf0 | 925 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 | 926 | { |
e5098611 MS |
927 | pte_val(pte) &= ~_PAGE_DIRTY; |
928 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
929 | return pte; |
930 | } | |
931 | ||
4448aaf0 | 932 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 | 933 | { |
5614dd92 | 934 | pte_val(pte) |= _PAGE_DIRTY | _PAGE_SOFT_DIRTY; |
e5098611 MS |
935 | if (pte_val(pte) & _PAGE_WRITE) |
936 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
937 | return pte; |
938 | } | |
939 | ||
4448aaf0 | 940 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 | 941 | { |
e5098611 | 942 | pte_val(pte) &= ~_PAGE_YOUNG; |
0944fe3f | 943 | pte_val(pte) |= _PAGE_INVALID; |
1da177e4 LT |
944 | return pte; |
945 | } | |
946 | ||
4448aaf0 | 947 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 | 948 | { |
0944fe3f MS |
949 | pte_val(pte) |= _PAGE_YOUNG; |
950 | if (pte_val(pte) & _PAGE_READ) | |
951 | pte_val(pte) &= ~_PAGE_INVALID; | |
1da177e4 LT |
952 | return pte; |
953 | } | |
954 | ||
7e675137 NP |
955 | static inline pte_t pte_mkspecial(pte_t pte) |
956 | { | |
a08cb629 | 957 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
958 | return pte; |
959 | } | |
960 | ||
84afdcee HC |
961 | #ifdef CONFIG_HUGETLB_PAGE |
962 | static inline pte_t pte_mkhuge(pte_t pte) | |
963 | { | |
e5098611 | 964 | pte_val(pte) |= _PAGE_LARGE; |
84afdcee HC |
965 | return pte; |
966 | } | |
967 | #endif | |
968 | ||
9282ed92 | 969 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 970 | { |
53e857f3 MS |
971 | unsigned long pto = (unsigned long) ptep; |
972 | ||
53e857f3 MS |
973 | /* Invalidation + global TLB flush for the pte */ |
974 | asm volatile( | |
975 | " ipte %2,%3" | |
976 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
977 | } | |
978 | ||
1b948d6c MS |
979 | static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep) |
980 | { | |
981 | unsigned long pto = (unsigned long) ptep; | |
982 | ||
1b948d6c MS |
983 | /* Invalidation + local TLB flush for the pte */ |
984 | asm volatile( | |
985 | " .insn rrf,0xb2210000,%2,%3,0,1" | |
986 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
987 | } | |
988 | ||
cfb0b241 HC |
989 | static inline void __ptep_ipte_range(unsigned long address, int nr, pte_t *ptep) |
990 | { | |
991 | unsigned long pto = (unsigned long) ptep; | |
992 | ||
cfb0b241 HC |
993 | /* Invalidate a range of ptes + global TLB flush of the ptes */ |
994 | do { | |
995 | asm volatile( | |
996 | " .insn rrf,0xb2210000,%2,%0,%1,0" | |
997 | : "+a" (address), "+a" (nr) : "a" (pto) : "memory"); | |
998 | } while (nr != 255); | |
999 | } | |
1000 | ||
53e857f3 MS |
1001 | static inline void ptep_flush_direct(struct mm_struct *mm, |
1002 | unsigned long address, pte_t *ptep) | |
1003 | { | |
1b948d6c MS |
1004 | int active, count; |
1005 | ||
53e857f3 MS |
1006 | if (pte_val(*ptep) & _PAGE_INVALID) |
1007 | return; | |
1b948d6c MS |
1008 | active = (mm == current->active_mm) ? 1 : 0; |
1009 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1010 | if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && | |
1011 | cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) | |
1012 | __ptep_ipte_local(address, ptep); | |
1013 | else | |
1014 | __ptep_ipte(address, ptep); | |
1015 | atomic_sub(0x10000, &mm->context.attach_count); | |
9282ed92 GS |
1016 | } |
1017 | ||
5c474a1e MS |
1018 | static inline void ptep_flush_lazy(struct mm_struct *mm, |
1019 | unsigned long address, pte_t *ptep) | |
1020 | { | |
53e857f3 | 1021 | int active, count; |
5c474a1e | 1022 | |
53e857f3 MS |
1023 | if (pte_val(*ptep) & _PAGE_INVALID) |
1024 | return; | |
1025 | active = (mm == current->active_mm) ? 1 : 0; | |
1026 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1027 | if ((count & 0xffff) <= active) { | |
1028 | pte_val(*ptep) |= _PAGE_INVALID; | |
5c474a1e | 1029 | mm->context.flush_mm = 1; |
53e857f3 MS |
1030 | } else |
1031 | __ptep_ipte(address, ptep); | |
1032 | atomic_sub(0x10000, &mm->context.attach_count); | |
5c474a1e MS |
1033 | } |
1034 | ||
0a61b222 MS |
1035 | /* |
1036 | * Get (and clear) the user dirty bit for a pte. | |
1037 | */ | |
1038 | static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, | |
1039 | unsigned long addr, | |
1040 | pte_t *ptep) | |
1041 | { | |
1042 | pgste_t pgste; | |
1043 | pte_t pte; | |
1044 | int dirty; | |
1045 | ||
1046 | if (!mm_has_pgste(mm)) | |
1047 | return 0; | |
1048 | pgste = pgste_get_lock(ptep); | |
1049 | dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT); | |
1050 | pgste_val(pgste) &= ~PGSTE_UC_BIT; | |
1051 | pte = *ptep; | |
1052 | if (dirty && (pte_val(pte) & _PAGE_PRESENT)) { | |
55dbbdd9 | 1053 | pgste = pgste_ipte_notify(mm, addr, ptep, pgste); |
0a61b222 MS |
1054 | __ptep_ipte(addr, ptep); |
1055 | if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE)) | |
1056 | pte_val(pte) |= _PAGE_PROTECT; | |
1057 | else | |
1058 | pte_val(pte) |= _PAGE_INVALID; | |
1059 | *ptep = pte; | |
1060 | } | |
1061 | pgste_set_unlock(ptep, pgste); | |
1062 | return dirty; | |
1063 | } | |
1064 | ||
0944fe3f MS |
1065 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
1066 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
1067 | unsigned long addr, pte_t *ptep) | |
1068 | { | |
1069 | pgste_t pgste; | |
3e03d4c4 | 1070 | pte_t pte, oldpte; |
0944fe3f MS |
1071 | int young; |
1072 | ||
1073 | if (mm_has_pgste(vma->vm_mm)) { | |
1074 | pgste = pgste_get_lock(ptep); | |
55dbbdd9 | 1075 | pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste); |
0944fe3f MS |
1076 | } |
1077 | ||
3e03d4c4 | 1078 | oldpte = pte = *ptep; |
53e857f3 | 1079 | ptep_flush_direct(vma->vm_mm, addr, ptep); |
0944fe3f MS |
1080 | young = pte_young(pte); |
1081 | pte = pte_mkold(pte); | |
1082 | ||
1083 | if (mm_has_pgste(vma->vm_mm)) { | |
3e03d4c4 | 1084 | pgste = pgste_update_all(&oldpte, pgste, vma->vm_mm); |
0a61b222 | 1085 | pgste = pgste_set_pte(ptep, pgste, pte); |
0944fe3f MS |
1086 | pgste_set_unlock(ptep, pgste); |
1087 | } else | |
1088 | *ptep = pte; | |
1089 | ||
1090 | return young; | |
1091 | } | |
1092 | ||
1093 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
1094 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
1095 | unsigned long address, pte_t *ptep) | |
1096 | { | |
1097 | return ptep_test_and_clear_young(vma, address, ptep); | |
1098 | } | |
1099 | ||
ba8a9229 MS |
1100 | /* |
1101 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
1102 | * both clear the TLB for the unmapped pte. The reason is that | |
1103 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
1104 | * to modify an active pte. The sequence is | |
1105 | * 1) ptep_get_and_clear | |
1106 | * 2) set_pte_at | |
1107 | * 3) flush_tlb_range | |
1108 | * On s390 the tlb needs to get flushed with the modification of the pte | |
1109 | * if the pte is active. The only way how this can be implemented is to | |
1110 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
1111 | * is a nop. | |
1112 | */ | |
1113 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
b2fa47e6 MS |
1114 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
1115 | unsigned long address, pte_t *ptep) | |
1116 | { | |
1117 | pgste_t pgste; | |
1118 | pte_t pte; | |
1119 | ||
d3383632 | 1120 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1121 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1122 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1123 | } |
b2fa47e6 MS |
1124 | |
1125 | pte = *ptep; | |
5c474a1e | 1126 | ptep_flush_lazy(mm, address, ptep); |
e5098611 | 1127 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 MS |
1128 | |
1129 | if (mm_has_pgste(mm)) { | |
65eef335 | 1130 | pgste = pgste_update_all(&pte, pgste, mm); |
b2fa47e6 MS |
1131 | pgste_set_unlock(ptep, pgste); |
1132 | } | |
1133 | return pte; | |
1134 | } | |
1135 | ||
1136 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
1137 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, | |
1138 | unsigned long address, | |
1139 | pte_t *ptep) | |
1140 | { | |
d3383632 | 1141 | pgste_t pgste; |
b2fa47e6 MS |
1142 | pte_t pte; |
1143 | ||
d3383632 MS |
1144 | if (mm_has_pgste(mm)) { |
1145 | pgste = pgste_get_lock(ptep); | |
55dbbdd9 | 1146 | pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1147 | } |
b2fa47e6 MS |
1148 | |
1149 | pte = *ptep; | |
5c474a1e | 1150 | ptep_flush_lazy(mm, address, ptep); |
b56433cb | 1151 | |
3a82603b | 1152 | if (mm_has_pgste(mm)) { |
65eef335 | 1153 | pgste = pgste_update_all(&pte, pgste, mm); |
3a82603b CB |
1154 | pgste_set(ptep, pgste); |
1155 | } | |
b2fa47e6 MS |
1156 | return pte; |
1157 | } | |
1158 | ||
1159 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, | |
1160 | unsigned long address, | |
1161 | pte_t *ptep, pte_t pte) | |
1162 | { | |
b56433cb CB |
1163 | pgste_t pgste; |
1164 | ||
abf09bed | 1165 | if (mm_has_pgste(mm)) { |
d56c893d | 1166 | pgste = pgste_get(ptep); |
65eef335 | 1167 | pgste_set_key(ptep, pgste, pte, mm); |
0a61b222 | 1168 | pgste = pgste_set_pte(ptep, pgste, pte); |
b56433cb | 1169 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1170 | } else |
1171 | *ptep = pte; | |
b2fa47e6 | 1172 | } |
ba8a9229 MS |
1173 | |
1174 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
1175 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
1176 | unsigned long address, pte_t *ptep) | |
1177 | { | |
b2fa47e6 MS |
1178 | pgste_t pgste; |
1179 | pte_t pte; | |
1180 | ||
d3383632 | 1181 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1182 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1183 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
d3383632 | 1184 | } |
b2fa47e6 MS |
1185 | |
1186 | pte = *ptep; | |
53e857f3 | 1187 | ptep_flush_direct(vma->vm_mm, address, ptep); |
e5098611 | 1188 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 MS |
1189 | |
1190 | if (mm_has_pgste(vma->vm_mm)) { | |
b31288fa KW |
1191 | if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) == |
1192 | _PGSTE_GPS_USAGE_UNUSED) | |
1193 | pte_val(pte) |= _PAGE_UNUSED; | |
65eef335 | 1194 | pgste = pgste_update_all(&pte, pgste, vma->vm_mm); |
b2fa47e6 MS |
1195 | pgste_set_unlock(ptep, pgste); |
1196 | } | |
1da177e4 LT |
1197 | return pte; |
1198 | } | |
1199 | ||
ba8a9229 MS |
1200 | /* |
1201 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
1202 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
1203 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
1204 | * cannot be accessed while the batched unmap is running. In this case | |
1205 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
1206 | */ | |
1207 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
1208 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
b2fa47e6 | 1209 | unsigned long address, |
ba8a9229 | 1210 | pte_t *ptep, int full) |
1da177e4 | 1211 | { |
b2fa47e6 MS |
1212 | pgste_t pgste; |
1213 | pte_t pte; | |
1214 | ||
a055f66a | 1215 | if (!full && mm_has_pgste(mm)) { |
b2fa47e6 | 1216 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1217 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1218 | } |
ba8a9229 | 1219 | |
b2fa47e6 MS |
1220 | pte = *ptep; |
1221 | if (!full) | |
5c474a1e | 1222 | ptep_flush_lazy(mm, address, ptep); |
e5098611 | 1223 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 | 1224 | |
a055f66a | 1225 | if (!full && mm_has_pgste(mm)) { |
65eef335 | 1226 | pgste = pgste_update_all(&pte, pgste, mm); |
b2fa47e6 MS |
1227 | pgste_set_unlock(ptep, pgste); |
1228 | } | |
ba8a9229 | 1229 | return pte; |
1da177e4 LT |
1230 | } |
1231 | ||
ba8a9229 | 1232 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
b2fa47e6 MS |
1233 | static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, |
1234 | unsigned long address, pte_t *ptep) | |
1235 | { | |
1236 | pgste_t pgste; | |
1237 | pte_t pte = *ptep; | |
1238 | ||
1239 | if (pte_write(pte)) { | |
d3383632 | 1240 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1241 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1242 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1243 | } |
b2fa47e6 | 1244 | |
5c474a1e | 1245 | ptep_flush_lazy(mm, address, ptep); |
abf09bed | 1246 | pte = pte_wrprotect(pte); |
b2fa47e6 | 1247 | |
abf09bed | 1248 | if (mm_has_pgste(mm)) { |
0a61b222 | 1249 | pgste = pgste_set_pte(ptep, pgste, pte); |
b2fa47e6 | 1250 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1251 | } else |
1252 | *ptep = pte; | |
b2fa47e6 MS |
1253 | } |
1254 | return pte; | |
1255 | } | |
ba8a9229 MS |
1256 | |
1257 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
b2fa47e6 MS |
1258 | static inline int ptep_set_access_flags(struct vm_area_struct *vma, |
1259 | unsigned long address, pte_t *ptep, | |
1260 | pte_t entry, int dirty) | |
1261 | { | |
1262 | pgste_t pgste; | |
395e6aa1 | 1263 | pte_t oldpte; |
b2fa47e6 | 1264 | |
395e6aa1 MS |
1265 | oldpte = *ptep; |
1266 | if (pte_same(oldpte, entry)) | |
b2fa47e6 | 1267 | return 0; |
d3383632 | 1268 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1269 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1270 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
d3383632 | 1271 | } |
b2fa47e6 | 1272 | |
53e857f3 | 1273 | ptep_flush_direct(vma->vm_mm, address, ptep); |
b2fa47e6 | 1274 | |
abf09bed | 1275 | if (mm_has_pgste(vma->vm_mm)) { |
395e6aa1 MS |
1276 | if (pte_val(oldpte) & _PAGE_INVALID) |
1277 | pgste_set_key(ptep, pgste, entry, vma->vm_mm); | |
0a61b222 | 1278 | pgste = pgste_set_pte(ptep, pgste, entry); |
b2fa47e6 | 1279 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1280 | } else |
1281 | *ptep = entry; | |
b2fa47e6 MS |
1282 | return 1; |
1283 | } | |
1da177e4 | 1284 | |
1da177e4 LT |
1285 | /* |
1286 | * Conversion functions: convert a page and protection to a page entry, | |
1287 | * and a page entry and page directory to the page they refer to. | |
1288 | */ | |
1289 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1290 | { | |
1291 | pte_t __pte; | |
1292 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
0944fe3f | 1293 | return pte_mkyoung(__pte); |
1da177e4 LT |
1294 | } |
1295 | ||
2dcea57a HC |
1296 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1297 | { | |
0b2b6e1d | 1298 | unsigned long physpage = page_to_phys(page); |
abf09bed | 1299 | pte_t __pte = mk_pte_phys(physpage, pgprot); |
1da177e4 | 1300 | |
e5098611 MS |
1301 | if (pte_write(__pte) && PageDirty(page)) |
1302 | __pte = pte_mkdirty(__pte); | |
abf09bed | 1303 | return __pte; |
2dcea57a HC |
1304 | } |
1305 | ||
190a1d72 MS |
1306 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1307 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
1308 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1309 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1310 | |
190a1d72 MS |
1311 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1312 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1313 | |
190a1d72 MS |
1314 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1315 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 1316 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1317 | |
5a216a20 MS |
1318 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
1319 | { | |
6252d702 MS |
1320 | pud_t *pud = (pud_t *) pgd; |
1321 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1322 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
1323 | return pud + pud_index(address); |
1324 | } | |
1da177e4 | 1325 | |
190a1d72 | 1326 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1327 | { |
6252d702 MS |
1328 | pmd_t *pmd = (pmd_t *) pud; |
1329 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
1330 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1331 | return pmd + pmd_index(address); |
1da177e4 LT |
1332 | } |
1333 | ||
190a1d72 MS |
1334 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1335 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1336 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1337 | |
152125b7 | 1338 | #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) |
1da177e4 | 1339 | |
190a1d72 MS |
1340 | /* Find an entry in the lowest level page table.. */ |
1341 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1342 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 | 1343 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1da177e4 | 1344 | #define pte_unmap(pte) do { } while (0) |
1da177e4 | 1345 | |
106c992a | 1346 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) |
1ae1c1d0 GS |
1347 | static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) |
1348 | { | |
d8e7a33d | 1349 | /* |
e5098611 | 1350 | * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx) |
d8e7a33d GS |
1351 | * Convert to segment table entry format. |
1352 | */ | |
1353 | if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) | |
1354 | return pgprot_val(SEGMENT_NONE); | |
e5098611 MS |
1355 | if (pgprot_val(pgprot) == pgprot_val(PAGE_READ)) |
1356 | return pgprot_val(SEGMENT_READ); | |
1357 | return pgprot_val(SEGMENT_WRITE); | |
1ae1c1d0 GS |
1358 | } |
1359 | ||
152125b7 | 1360 | static inline pmd_t pmd_wrprotect(pmd_t pmd) |
0944fe3f | 1361 | { |
152125b7 MS |
1362 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; |
1363 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1364 | return pmd; | |
1365 | } | |
1366 | ||
1367 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
1368 | { | |
1369 | pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; | |
1370 | if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1371 | return pmd; | |
1372 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1373 | return pmd; | |
1374 | } | |
1375 | ||
1376 | static inline pmd_t pmd_mkclean(pmd_t pmd) | |
1377 | { | |
1378 | if (pmd_large(pmd)) { | |
1379 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; | |
0944fe3f | 1380 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; |
152125b7 MS |
1381 | } |
1382 | return pmd; | |
1383 | } | |
1384 | ||
1385 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
1386 | { | |
1387 | if (pmd_large(pmd)) { | |
5614dd92 MS |
1388 | pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY | |
1389 | _SEGMENT_ENTRY_SOFT_DIRTY; | |
152125b7 MS |
1390 | if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) |
1391 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1392 | } | |
1393 | return pmd; | |
1394 | } | |
1395 | ||
1396 | static inline pmd_t pmd_mkyoung(pmd_t pmd) | |
1397 | { | |
1398 | if (pmd_large(pmd)) { | |
0944fe3f | 1399 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
152125b7 MS |
1400 | if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) |
1401 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; | |
0944fe3f | 1402 | } |
0944fe3f MS |
1403 | return pmd; |
1404 | } | |
1405 | ||
1406 | static inline pmd_t pmd_mkold(pmd_t pmd) | |
1407 | { | |
152125b7 | 1408 | if (pmd_large(pmd)) { |
0944fe3f MS |
1409 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; |
1410 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1411 | } | |
0944fe3f MS |
1412 | return pmd; |
1413 | } | |
1414 | ||
1ae1c1d0 GS |
1415 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
1416 | { | |
152125b7 MS |
1417 | if (pmd_large(pmd)) { |
1418 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | | |
1419 | _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | | |
fecffad2 | 1420 | _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SOFT_DIRTY; |
152125b7 MS |
1421 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1422 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1423 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1424 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) | |
1425 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1426 | return pmd; | |
1427 | } | |
1428 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN; | |
1ae1c1d0 GS |
1429 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1430 | return pmd; | |
1431 | } | |
1432 | ||
106c992a | 1433 | static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) |
1ae1c1d0 | 1434 | { |
106c992a GS |
1435 | pmd_t __pmd; |
1436 | pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); | |
152125b7 | 1437 | return __pmd; |
1ae1c1d0 GS |
1438 | } |
1439 | ||
106c992a GS |
1440 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ |
1441 | ||
1b948d6c MS |
1442 | static inline void __pmdp_csp(pmd_t *pmdp) |
1443 | { | |
1444 | register unsigned long reg2 asm("2") = pmd_val(*pmdp); | |
1445 | register unsigned long reg3 asm("3") = pmd_val(*pmdp) | | |
1446 | _SEGMENT_ENTRY_INVALID; | |
1447 | register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5; | |
1448 | ||
1449 | asm volatile( | |
1450 | " csp %1,%3" | |
1451 | : "=m" (*pmdp) | |
1452 | : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc"); | |
1453 | } | |
1454 | ||
1455 | static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp) | |
1456 | { | |
1457 | unsigned long sto; | |
1458 | ||
1459 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1460 | asm volatile( | |
1461 | " .insn rrf,0xb98e0000,%2,%3,0,0" | |
1462 | : "=m" (*pmdp) | |
1463 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1464 | : "cc" ); | |
1465 | } | |
1466 | ||
1467 | static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp) | |
1468 | { | |
1469 | unsigned long sto; | |
1470 | ||
1471 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1472 | asm volatile( | |
1473 | " .insn rrf,0xb98e0000,%2,%3,0,1" | |
1474 | : "=m" (*pmdp) | |
1475 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1476 | : "cc" ); | |
1477 | } | |
1478 | ||
1479 | static inline void pmdp_flush_direct(struct mm_struct *mm, | |
1480 | unsigned long address, pmd_t *pmdp) | |
1481 | { | |
1482 | int active, count; | |
1483 | ||
1484 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) | |
1485 | return; | |
1486 | if (!MACHINE_HAS_IDTE) { | |
1487 | __pmdp_csp(pmdp); | |
1488 | return; | |
1489 | } | |
1490 | active = (mm == current->active_mm) ? 1 : 0; | |
1491 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1492 | if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && | |
1493 | cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) | |
1494 | __pmdp_idte_local(address, pmdp); | |
1495 | else | |
1496 | __pmdp_idte(address, pmdp); | |
1497 | atomic_sub(0x10000, &mm->context.attach_count); | |
1498 | } | |
1499 | ||
3eabaee9 MS |
1500 | static inline void pmdp_flush_lazy(struct mm_struct *mm, |
1501 | unsigned long address, pmd_t *pmdp) | |
1502 | { | |
53e857f3 | 1503 | int active, count; |
3eabaee9 | 1504 | |
1b948d6c MS |
1505 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) |
1506 | return; | |
53e857f3 MS |
1507 | active = (mm == current->active_mm) ? 1 : 0; |
1508 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1509 | if ((count & 0xffff) <= active) { | |
1510 | pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID; | |
3eabaee9 | 1511 | mm->context.flush_mm = 1; |
1b948d6c MS |
1512 | } else if (MACHINE_HAS_IDTE) |
1513 | __pmdp_idte(address, pmdp); | |
1514 | else | |
1515 | __pmdp_csp(pmdp); | |
53e857f3 | 1516 | atomic_sub(0x10000, &mm->context.attach_count); |
3eabaee9 MS |
1517 | } |
1518 | ||
106c992a GS |
1519 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1520 | ||
1521 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
6b0b50b0 AK |
1522 | extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
1523 | pgtable_t pgtable); | |
106c992a GS |
1524 | |
1525 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
6b0b50b0 | 1526 | extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
106c992a | 1527 | |
106c992a GS |
1528 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
1529 | pmd_t *pmdp, pmd_t entry) | |
1530 | { | |
106c992a GS |
1531 | *pmdp = entry; |
1532 | } | |
1533 | ||
1534 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1535 | { | |
1536 | pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; | |
152125b7 MS |
1537 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
1538 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1ae1c1d0 GS |
1539 | return pmd; |
1540 | } | |
1541 | ||
1ae1c1d0 GS |
1542 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1543 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1544 | unsigned long address, pmd_t *pmdp) | |
1545 | { | |
0944fe3f | 1546 | pmd_t pmd; |
1ae1c1d0 | 1547 | |
0944fe3f | 1548 | pmd = *pmdp; |
1b948d6c | 1549 | pmdp_flush_direct(vma->vm_mm, address, pmdp); |
0944fe3f MS |
1550 | *pmdp = pmd_mkold(pmd); |
1551 | return pmd_young(pmd); | |
1ae1c1d0 GS |
1552 | } |
1553 | ||
8809aa2d AK |
1554 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
1555 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
1556 | unsigned long address, pmd_t *pmdp) | |
1ae1c1d0 GS |
1557 | { |
1558 | pmd_t pmd = *pmdp; | |
1559 | ||
1b948d6c | 1560 | pmdp_flush_direct(mm, address, pmdp); |
1ae1c1d0 GS |
1561 | pmd_clear(pmdp); |
1562 | return pmd; | |
1563 | } | |
1564 | ||
8809aa2d AK |
1565 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1566 | static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm, | |
1567 | unsigned long address, | |
1568 | pmd_t *pmdp, int full) | |
fcbe08d6 MS |
1569 | { |
1570 | pmd_t pmd = *pmdp; | |
1571 | ||
1572 | if (!full) | |
1573 | pmdp_flush_lazy(mm, address, pmdp); | |
1574 | pmd_clear(pmdp); | |
1575 | return pmd; | |
1576 | } | |
1577 | ||
8809aa2d AK |
1578 | #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH |
1579 | static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, | |
1580 | unsigned long address, pmd_t *pmdp) | |
1ae1c1d0 | 1581 | { |
8809aa2d | 1582 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
1ae1c1d0 GS |
1583 | } |
1584 | ||
1585 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1586 | static inline void pmdp_invalidate(struct vm_area_struct *vma, | |
1587 | unsigned long address, pmd_t *pmdp) | |
1588 | { | |
1b948d6c | 1589 | pmdp_flush_direct(vma->vm_mm, address, pmdp); |
1ae1c1d0 GS |
1590 | } |
1591 | ||
be328650 GS |
1592 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1593 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
1594 | unsigned long address, pmd_t *pmdp) | |
1595 | { | |
1596 | pmd_t pmd = *pmdp; | |
1597 | ||
1598 | if (pmd_write(pmd)) { | |
1b948d6c | 1599 | pmdp_flush_direct(mm, address, pmdp); |
be328650 GS |
1600 | set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); |
1601 | } | |
1602 | } | |
1603 | ||
f28b6ff8 AK |
1604 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1605 | unsigned long address, | |
1606 | pmd_t *pmdp) | |
1607 | { | |
8809aa2d | 1608 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
f28b6ff8 AK |
1609 | } |
1610 | #define pmdp_collapse_flush pmdp_collapse_flush | |
1611 | ||
1ae1c1d0 GS |
1612 | #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) |
1613 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) | |
1614 | ||
1615 | static inline int pmd_trans_huge(pmd_t pmd) | |
1616 | { | |
1617 | return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; | |
1618 | } | |
1619 | ||
1620 | static inline int has_transparent_hugepage(void) | |
1621 | { | |
1622 | return MACHINE_HAS_HPAGE ? 1 : 0; | |
1623 | } | |
75077afb GS |
1624 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1625 | ||
1da177e4 | 1626 | /* |
1da177e4 LT |
1627 | * 64 bit swap entry format: |
1628 | * A page-table entry has some bits we have to treat in a special way. | |
4e0a6412 | 1629 | * Bits 52 and bit 55 have to be zero, otherwise a specification |
1da177e4 | 1630 | * exception will occur instead of a page translation exception. The |
4e0a6412 | 1631 | * specification exception has the bad habit not to store necessary |
1da177e4 | 1632 | * information in the lowcore. |
a1c843b8 MS |
1633 | * Bits 54 and 63 are used to indicate the page type. |
1634 | * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 | |
1635 | * This leaves the bits 0-51 and bits 56-62 to store type and offset. | |
1636 | * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 | |
1637 | * for the offset. | |
1638 | * | offset |01100|type |00| | |
1639 | * |0000000000111111111122222222223333333333444444444455|55555|55566|66| | |
1640 | * |0123456789012345678901234567890123456789012345678901|23456|78901|23| | |
1da177e4 | 1641 | */ |
5a79859a | 1642 | |
a1c843b8 MS |
1643 | #define __SWP_OFFSET_MASK ((1UL << 52) - 1) |
1644 | #define __SWP_OFFSET_SHIFT 12 | |
1645 | #define __SWP_TYPE_MASK ((1UL << 5) - 1) | |
1646 | #define __SWP_TYPE_SHIFT 2 | |
5a79859a | 1647 | |
4448aaf0 | 1648 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1649 | { |
1650 | pte_t pte; | |
a1c843b8 MS |
1651 | |
1652 | pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; | |
1653 | pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; | |
1654 | pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; | |
1da177e4 LT |
1655 | return pte; |
1656 | } | |
1657 | ||
a1c843b8 MS |
1658 | static inline unsigned long __swp_type(swp_entry_t entry) |
1659 | { | |
1660 | return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; | |
1661 | } | |
1662 | ||
1663 | static inline unsigned long __swp_offset(swp_entry_t entry) | |
1664 | { | |
1665 | return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; | |
1666 | } | |
1667 | ||
1668 | static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) | |
1669 | { | |
1670 | return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; | |
1671 | } | |
1da177e4 LT |
1672 | |
1673 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1674 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1675 | ||
1da177e4 LT |
1676 | #endif /* !__ASSEMBLY__ */ |
1677 | ||
1678 | #define kern_addr_valid(addr) (1) | |
1679 | ||
17f34580 HC |
1680 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1681 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1682 | extern int s390_enable_sie(void); |
3ac8e380 | 1683 | extern int s390_enable_skey(void); |
a13cff31 | 1684 | extern void s390_reset_cmma(struct mm_struct *mm); |
f4eb07c1 | 1685 | |
1f6b83e5 MS |
1686 | /* s390 has a private copy of get unmapped area to deal with cache synonyms */ |
1687 | #define HAVE_ARCH_UNMAPPED_AREA | |
1688 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
1689 | ||
1da177e4 LT |
1690 | /* |
1691 | * No page table caches to initialise | |
1692 | */ | |
765a0cac HC |
1693 | static inline void pgtable_cache_init(void) { } |
1694 | static inline void check_pgt_cache(void) { } | |
1da177e4 | 1695 | |
1da177e4 LT |
1696 | #include <asm-generic/pgtable.h> |
1697 | ||
1698 | #endif /* _S390_PAGE_H */ |