Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999, 2000 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com) |
5 | * Ulrich Weigand (weigand@de.ibm.com) | |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
7 | * | |
8 | * Derived from "include/asm-i386/pgtable.h" | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_S390_PGTABLE_H | |
12 | #define _ASM_S390_PGTABLE_H | |
13 | ||
1da177e4 | 14 | /* |
a1c843b8 MS |
15 | * The Linux memory management assumes a three-level page table setup. |
16 | * For s390 64 bit we use up to four of the five levels the hardware | |
17 | * provides (region first tables are not used). | |
1da177e4 LT |
18 | * |
19 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
20 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
21 | * into the pgd entry) | |
22 | * | |
23 | * This file contains the functions and defines necessary to modify and use | |
24 | * the S390 page table tree. | |
25 | */ | |
26 | #ifndef __ASSEMBLY__ | |
9789db08 | 27 | #include <linux/sched.h> |
2dcea57a | 28 | #include <linux/mm_types.h> |
abf09bed | 29 | #include <linux/page-flags.h> |
527e30b4 | 30 | #include <linux/radix-tree.h> |
37cd944c | 31 | #include <linux/atomic.h> |
1da177e4 | 32 | #include <asm/bug.h> |
b2fa47e6 | 33 | #include <asm/page.h> |
1da177e4 | 34 | |
0ccb32c9 | 35 | extern pgd_t swapper_pg_dir[]; |
1da177e4 | 36 | extern void paging_init(void); |
2b67fc46 | 37 | extern void vmem_map_init(void); |
e8a97e42 HC |
38 | pmd_t *vmem_pmd_alloc(void); |
39 | pte_t *vmem_pte_alloc(void); | |
1da177e4 | 40 | |
37cd944c HC |
41 | enum { |
42 | PG_DIRECT_MAP_4K = 0, | |
43 | PG_DIRECT_MAP_1M, | |
44 | PG_DIRECT_MAP_2G, | |
45 | PG_DIRECT_MAP_MAX | |
46 | }; | |
47 | ||
48 | extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX]; | |
49 | ||
50 | static inline void update_page_count(int level, long count) | |
51 | { | |
52 | if (IS_ENABLED(CONFIG_PROC_FS)) | |
53 | atomic_long_add(count, &direct_pages_count[level]); | |
54 | } | |
55 | ||
56 | struct seq_file; | |
57 | void arch_report_meminfo(struct seq_file *m); | |
58 | ||
1da177e4 LT |
59 | /* |
60 | * The S390 doesn't have any external MMU info: the kernel page | |
61 | * tables contain all the necessary information. | |
62 | */ | |
4b3073e1 | 63 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
b113da65 | 64 | #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) |
1da177e4 LT |
65 | |
66 | /* | |
238ec4ef | 67 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
68 | * for zero-mapped memory areas etc.. |
69 | */ | |
238ec4ef MS |
70 | |
71 | extern unsigned long empty_zero_page; | |
72 | extern unsigned long zero_page_mask; | |
73 | ||
74 | #define ZERO_PAGE(vaddr) \ | |
75 | (virt_to_page((void *)(empty_zero_page + \ | |
76 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
816422ad | 77 | #define __HAVE_COLOR_ZERO_PAGE |
238ec4ef | 78 | |
4f2e2903 | 79 | /* TODO: s390 cannot support io_remap_pfn_range... */ |
1da177e4 LT |
80 | #endif /* !__ASSEMBLY__ */ |
81 | ||
82 | /* | |
83 | * PMD_SHIFT determines the size of the area a second-level page | |
84 | * table can map | |
85 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
86 | */ | |
5a79859a HC |
87 | #define PMD_SHIFT 20 |
88 | #define PUD_SHIFT 31 | |
89 | #define PGDIR_SHIFT 42 | |
1da177e4 LT |
90 | |
91 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
92 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
93 | #define PUD_SIZE (1UL << PUD_SHIFT) |
94 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
95 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
96 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
97 | |
98 | /* | |
99 | * entries per page directory level: the S390 is two-level, so | |
100 | * we don't really have any PMD directory physically. | |
101 | * for S390 segment-table entries are combined to one PGD | |
102 | * that leads to 1024 pte per pgd | |
103 | */ | |
146e4b3c | 104 | #define PTRS_PER_PTE 256 |
146e4b3c | 105 | #define PTRS_PER_PMD 2048 |
5a216a20 | 106 | #define PTRS_PER_PUD 2048 |
146e4b3c | 107 | #define PTRS_PER_PGD 2048 |
1da177e4 | 108 | |
d016bf7e | 109 | #define FIRST_USER_ADDRESS 0UL |
d455a369 | 110 | |
1da177e4 LT |
111 | #define pte_ERROR(e) \ |
112 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
113 | #define pmd_ERROR(e) \ | |
114 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
115 | #define pud_ERROR(e) \ |
116 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
117 | #define pgd_ERROR(e) \ |
118 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
119 | ||
120 | #ifndef __ASSEMBLY__ | |
121 | /* | |
a1c843b8 MS |
122 | * The vmalloc and module area will always be on the topmost area of the |
123 | * kernel mapping. We reserve 128GB (64bit) for vmalloc and modules. | |
c972cc60 HC |
124 | * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where |
125 | * modules will reside. That makes sure that inter module branches always | |
126 | * happen without trampolines and in addition the placement within a 2GB frame | |
127 | * is branch prediction unit friendly. | |
8b62bc96 | 128 | */ |
239a6425 | 129 | extern unsigned long VMALLOC_START; |
14045ebf MS |
130 | extern unsigned long VMALLOC_END; |
131 | extern struct page *vmemmap; | |
239a6425 | 132 | |
14045ebf | 133 | #define VMEM_MAX_PHYS ((unsigned long) vmemmap) |
5fd9c6e2 | 134 | |
c972cc60 HC |
135 | extern unsigned long MODULES_VADDR; |
136 | extern unsigned long MODULES_END; | |
137 | #define MODULES_VADDR MODULES_VADDR | |
138 | #define MODULES_END MODULES_END | |
139 | #define MODULES_LEN (1UL << 31) | |
c972cc60 | 140 | |
c933146a HC |
141 | static inline int is_module_addr(void *addr) |
142 | { | |
c933146a HC |
143 | BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); |
144 | if (addr < (void *)MODULES_VADDR) | |
145 | return 0; | |
146 | if (addr > (void *)MODULES_END) | |
147 | return 0; | |
c933146a HC |
148 | return 1; |
149 | } | |
150 | ||
1da177e4 | 151 | /* |
1da177e4 | 152 | * A 64 bit pagetable entry of S390 has following format: |
6a985c61 | 153 | * | PFRA |0IPC| OS | |
1da177e4 LT |
154 | * 0000000000111111111122222222223333333333444444444455555555556666 |
155 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
156 | * | |
157 | * I Page-Invalid Bit: Page is not available for address-translation | |
158 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 159 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
160 | * |
161 | * A 64 bit segmenttable entry of S390 has following format: | |
162 | * | P-table origin | TT | |
163 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
164 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
165 | * | |
166 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
167 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
168 | * P Page-Protection Bit: Store access not possible for page | |
169 | * TT Type 00 | |
170 | * | |
171 | * A 64 bit region table entry of S390 has following format: | |
172 | * | S-table origin | TF TTTL | |
173 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
174 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
175 | * | |
176 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
177 | * TT Type 01 | |
178 | * TF | |
190a1d72 | 179 | * TL Table length |
1da177e4 LT |
180 | * |
181 | * The 64 bit regiontable origin of S390 has following format: | |
182 | * | region table origon | DTTL | |
183 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
184 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
185 | * | |
186 | * X Space-Switch event: | |
187 | * G Segment-Invalid Bit: | |
188 | * P Private-Space Bit: | |
189 | * S Storage-Alteration: | |
190 | * R Real space | |
191 | * TL Table-Length: | |
192 | * | |
193 | * A storage key has the following format: | |
194 | * | ACC |F|R|C|0| | |
195 | * 0 3 4 5 6 7 | |
196 | * ACC: access key | |
197 | * F : fetch protection bit | |
198 | * R : referenced bit | |
199 | * C : changed bit | |
200 | */ | |
201 | ||
202 | /* Hardware bits in the page table entry */ | |
e5098611 | 203 | #define _PAGE_PROTECT 0x200 /* HW read-only bit */ |
83377484 | 204 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ |
e5098611 | 205 | #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ |
3610cce8 MS |
206 | |
207 | /* Software bits in the page table entry */ | |
e5098611 | 208 | #define _PAGE_PRESENT 0x001 /* SW pte present bit */ |
e5098611 MS |
209 | #define _PAGE_YOUNG 0x004 /* SW pte young bit */ |
210 | #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ | |
0944fe3f MS |
211 | #define _PAGE_READ 0x010 /* SW pte read bit */ |
212 | #define _PAGE_WRITE 0x020 /* SW pte write bit */ | |
213 | #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ | |
b31288fa | 214 | #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ |
a08cb629 | 215 | #define __HAVE_ARCH_PTE_SPECIAL |
1da177e4 | 216 | |
5614dd92 MS |
217 | #ifdef CONFIG_MEM_SOFT_DIRTY |
218 | #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ | |
219 | #else | |
220 | #define _PAGE_SOFT_DIRTY 0x000 | |
221 | #endif | |
222 | ||
138c9021 | 223 | /* Set of bits not changed in pte_modify */ |
6a5c1482 | 224 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ |
5614dd92 | 225 | _PAGE_YOUNG | _PAGE_SOFT_DIRTY) |
53492b1d | 226 | |
83377484 | 227 | /* |
6e76d4b2 KS |
228 | * handle_pte_fault uses pte_present and pte_none to find out the pte type |
229 | * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to | |
230 | * distinguish present from not-present ptes. It is changed only with the page | |
231 | * table lock held. | |
83377484 | 232 | * |
e5098611 | 233 | * The following table gives the different possible bit combinations for |
a1c843b8 MS |
234 | * the pte hardware and software bits in the last 12 bits of a pte |
235 | * (. unassigned bit, x don't care, t swap type): | |
83377484 | 236 | * |
0944fe3f MS |
237 | * 842100000000 |
238 | * 000084210000 | |
239 | * 000000008421 | |
a1c843b8 MS |
240 | * .IR.uswrdy.p |
241 | * empty .10.00000000 | |
242 | * swap .11..ttttt.0 | |
243 | * prot-none, clean, old .11.xx0000.1 | |
244 | * prot-none, clean, young .11.xx0001.1 | |
bc29b7ac GS |
245 | * prot-none, dirty, old .11.xx0010.1 |
246 | * prot-none, dirty, young .11.xx0011.1 | |
a1c843b8 MS |
247 | * read-only, clean, old .11.xx0100.1 |
248 | * read-only, clean, young .01.xx0101.1 | |
249 | * read-only, dirty, old .11.xx0110.1 | |
250 | * read-only, dirty, young .01.xx0111.1 | |
251 | * read-write, clean, old .11.xx1100.1 | |
252 | * read-write, clean, young .01.xx1101.1 | |
253 | * read-write, dirty, old .10.xx1110.1 | |
254 | * read-write, dirty, young .00.xx1111.1 | |
255 | * HW-bits: R read-only, I invalid | |
256 | * SW-bits: p present, y young, d dirty, r read, w write, s special, | |
257 | * u unused, l large | |
e5098611 | 258 | * |
a1c843b8 MS |
259 | * pte_none is true for the bit pattern .10.00000000, pte == 0x400 |
260 | * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 | |
261 | * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 | |
83377484 MS |
262 | */ |
263 | ||
3610cce8 MS |
264 | /* Bits in the segment/region table address-space-control-element */ |
265 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
266 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
267 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
268 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
269 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
270 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
271 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
272 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
273 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
274 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
275 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
276 | ||
277 | /* Bits in the region table entry */ | |
278 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
e5098611 | 279 | #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ |
4be130a0 | 280 | #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ |
e5098611 | 281 | #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ |
3610cce8 MS |
282 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ |
283 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
284 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
285 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
286 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
287 | ||
288 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
e5098611 | 289 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) |
3610cce8 | 290 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) |
e5098611 | 291 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) |
3610cce8 | 292 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) |
e5098611 | 293 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) |
3610cce8 | 294 | |
9e20b4da HC |
295 | #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ |
296 | #define _REGION3_ENTRY_ORIGIN ~0x7ffUL/* region third table origin */ | |
297 | ||
2dffdcba HC |
298 | #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ |
299 | #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ | |
300 | #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ | |
301 | #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ | |
302 | #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ | |
303 | ||
304 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
305 | #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ | |
306 | #else | |
307 | #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ | |
308 | #endif | |
309 | ||
d08de8e2 GS |
310 | #define _REGION_ENTRY_BITS 0xfffffffffffff227UL |
311 | #define _REGION_ENTRY_BITS_LARGE 0xffffffff8000fe27UL | |
312 | ||
1da177e4 | 313 | /* Bits in the segment table entry */ |
0944fe3f | 314 | #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL |
152125b7 | 315 | #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL |
ea81531d | 316 | #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ |
3610cce8 | 317 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
e5098611 MS |
318 | #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ |
319 | #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ | |
1da177e4 | 320 | |
3610cce8 | 321 | #define _SEGMENT_ENTRY (0) |
e5098611 | 322 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) |
3610cce8 | 323 | |
152125b7 MS |
324 | #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ |
325 | #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ | |
152125b7 | 326 | #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ |
bc29b7ac GS |
327 | #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ |
328 | #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ | |
0944fe3f | 329 | |
5614dd92 MS |
330 | #ifdef CONFIG_MEM_SOFT_DIRTY |
331 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ | |
332 | #else | |
333 | #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ | |
334 | #endif | |
335 | ||
0944fe3f | 336 | /* |
2dffdcba HC |
337 | * Segment table and region3 table entry encoding |
338 | * (R = read-only, I = invalid, y = young bit): | |
bc29b7ac | 339 | * dy..R...I...wr |
152125b7 MS |
340 | * prot-none, clean, old 00..1...1...00 |
341 | * prot-none, clean, young 01..1...1...00 | |
342 | * prot-none, dirty, old 10..1...1...00 | |
343 | * prot-none, dirty, young 11..1...1...00 | |
bc29b7ac GS |
344 | * read-only, clean, old 00..1...1...01 |
345 | * read-only, clean, young 01..1...0...01 | |
346 | * read-only, dirty, old 10..1...1...01 | |
347 | * read-only, dirty, young 11..1...0...01 | |
152125b7 MS |
348 | * read-write, clean, old 00..1...1...11 |
349 | * read-write, clean, young 01..1...0...11 | |
350 | * read-write, dirty, old 10..0...1...11 | |
351 | * read-write, dirty, young 11..0...0...11 | |
0944fe3f MS |
352 | * The segment table origin is used to distinguish empty (origin==0) from |
353 | * read-write, old segment table entries (origin!=0) | |
a1c843b8 MS |
354 | * HW-bits: R read-only, I invalid |
355 | * SW-bits: y young, d dirty, r read, w write | |
0944fe3f | 356 | */ |
e5098611 | 357 | |
6c61cfe9 | 358 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
359 | #define PGSTE_ACC_BITS 0xf000000000000000UL |
360 | #define PGSTE_FP_BIT 0x0800000000000000UL | |
361 | #define PGSTE_PCL_BIT 0x0080000000000000UL | |
362 | #define PGSTE_HR_BIT 0x0040000000000000UL | |
363 | #define PGSTE_HC_BIT 0x0020000000000000UL | |
364 | #define PGSTE_GR_BIT 0x0004000000000000UL | |
365 | #define PGSTE_GC_BIT 0x0002000000000000UL | |
0a61b222 MS |
366 | #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ |
367 | #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ | |
4be130a0 | 368 | #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ |
6c61cfe9 | 369 | |
b31288fa KW |
370 | /* Guest Page State used for virtualization */ |
371 | #define _PGSTE_GPS_ZERO 0x0000000080000000UL | |
372 | #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL | |
373 | #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL | |
374 | #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL | |
375 | ||
1da177e4 | 376 | /* |
3610cce8 MS |
377 | * A user page table pointer has the space-switch-event bit, the |
378 | * private-space-control bit and the storage-alteration-event-control | |
379 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 380 | */ |
3610cce8 MS |
381 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
382 | _ASCE_ALT_EVENT) | |
1da177e4 | 383 | |
1da177e4 | 384 | /* |
9282ed92 | 385 | * Page protection definitions. |
1da177e4 | 386 | */ |
bc29b7ac | 387 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) |
0944fe3f MS |
388 | #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \ |
389 | _PAGE_INVALID | _PAGE_PROTECT) | |
390 | #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
391 | _PAGE_INVALID | _PAGE_PROTECT) | |
392 | ||
393 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
394 | _PAGE_YOUNG | _PAGE_DIRTY) | |
395 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
396 | _PAGE_YOUNG | _PAGE_DIRTY) | |
397 | #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ | |
398 | _PAGE_PROTECT) | |
1da177e4 LT |
399 | |
400 | /* | |
043d0708 MS |
401 | * On s390 the page table entry has an invalid bit and a read-only bit. |
402 | * Read permission implies execute permission and write permission | |
403 | * implies read permission. | |
1da177e4 LT |
404 | */ |
405 | /*xwr*/ | |
9282ed92 | 406 | #define __P000 PAGE_NONE |
e5098611 MS |
407 | #define __P001 PAGE_READ |
408 | #define __P010 PAGE_READ | |
409 | #define __P011 PAGE_READ | |
410 | #define __P100 PAGE_READ | |
411 | #define __P101 PAGE_READ | |
412 | #define __P110 PAGE_READ | |
413 | #define __P111 PAGE_READ | |
9282ed92 GS |
414 | |
415 | #define __S000 PAGE_NONE | |
e5098611 MS |
416 | #define __S001 PAGE_READ |
417 | #define __S010 PAGE_WRITE | |
418 | #define __S011 PAGE_WRITE | |
419 | #define __S100 PAGE_READ | |
420 | #define __S101 PAGE_READ | |
421 | #define __S110 PAGE_WRITE | |
422 | #define __S111 PAGE_WRITE | |
1da177e4 | 423 | |
106c992a GS |
424 | /* |
425 | * Segment entry (large page) protection definitions. | |
426 | */ | |
e5098611 MS |
427 | #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ |
428 | _SEGMENT_ENTRY_PROTECT) | |
152125b7 MS |
429 | #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \ |
430 | _SEGMENT_ENTRY_READ) | |
431 | #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \ | |
432 | _SEGMENT_ENTRY_WRITE) | |
2dffdcba HC |
433 | #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ |
434 | _SEGMENT_ENTRY_LARGE | \ | |
435 | _SEGMENT_ENTRY_READ | \ | |
436 | _SEGMENT_ENTRY_WRITE | \ | |
437 | _SEGMENT_ENTRY_YOUNG | \ | |
438 | _SEGMENT_ENTRY_DIRTY) | |
439 | #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ | |
440 | _SEGMENT_ENTRY_LARGE | \ | |
441 | _SEGMENT_ENTRY_READ | \ | |
442 | _SEGMENT_ENTRY_YOUNG | \ | |
443 | _SEGMENT_ENTRY_PROTECT) | |
444 | ||
445 | /* | |
446 | * Region3 entry (large page) protection definitions. | |
447 | */ | |
448 | ||
449 | #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ | |
450 | _REGION3_ENTRY_LARGE | \ | |
451 | _REGION3_ENTRY_READ | \ | |
452 | _REGION3_ENTRY_WRITE | \ | |
453 | _REGION3_ENTRY_YOUNG | \ | |
454 | _REGION3_ENTRY_DIRTY) | |
455 | #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ | |
456 | _REGION3_ENTRY_LARGE | \ | |
457 | _REGION3_ENTRY_READ | \ | |
458 | _REGION3_ENTRY_YOUNG | \ | |
459 | _REGION_ENTRY_PROTECT) | |
106c992a | 460 | |
b2fa47e6 MS |
461 | static inline int mm_has_pgste(struct mm_struct *mm) |
462 | { | |
463 | #ifdef CONFIG_PGSTE | |
464 | if (unlikely(mm->context.has_pgste)) | |
465 | return 1; | |
466 | #endif | |
467 | return 0; | |
468 | } | |
65eef335 | 469 | |
0b46e0a3 MS |
470 | static inline int mm_alloc_pgste(struct mm_struct *mm) |
471 | { | |
472 | #ifdef CONFIG_PGSTE | |
473 | if (unlikely(mm->context.alloc_pgste)) | |
474 | return 1; | |
475 | #endif | |
476 | return 0; | |
477 | } | |
478 | ||
2faee8ff DD |
479 | /* |
480 | * In the case that a guest uses storage keys | |
481 | * faults should no longer be backed by zero pages | |
482 | */ | |
483 | #define mm_forbids_zeropage mm_use_skey | |
65eef335 DD |
484 | static inline int mm_use_skey(struct mm_struct *mm) |
485 | { | |
486 | #ifdef CONFIG_PGSTE | |
487 | if (mm->context.use_skey) | |
488 | return 1; | |
489 | #endif | |
490 | return 0; | |
491 | } | |
492 | ||
4ccccc52 HC |
493 | static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) |
494 | { | |
495 | register unsigned long reg2 asm("2") = old; | |
496 | register unsigned long reg3 asm("3") = new; | |
497 | unsigned long address = (unsigned long)ptr | 1; | |
498 | ||
499 | asm volatile( | |
500 | " csp %0,%3" | |
501 | : "+d" (reg2), "+m" (*ptr) | |
502 | : "d" (reg3), "d" (address) | |
503 | : "cc"); | |
504 | } | |
505 | ||
e8a97e42 HC |
506 | static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) |
507 | { | |
508 | register unsigned long reg2 asm("2") = old; | |
509 | register unsigned long reg3 asm("3") = new; | |
510 | unsigned long address = (unsigned long)ptr | 1; | |
511 | ||
512 | asm volatile( | |
513 | " .insn rre,0xb98a0000,%0,%3" | |
514 | : "+d" (reg2), "+m" (*ptr) | |
515 | : "d" (reg3), "d" (address) | |
516 | : "cc"); | |
517 | } | |
518 | ||
519 | #define CRDTE_DTT_PAGE 0x00UL | |
520 | #define CRDTE_DTT_SEGMENT 0x10UL | |
521 | #define CRDTE_DTT_REGION3 0x14UL | |
522 | #define CRDTE_DTT_REGION2 0x18UL | |
523 | #define CRDTE_DTT_REGION1 0x1cUL | |
524 | ||
525 | static inline void crdte(unsigned long old, unsigned long new, | |
526 | unsigned long table, unsigned long dtt, | |
527 | unsigned long address, unsigned long asce) | |
528 | { | |
529 | register unsigned long reg2 asm("2") = old; | |
530 | register unsigned long reg3 asm("3") = new; | |
531 | register unsigned long reg4 asm("4") = table | dtt; | |
532 | register unsigned long reg5 asm("5") = address; | |
533 | ||
534 | asm volatile(".insn rrf,0xb98f0000,%0,%2,%4,0" | |
535 | : "+d" (reg2) | |
536 | : "d" (reg3), "d" (reg4), "d" (reg5), "a" (asce) | |
537 | : "memory", "cc"); | |
538 | } | |
539 | ||
1da177e4 LT |
540 | /* |
541 | * pgd/pmd/pte query functions | |
542 | */ | |
5a216a20 MS |
543 | static inline int pgd_present(pgd_t pgd) |
544 | { | |
6252d702 MS |
545 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
546 | return 1; | |
5a216a20 MS |
547 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
548 | } | |
549 | ||
550 | static inline int pgd_none(pgd_t pgd) | |
551 | { | |
6252d702 MS |
552 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
553 | return 0; | |
e5098611 | 554 | return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; |
5a216a20 MS |
555 | } |
556 | ||
557 | static inline int pgd_bad(pgd_t pgd) | |
558 | { | |
6252d702 MS |
559 | /* |
560 | * With dynamic page table levels the pgd can be a region table | |
561 | * entry or a segment table entry. Check for the bit that are | |
562 | * invalid for either table entry. | |
563 | */ | |
5a216a20 | 564 | unsigned long mask = |
e5098611 | 565 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
566 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
567 | return (pgd_val(pgd) & mask) != 0; | |
568 | } | |
190a1d72 MS |
569 | |
570 | static inline int pud_present(pud_t pud) | |
1da177e4 | 571 | { |
6252d702 MS |
572 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
573 | return 1; | |
0d017923 | 574 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
575 | } |
576 | ||
190a1d72 | 577 | static inline int pud_none(pud_t pud) |
1da177e4 | 578 | { |
6252d702 MS |
579 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
580 | return 0; | |
d08de8e2 | 581 | return pud_val(pud) == _REGION3_ENTRY_EMPTY; |
1da177e4 LT |
582 | } |
583 | ||
18da2369 HC |
584 | static inline int pud_large(pud_t pud) |
585 | { | |
586 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) | |
587 | return 0; | |
588 | return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); | |
589 | } | |
590 | ||
9e20b4da HC |
591 | static inline unsigned long pud_pfn(pud_t pud) |
592 | { | |
593 | unsigned long origin_mask; | |
594 | ||
595 | origin_mask = _REGION3_ENTRY_ORIGIN; | |
596 | if (pud_large(pud)) | |
597 | origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; | |
598 | return (pud_val(pud) & origin_mask) >> PAGE_SHIFT; | |
599 | } | |
600 | ||
d08de8e2 GS |
601 | static inline int pmd_large(pmd_t pmd) |
602 | { | |
603 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; | |
604 | } | |
605 | ||
606 | static inline int pmd_bad(pmd_t pmd) | |
607 | { | |
608 | if (pmd_large(pmd)) | |
609 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; | |
610 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; | |
611 | } | |
612 | ||
190a1d72 | 613 | static inline int pud_bad(pud_t pud) |
1da177e4 | 614 | { |
d08de8e2 GS |
615 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
616 | return pmd_bad(__pmd(pud_val(pud))); | |
617 | if (pud_large(pud)) | |
618 | return (pud_val(pud) & ~_REGION_ENTRY_BITS_LARGE) != 0; | |
619 | return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; | |
1da177e4 LT |
620 | } |
621 | ||
4448aaf0 | 622 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 623 | { |
e5098611 | 624 | return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
625 | } |
626 | ||
4448aaf0 | 627 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 628 | { |
e5098611 | 629 | return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
630 | } |
631 | ||
7cded342 | 632 | static inline unsigned long pmd_pfn(pmd_t pmd) |
0944fe3f | 633 | { |
152125b7 MS |
634 | unsigned long origin_mask; |
635 | ||
636 | origin_mask = _SEGMENT_ENTRY_ORIGIN; | |
637 | if (pmd_large(pmd)) | |
638 | origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; | |
639 | return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT; | |
0944fe3f MS |
640 | } |
641 | ||
1ae1c1d0 GS |
642 | #define __HAVE_ARCH_PMD_WRITE |
643 | static inline int pmd_write(pmd_t pmd) | |
644 | { | |
152125b7 MS |
645 | return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; |
646 | } | |
647 | ||
648 | static inline int pmd_dirty(pmd_t pmd) | |
649 | { | |
650 | int dirty = 1; | |
651 | if (pmd_large(pmd)) | |
652 | dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; | |
653 | return dirty; | |
1ae1c1d0 GS |
654 | } |
655 | ||
656 | static inline int pmd_young(pmd_t pmd) | |
657 | { | |
152125b7 MS |
658 | int young = 1; |
659 | if (pmd_large(pmd)) | |
0944fe3f | 660 | young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; |
0944fe3f | 661 | return young; |
1ae1c1d0 GS |
662 | } |
663 | ||
e5098611 | 664 | static inline int pte_present(pte_t pte) |
1da177e4 | 665 | { |
e5098611 MS |
666 | /* Bit pattern: (pte & 0x001) == 0x001 */ |
667 | return (pte_val(pte) & _PAGE_PRESENT) != 0; | |
1da177e4 LT |
668 | } |
669 | ||
e5098611 | 670 | static inline int pte_none(pte_t pte) |
1da177e4 | 671 | { |
e5098611 MS |
672 | /* Bit pattern: pte == 0x400 */ |
673 | return pte_val(pte) == _PAGE_INVALID; | |
1da177e4 LT |
674 | } |
675 | ||
b31288fa KW |
676 | static inline int pte_swap(pte_t pte) |
677 | { | |
a1c843b8 MS |
678 | /* Bit pattern: (pte & 0x201) == 0x200 */ |
679 | return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) | |
680 | == _PAGE_PROTECT; | |
b31288fa KW |
681 | } |
682 | ||
7e675137 NP |
683 | static inline int pte_special(pte_t pte) |
684 | { | |
a08cb629 | 685 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
686 | } |
687 | ||
ba8a9229 | 688 | #define __HAVE_ARCH_PTE_SAME |
b2fa47e6 MS |
689 | static inline int pte_same(pte_t a, pte_t b) |
690 | { | |
691 | return pte_val(a) == pte_val(b); | |
692 | } | |
1da177e4 | 693 | |
b54565b8 MS |
694 | #ifdef CONFIG_NUMA_BALANCING |
695 | static inline int pte_protnone(pte_t pte) | |
696 | { | |
697 | return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); | |
698 | } | |
699 | ||
700 | static inline int pmd_protnone(pmd_t pmd) | |
701 | { | |
702 | /* pmd_large(pmd) implies pmd_present(pmd) */ | |
703 | return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); | |
704 | } | |
705 | #endif | |
706 | ||
5614dd92 MS |
707 | static inline int pte_soft_dirty(pte_t pte) |
708 | { | |
709 | return pte_val(pte) & _PAGE_SOFT_DIRTY; | |
710 | } | |
711 | #define pte_swp_soft_dirty pte_soft_dirty | |
712 | ||
713 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
714 | { | |
715 | pte_val(pte) |= _PAGE_SOFT_DIRTY; | |
716 | return pte; | |
717 | } | |
718 | #define pte_swp_mksoft_dirty pte_mksoft_dirty | |
719 | ||
720 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
721 | { | |
722 | pte_val(pte) &= ~_PAGE_SOFT_DIRTY; | |
723 | return pte; | |
724 | } | |
725 | #define pte_swp_clear_soft_dirty pte_clear_soft_dirty | |
726 | ||
727 | static inline int pmd_soft_dirty(pmd_t pmd) | |
728 | { | |
729 | return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; | |
730 | } | |
731 | ||
732 | static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) | |
733 | { | |
734 | pmd_val(pmd) |= _SEGMENT_ENTRY_SOFT_DIRTY; | |
735 | return pmd; | |
736 | } | |
737 | ||
738 | static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) | |
739 | { | |
740 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_SOFT_DIRTY; | |
741 | return pmd; | |
742 | } | |
743 | ||
1da177e4 LT |
744 | /* |
745 | * query functions pte_write/pte_dirty/pte_young only work if | |
746 | * pte_present() is true. Undefined behaviour if not.. | |
747 | */ | |
4448aaf0 | 748 | static inline int pte_write(pte_t pte) |
1da177e4 | 749 | { |
e5098611 | 750 | return (pte_val(pte) & _PAGE_WRITE) != 0; |
1da177e4 LT |
751 | } |
752 | ||
4448aaf0 | 753 | static inline int pte_dirty(pte_t pte) |
1da177e4 | 754 | { |
e5098611 | 755 | return (pte_val(pte) & _PAGE_DIRTY) != 0; |
1da177e4 LT |
756 | } |
757 | ||
4448aaf0 | 758 | static inline int pte_young(pte_t pte) |
1da177e4 | 759 | { |
0944fe3f | 760 | return (pte_val(pte) & _PAGE_YOUNG) != 0; |
1da177e4 LT |
761 | } |
762 | ||
b31288fa KW |
763 | #define __HAVE_ARCH_PTE_UNUSED |
764 | static inline int pte_unused(pte_t pte) | |
765 | { | |
766 | return pte_val(pte) & _PAGE_UNUSED; | |
767 | } | |
768 | ||
1da177e4 LT |
769 | /* |
770 | * pgd/pmd/pte modification functions | |
771 | */ | |
772 | ||
b2fa47e6 | 773 | static inline void pgd_clear(pgd_t *pgd) |
5a216a20 | 774 | { |
6252d702 MS |
775 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
776 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
777 | } |
778 | ||
b2fa47e6 | 779 | static inline void pud_clear(pud_t *pud) |
1da177e4 | 780 | { |
6252d702 MS |
781 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
782 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
783 | } |
784 | ||
b2fa47e6 | 785 | static inline void pmd_clear(pmd_t *pmdp) |
1da177e4 | 786 | { |
e5098611 | 787 | pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
788 | } |
789 | ||
4448aaf0 | 790 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 791 | { |
e5098611 | 792 | pte_val(*ptep) = _PAGE_INVALID; |
1da177e4 LT |
793 | } |
794 | ||
795 | /* | |
796 | * The following pte modification functions only work if | |
797 | * pte_present() is true. Undefined behaviour if not.. | |
798 | */ | |
4448aaf0 | 799 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 800 | { |
138c9021 | 801 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 | 802 | pte_val(pte) |= pgprot_val(newprot); |
0944fe3f MS |
803 | /* |
804 | * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the | |
805 | * invalid bit set, clear it again for readable, young pages | |
806 | */ | |
807 | if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) | |
808 | pte_val(pte) &= ~_PAGE_INVALID; | |
809 | /* | |
810 | * newprot for PAGE_READ and PAGE_WRITE has the page protection | |
811 | * bit set, clear it again for writable, dirty pages | |
812 | */ | |
e5098611 MS |
813 | if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) |
814 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
815 | return pte; |
816 | } | |
817 | ||
4448aaf0 | 818 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 819 | { |
e5098611 MS |
820 | pte_val(pte) &= ~_PAGE_WRITE; |
821 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
822 | return pte; |
823 | } | |
824 | ||
4448aaf0 | 825 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 | 826 | { |
e5098611 MS |
827 | pte_val(pte) |= _PAGE_WRITE; |
828 | if (pte_val(pte) & _PAGE_DIRTY) | |
829 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
830 | return pte; |
831 | } | |
832 | ||
4448aaf0 | 833 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 | 834 | { |
e5098611 MS |
835 | pte_val(pte) &= ~_PAGE_DIRTY; |
836 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
837 | return pte; |
838 | } | |
839 | ||
4448aaf0 | 840 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 | 841 | { |
5614dd92 | 842 | pte_val(pte) |= _PAGE_DIRTY | _PAGE_SOFT_DIRTY; |
e5098611 MS |
843 | if (pte_val(pte) & _PAGE_WRITE) |
844 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
845 | return pte; |
846 | } | |
847 | ||
4448aaf0 | 848 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 | 849 | { |
e5098611 | 850 | pte_val(pte) &= ~_PAGE_YOUNG; |
0944fe3f | 851 | pte_val(pte) |= _PAGE_INVALID; |
1da177e4 LT |
852 | return pte; |
853 | } | |
854 | ||
4448aaf0 | 855 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 | 856 | { |
0944fe3f MS |
857 | pte_val(pte) |= _PAGE_YOUNG; |
858 | if (pte_val(pte) & _PAGE_READ) | |
859 | pte_val(pte) &= ~_PAGE_INVALID; | |
1da177e4 LT |
860 | return pte; |
861 | } | |
862 | ||
7e675137 NP |
863 | static inline pte_t pte_mkspecial(pte_t pte) |
864 | { | |
a08cb629 | 865 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
866 | return pte; |
867 | } | |
868 | ||
84afdcee HC |
869 | #ifdef CONFIG_HUGETLB_PAGE |
870 | static inline pte_t pte_mkhuge(pte_t pte) | |
871 | { | |
e5098611 | 872 | pte_val(pte) |= _PAGE_LARGE; |
84afdcee HC |
873 | return pte; |
874 | } | |
875 | #endif | |
876 | ||
9282ed92 | 877 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 878 | { |
53e857f3 MS |
879 | unsigned long pto = (unsigned long) ptep; |
880 | ||
53e857f3 MS |
881 | /* Invalidation + global TLB flush for the pte */ |
882 | asm volatile( | |
883 | " ipte %2,%3" | |
884 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
885 | } | |
886 | ||
1b948d6c MS |
887 | static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep) |
888 | { | |
889 | unsigned long pto = (unsigned long) ptep; | |
890 | ||
1b948d6c MS |
891 | /* Invalidation + local TLB flush for the pte */ |
892 | asm volatile( | |
893 | " .insn rrf,0xb2210000,%2,%3,0,1" | |
894 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
895 | } | |
896 | ||
cfb0b241 HC |
897 | static inline void __ptep_ipte_range(unsigned long address, int nr, pte_t *ptep) |
898 | { | |
899 | unsigned long pto = (unsigned long) ptep; | |
900 | ||
cfb0b241 HC |
901 | /* Invalidate a range of ptes + global TLB flush of the ptes */ |
902 | do { | |
903 | asm volatile( | |
904 | " .insn rrf,0xb2210000,%2,%0,%1,0" | |
905 | : "+a" (address), "+a" (nr) : "a" (pto) : "memory"); | |
906 | } while (nr != 255); | |
907 | } | |
908 | ||
0a61b222 | 909 | /* |
ebde765c MS |
910 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush |
911 | * both clear the TLB for the unmapped pte. The reason is that | |
912 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
913 | * to modify an active pte. The sequence is | |
914 | * 1) ptep_get_and_clear | |
915 | * 2) set_pte_at | |
916 | * 3) flush_tlb_range | |
917 | * On s390 the tlb needs to get flushed with the modification of the pte | |
918 | * if the pte is active. The only way how this can be implemented is to | |
919 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
920 | * is a nop. | |
0a61b222 | 921 | */ |
ebde765c MS |
922 | pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); |
923 | pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); | |
0a61b222 | 924 | |
0944fe3f MS |
925 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
926 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
927 | unsigned long addr, pte_t *ptep) | |
928 | { | |
ebde765c | 929 | pte_t pte = *ptep; |
0944fe3f | 930 | |
ebde765c MS |
931 | pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); |
932 | return pte_young(pte); | |
0944fe3f MS |
933 | } |
934 | ||
935 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
936 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
937 | unsigned long address, pte_t *ptep) | |
938 | { | |
939 | return ptep_test_and_clear_young(vma, address, ptep); | |
940 | } | |
941 | ||
ba8a9229 | 942 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
b2fa47e6 | 943 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
ebde765c | 944 | unsigned long addr, pte_t *ptep) |
b2fa47e6 | 945 | { |
ebde765c | 946 | return ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); |
b2fa47e6 MS |
947 | } |
948 | ||
949 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
ebde765c MS |
950 | pte_t ptep_modify_prot_start(struct mm_struct *, unsigned long, pte_t *); |
951 | void ptep_modify_prot_commit(struct mm_struct *, unsigned long, pte_t *, pte_t); | |
ba8a9229 MS |
952 | |
953 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 | 954 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
ebde765c | 955 | unsigned long addr, pte_t *ptep) |
f0e47c22 | 956 | { |
ebde765c | 957 | return ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); |
1da177e4 LT |
958 | } |
959 | ||
ba8a9229 MS |
960 | /* |
961 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
962 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
963 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
964 | * cannot be accessed while the batched unmap is running. In this case | |
965 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
966 | */ | |
967 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
968 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
ebde765c | 969 | unsigned long addr, |
ba8a9229 | 970 | pte_t *ptep, int full) |
1da177e4 | 971 | { |
ebde765c MS |
972 | if (full) { |
973 | pte_t pte = *ptep; | |
974 | *ptep = __pte(_PAGE_INVALID); | |
975 | return pte; | |
b2fa47e6 | 976 | } |
ebde765c | 977 | return ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); |
1da177e4 LT |
978 | } |
979 | ||
ba8a9229 | 980 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
ebde765c MS |
981 | static inline void ptep_set_wrprotect(struct mm_struct *mm, |
982 | unsigned long addr, pte_t *ptep) | |
b2fa47e6 | 983 | { |
b2fa47e6 MS |
984 | pte_t pte = *ptep; |
985 | ||
ebde765c MS |
986 | if (pte_write(pte)) |
987 | ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); | |
b2fa47e6 | 988 | } |
ba8a9229 MS |
989 | |
990 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
b2fa47e6 | 991 | static inline int ptep_set_access_flags(struct vm_area_struct *vma, |
ebde765c | 992 | unsigned long addr, pte_t *ptep, |
b2fa47e6 MS |
993 | pte_t entry, int dirty) |
994 | { | |
ebde765c | 995 | if (pte_same(*ptep, entry)) |
b2fa47e6 | 996 | return 0; |
ebde765c MS |
997 | ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); |
998 | return 1; | |
999 | } | |
b2fa47e6 | 1000 | |
1e133ab2 MS |
1001 | /* |
1002 | * Additional functions to handle KVM guest page tables | |
1003 | */ | |
1004 | void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1005 | pte_t *ptep, pte_t entry); | |
1006 | void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); | |
4be130a0 MS |
1007 | void ptep_notify(struct mm_struct *mm, unsigned long addr, |
1008 | pte_t *ptep, unsigned long bits); | |
b2d73b2a | 1009 | int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, |
4be130a0 | 1010 | pte_t *ptep, int prot, unsigned long bit); |
1e133ab2 MS |
1011 | void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, |
1012 | pte_t *ptep , int reset); | |
1013 | void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); | |
4be130a0 | 1014 | int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, |
a9d23e71 | 1015 | pte_t *sptep, pte_t *tptep, pte_t pte); |
4be130a0 | 1016 | void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); |
1e133ab2 MS |
1017 | |
1018 | bool test_and_clear_guest_dirty(struct mm_struct *mm, unsigned long address); | |
1019 | int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, | |
1020 | unsigned char key, bool nq); | |
1824c723 DH |
1021 | int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, |
1022 | unsigned char key, unsigned char *oldkey, | |
1023 | bool nq, bool mr, bool mc); | |
a7e19ab5 | 1024 | int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); |
154c8c19 DH |
1025 | int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, |
1026 | unsigned char *key); | |
b2fa47e6 | 1027 | |
ebde765c MS |
1028 | /* |
1029 | * Certain architectures need to do special things when PTEs | |
1030 | * within a page table are directly modified. Thus, the following | |
1031 | * hook is made available. | |
1032 | */ | |
1033 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1034 | pte_t *ptep, pte_t entry) | |
1035 | { | |
1036 | if (mm_has_pgste(mm)) | |
1e133ab2 | 1037 | ptep_set_pte_at(mm, addr, ptep, entry); |
ebde765c | 1038 | else |
abf09bed | 1039 | *ptep = entry; |
b2fa47e6 | 1040 | } |
1da177e4 | 1041 | |
1da177e4 LT |
1042 | /* |
1043 | * Conversion functions: convert a page and protection to a page entry, | |
1044 | * and a page entry and page directory to the page they refer to. | |
1045 | */ | |
1046 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1047 | { | |
1048 | pte_t __pte; | |
1049 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
0944fe3f | 1050 | return pte_mkyoung(__pte); |
1da177e4 LT |
1051 | } |
1052 | ||
2dcea57a HC |
1053 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1054 | { | |
0b2b6e1d | 1055 | unsigned long physpage = page_to_phys(page); |
abf09bed | 1056 | pte_t __pte = mk_pte_phys(physpage, pgprot); |
1da177e4 | 1057 | |
e5098611 MS |
1058 | if (pte_write(__pte) && PageDirty(page)) |
1059 | __pte = pte_mkdirty(__pte); | |
abf09bed | 1060 | return __pte; |
2dcea57a HC |
1061 | } |
1062 | ||
190a1d72 MS |
1063 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1064 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
1065 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1066 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1067 | |
190a1d72 MS |
1068 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1069 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1070 | |
190a1d72 MS |
1071 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1072 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 1073 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1074 | |
5a216a20 MS |
1075 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
1076 | { | |
6252d702 MS |
1077 | pud_t *pud = (pud_t *) pgd; |
1078 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1079 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
1080 | return pud + pud_index(address); |
1081 | } | |
1da177e4 | 1082 | |
190a1d72 | 1083 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1084 | { |
6252d702 MS |
1085 | pmd_t *pmd = (pmd_t *) pud; |
1086 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
1087 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1088 | return pmd + pmd_index(address); |
1da177e4 LT |
1089 | } |
1090 | ||
190a1d72 MS |
1091 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1092 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1093 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1094 | |
152125b7 | 1095 | #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) |
d08de8e2 | 1096 | #define pud_page(pud) pfn_to_page(pud_pfn(pud)) |
1da177e4 | 1097 | |
190a1d72 MS |
1098 | /* Find an entry in the lowest level page table.. */ |
1099 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1100 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 | 1101 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1da177e4 | 1102 | #define pte_unmap(pte) do { } while (0) |
1da177e4 | 1103 | |
152125b7 | 1104 | static inline pmd_t pmd_wrprotect(pmd_t pmd) |
0944fe3f | 1105 | { |
152125b7 MS |
1106 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; |
1107 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1108 | return pmd; | |
1109 | } | |
1110 | ||
1111 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
1112 | { | |
1113 | pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; | |
1114 | if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1115 | return pmd; | |
1116 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1117 | return pmd; | |
1118 | } | |
1119 | ||
1120 | static inline pmd_t pmd_mkclean(pmd_t pmd) | |
1121 | { | |
1122 | if (pmd_large(pmd)) { | |
1123 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; | |
0944fe3f | 1124 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; |
152125b7 MS |
1125 | } |
1126 | return pmd; | |
1127 | } | |
1128 | ||
1129 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
1130 | { | |
1131 | if (pmd_large(pmd)) { | |
5614dd92 MS |
1132 | pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY | |
1133 | _SEGMENT_ENTRY_SOFT_DIRTY; | |
152125b7 MS |
1134 | if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) |
1135 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1136 | } | |
1137 | return pmd; | |
1138 | } | |
1139 | ||
9e20b4da HC |
1140 | static inline pud_t pud_wrprotect(pud_t pud) |
1141 | { | |
1142 | pud_val(pud) &= ~_REGION3_ENTRY_WRITE; | |
1143 | pud_val(pud) |= _REGION_ENTRY_PROTECT; | |
1144 | return pud; | |
1145 | } | |
1146 | ||
1147 | static inline pud_t pud_mkwrite(pud_t pud) | |
1148 | { | |
1149 | pud_val(pud) |= _REGION3_ENTRY_WRITE; | |
1150 | if (pud_large(pud) && !(pud_val(pud) & _REGION3_ENTRY_DIRTY)) | |
1151 | return pud; | |
1152 | pud_val(pud) &= ~_REGION_ENTRY_PROTECT; | |
1153 | return pud; | |
1154 | } | |
1155 | ||
1156 | static inline pud_t pud_mkclean(pud_t pud) | |
1157 | { | |
1158 | if (pud_large(pud)) { | |
1159 | pud_val(pud) &= ~_REGION3_ENTRY_DIRTY; | |
1160 | pud_val(pud) |= _REGION_ENTRY_PROTECT; | |
1161 | } | |
1162 | return pud; | |
1163 | } | |
1164 | ||
1165 | static inline pud_t pud_mkdirty(pud_t pud) | |
1166 | { | |
1167 | if (pud_large(pud)) { | |
1168 | pud_val(pud) |= _REGION3_ENTRY_DIRTY | | |
1169 | _REGION3_ENTRY_SOFT_DIRTY; | |
1170 | if (pud_val(pud) & _REGION3_ENTRY_WRITE) | |
1171 | pud_val(pud) &= ~_REGION_ENTRY_PROTECT; | |
1172 | } | |
1173 | return pud; | |
1174 | } | |
1175 | ||
1176 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) | |
1177 | static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) | |
1178 | { | |
1179 | /* | |
1180 | * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx) | |
1181 | * Convert to segment table entry format. | |
1182 | */ | |
1183 | if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) | |
1184 | return pgprot_val(SEGMENT_NONE); | |
1185 | if (pgprot_val(pgprot) == pgprot_val(PAGE_READ)) | |
1186 | return pgprot_val(SEGMENT_READ); | |
1187 | return pgprot_val(SEGMENT_WRITE); | |
1188 | } | |
1189 | ||
152125b7 MS |
1190 | static inline pmd_t pmd_mkyoung(pmd_t pmd) |
1191 | { | |
1192 | if (pmd_large(pmd)) { | |
0944fe3f | 1193 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
152125b7 MS |
1194 | if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) |
1195 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; | |
0944fe3f | 1196 | } |
0944fe3f MS |
1197 | return pmd; |
1198 | } | |
1199 | ||
1200 | static inline pmd_t pmd_mkold(pmd_t pmd) | |
1201 | { | |
152125b7 | 1202 | if (pmd_large(pmd)) { |
0944fe3f MS |
1203 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; |
1204 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1205 | } | |
0944fe3f MS |
1206 | return pmd; |
1207 | } | |
1208 | ||
1ae1c1d0 GS |
1209 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
1210 | { | |
152125b7 MS |
1211 | if (pmd_large(pmd)) { |
1212 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | | |
1213 | _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | | |
fecffad2 | 1214 | _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SOFT_DIRTY; |
152125b7 MS |
1215 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1216 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1217 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1218 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) | |
1219 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1220 | return pmd; | |
1221 | } | |
1222 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN; | |
1ae1c1d0 GS |
1223 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1224 | return pmd; | |
1225 | } | |
1226 | ||
106c992a | 1227 | static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) |
1ae1c1d0 | 1228 | { |
106c992a GS |
1229 | pmd_t __pmd; |
1230 | pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); | |
152125b7 | 1231 | return __pmd; |
1ae1c1d0 GS |
1232 | } |
1233 | ||
106c992a GS |
1234 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ |
1235 | ||
1b948d6c MS |
1236 | static inline void __pmdp_csp(pmd_t *pmdp) |
1237 | { | |
4ccccc52 HC |
1238 | csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), |
1239 | pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); | |
1b948d6c MS |
1240 | } |
1241 | ||
1242 | static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp) | |
1243 | { | |
1244 | unsigned long sto; | |
1245 | ||
1246 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1247 | asm volatile( | |
1248 | " .insn rrf,0xb98e0000,%2,%3,0,0" | |
1249 | : "=m" (*pmdp) | |
1250 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1251 | : "cc" ); | |
1252 | } | |
1253 | ||
d08de8e2 GS |
1254 | static inline void __pudp_idte(unsigned long address, pud_t *pudp) |
1255 | { | |
1256 | unsigned long r3o; | |
1257 | ||
1258 | r3o = (unsigned long) pudp - pud_index(address) * sizeof(pud_t); | |
1259 | r3o |= _ASCE_TYPE_REGION3; | |
1260 | asm volatile( | |
1261 | " .insn rrf,0xb98e0000,%2,%3,0,0" | |
1262 | : "=m" (*pudp) | |
1263 | : "m" (*pudp), "a" (r3o), "a" ((address & PUD_MASK)) | |
1264 | : "cc"); | |
1265 | } | |
1266 | ||
1b948d6c MS |
1267 | static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp) |
1268 | { | |
1269 | unsigned long sto; | |
1270 | ||
1271 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1272 | asm volatile( | |
1273 | " .insn rrf,0xb98e0000,%2,%3,0,1" | |
1274 | : "=m" (*pmdp) | |
1275 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1276 | : "cc" ); | |
1277 | } | |
1278 | ||
d08de8e2 GS |
1279 | static inline void __pudp_idte_local(unsigned long address, pud_t *pudp) |
1280 | { | |
1281 | unsigned long r3o; | |
1282 | ||
1283 | r3o = (unsigned long) pudp - pud_index(address) * sizeof(pud_t); | |
1284 | r3o |= _ASCE_TYPE_REGION3; | |
1285 | asm volatile( | |
1286 | " .insn rrf,0xb98e0000,%2,%3,0,1" | |
1287 | : "=m" (*pudp) | |
1288 | : "m" (*pudp), "a" (r3o), "a" ((address & PUD_MASK)) | |
1289 | : "cc"); | |
1290 | } | |
1291 | ||
227be799 MS |
1292 | pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); |
1293 | pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); | |
d08de8e2 | 1294 | pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); |
1b948d6c | 1295 | |
227be799 MS |
1296 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1297 | ||
1298 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
1299 | void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, | |
1300 | pgtable_t pgtable); | |
1301 | ||
1302 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
1303 | pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); | |
1b948d6c | 1304 | |
227be799 MS |
1305 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1306 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1307 | unsigned long addr, pmd_t *pmdp, | |
1308 | pmd_t entry, int dirty) | |
3eabaee9 | 1309 | { |
227be799 | 1310 | VM_BUG_ON(addr & ~HPAGE_MASK); |
3eabaee9 | 1311 | |
227be799 MS |
1312 | entry = pmd_mkyoung(entry); |
1313 | if (dirty) | |
1314 | entry = pmd_mkdirty(entry); | |
1315 | if (pmd_val(*pmdp) == pmd_val(entry)) | |
1316 | return 0; | |
1317 | pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); | |
1318 | return 1; | |
3eabaee9 MS |
1319 | } |
1320 | ||
227be799 MS |
1321 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1322 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1323 | unsigned long addr, pmd_t *pmdp) | |
1324 | { | |
1325 | pmd_t pmd = *pmdp; | |
106c992a | 1326 | |
227be799 MS |
1327 | pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); |
1328 | return pmd_young(pmd); | |
1329 | } | |
106c992a | 1330 | |
227be799 MS |
1331 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH |
1332 | static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
1333 | unsigned long addr, pmd_t *pmdp) | |
1334 | { | |
1335 | VM_BUG_ON(addr & ~HPAGE_MASK); | |
1336 | return pmdp_test_and_clear_young(vma, addr, pmdp); | |
1337 | } | |
106c992a | 1338 | |
106c992a GS |
1339 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
1340 | pmd_t *pmdp, pmd_t entry) | |
1341 | { | |
106c992a GS |
1342 | *pmdp = entry; |
1343 | } | |
1344 | ||
1345 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1346 | { | |
1347 | pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; | |
152125b7 MS |
1348 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
1349 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1ae1c1d0 GS |
1350 | return pmd; |
1351 | } | |
1352 | ||
8809aa2d AK |
1353 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
1354 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
227be799 | 1355 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1356 | { |
227be799 | 1357 | return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_INVALID)); |
1ae1c1d0 GS |
1358 | } |
1359 | ||
8809aa2d AK |
1360 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1361 | static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm, | |
227be799 | 1362 | unsigned long addr, |
8809aa2d | 1363 | pmd_t *pmdp, int full) |
fcbe08d6 | 1364 | { |
227be799 MS |
1365 | if (full) { |
1366 | pmd_t pmd = *pmdp; | |
1367 | *pmdp = __pmd(_SEGMENT_ENTRY_INVALID); | |
1368 | return pmd; | |
1369 | } | |
1370 | return pmdp_xchg_lazy(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_INVALID)); | |
fcbe08d6 MS |
1371 | } |
1372 | ||
8809aa2d AK |
1373 | #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH |
1374 | static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, | |
227be799 | 1375 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1376 | { |
227be799 | 1377 | return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); |
1ae1c1d0 GS |
1378 | } |
1379 | ||
1380 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1381 | static inline void pmdp_invalidate(struct vm_area_struct *vma, | |
227be799 | 1382 | unsigned long addr, pmd_t *pmdp) |
1ae1c1d0 | 1383 | { |
227be799 | 1384 | pmdp_xchg_direct(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_INVALID)); |
1ae1c1d0 GS |
1385 | } |
1386 | ||
be328650 GS |
1387 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1388 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
227be799 | 1389 | unsigned long addr, pmd_t *pmdp) |
be328650 GS |
1390 | { |
1391 | pmd_t pmd = *pmdp; | |
1392 | ||
227be799 MS |
1393 | if (pmd_write(pmd)) |
1394 | pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); | |
be328650 GS |
1395 | } |
1396 | ||
f28b6ff8 AK |
1397 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1398 | unsigned long address, | |
1399 | pmd_t *pmdp) | |
1400 | { | |
8809aa2d | 1401 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
f28b6ff8 AK |
1402 | } |
1403 | #define pmdp_collapse_flush pmdp_collapse_flush | |
1404 | ||
1ae1c1d0 GS |
1405 | #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) |
1406 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) | |
1407 | ||
1408 | static inline int pmd_trans_huge(pmd_t pmd) | |
1409 | { | |
1410 | return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; | |
1411 | } | |
1412 | ||
fd8cfd30 | 1413 | #define has_transparent_hugepage has_transparent_hugepage |
1ae1c1d0 GS |
1414 | static inline int has_transparent_hugepage(void) |
1415 | { | |
1416 | return MACHINE_HAS_HPAGE ? 1 : 0; | |
1417 | } | |
75077afb GS |
1418 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1419 | ||
1da177e4 | 1420 | /* |
1da177e4 LT |
1421 | * 64 bit swap entry format: |
1422 | * A page-table entry has some bits we have to treat in a special way. | |
4e0a6412 | 1423 | * Bits 52 and bit 55 have to be zero, otherwise a specification |
1da177e4 | 1424 | * exception will occur instead of a page translation exception. The |
4e0a6412 | 1425 | * specification exception has the bad habit not to store necessary |
1da177e4 | 1426 | * information in the lowcore. |
a1c843b8 MS |
1427 | * Bits 54 and 63 are used to indicate the page type. |
1428 | * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 | |
1429 | * This leaves the bits 0-51 and bits 56-62 to store type and offset. | |
1430 | * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 | |
1431 | * for the offset. | |
1432 | * | offset |01100|type |00| | |
1433 | * |0000000000111111111122222222223333333333444444444455|55555|55566|66| | |
1434 | * |0123456789012345678901234567890123456789012345678901|23456|78901|23| | |
1da177e4 | 1435 | */ |
5a79859a | 1436 | |
a1c843b8 MS |
1437 | #define __SWP_OFFSET_MASK ((1UL << 52) - 1) |
1438 | #define __SWP_OFFSET_SHIFT 12 | |
1439 | #define __SWP_TYPE_MASK ((1UL << 5) - 1) | |
1440 | #define __SWP_TYPE_SHIFT 2 | |
5a79859a | 1441 | |
4448aaf0 | 1442 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1443 | { |
1444 | pte_t pte; | |
a1c843b8 MS |
1445 | |
1446 | pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; | |
1447 | pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; | |
1448 | pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; | |
1da177e4 LT |
1449 | return pte; |
1450 | } | |
1451 | ||
a1c843b8 MS |
1452 | static inline unsigned long __swp_type(swp_entry_t entry) |
1453 | { | |
1454 | return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; | |
1455 | } | |
1456 | ||
1457 | static inline unsigned long __swp_offset(swp_entry_t entry) | |
1458 | { | |
1459 | return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; | |
1460 | } | |
1461 | ||
1462 | static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) | |
1463 | { | |
1464 | return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; | |
1465 | } | |
1da177e4 LT |
1466 | |
1467 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1468 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1469 | ||
1da177e4 LT |
1470 | #endif /* !__ASSEMBLY__ */ |
1471 | ||
1472 | #define kern_addr_valid(addr) (1) | |
1473 | ||
17f34580 HC |
1474 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1475 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1476 | extern int s390_enable_sie(void); |
3ac8e380 | 1477 | extern int s390_enable_skey(void); |
a13cff31 | 1478 | extern void s390_reset_cmma(struct mm_struct *mm); |
f4eb07c1 | 1479 | |
1f6b83e5 MS |
1480 | /* s390 has a private copy of get unmapped area to deal with cache synonyms */ |
1481 | #define HAVE_ARCH_UNMAPPED_AREA | |
1482 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
1483 | ||
1da177e4 LT |
1484 | /* |
1485 | * No page table caches to initialise | |
1486 | */ | |
765a0cac HC |
1487 | static inline void pgtable_cache_init(void) { } |
1488 | static inline void check_pgt_cache(void) { } | |
1da177e4 | 1489 | |
1da177e4 LT |
1490 | #include <asm-generic/pgtable.h> |
1491 | ||
1492 | #endif /* _S390_PAGE_H */ |