projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
[deliverable/linux.git] / arch / s390 / include / asm / pgtable.h
CommitLineData
1da177e4 1/*
1da177e4 2 * S390 version
a53c8fab 3 * Copyright IBM Corp. 1999, 2000
1da177e4
LT		 4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11#ifndef _ASM_S390_PGTABLE_H
12#define _ASM_S390_PGTABLE_H
13
1da177e4
LT		 14/*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29#ifndef __ASSEMBLY__
9789db08 30#include <linux/sched.h>
2dcea57a 31#include <linux/mm_types.h>
abf09bed 32#include <linux/page-flags.h>
1da177e4 33#include <asm/bug.h>
b2fa47e6 34#include <asm/page.h>
1da177e4 35
1da177e4
LT		 36extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
37extern void paging_init(void);
2b67fc46 38extern void vmem_map_init(void);
1da177e4
LT		 39
40/*
41 * The S390 doesn't have any external MMU info: the kernel page
42 * tables contain all the necessary information.
43 */
4b3073e1 44#define update_mmu_cache(vma, address, ptep) do { } while (0)
b113da65 45#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
1da177e4
LT		 46
47/*
238ec4ef 48 * ZERO_PAGE is a global shared page that is always zero; used
1da177e4
LT		 49 * for zero-mapped memory areas etc..
50 */
238ec4ef
MS		 51
52extern unsigned long empty_zero_page;
53extern unsigned long zero_page_mask;
54
55#define ZERO_PAGE(vaddr) \
56 (virt_to_page((void *)(empty_zero_page + \
57 (((unsigned long)(vaddr)) &zero_page_mask))))
816422ad 58#define __HAVE_COLOR_ZERO_PAGE
238ec4ef 59
4f2e2903 60/* TODO: s390 cannot support io_remap_pfn_range... */
1da177e4
LT		 61#endif /* !__ASSEMBLY__ */
62
63/*
64 * PMD_SHIFT determines the size of the area a second-level page
65 * table can map
66 * PGDIR_SHIFT determines what a third-level page table entry can map
67 */
f4815ac6 68#ifndef CONFIG_64BIT
146e4b3c
MS		 69# define PMD_SHIFT 20
70# define PUD_SHIFT 20
71# define PGDIR_SHIFT 20
f4815ac6 72#else /* CONFIG_64BIT */
146e4b3c 73# define PMD_SHIFT 20
190a1d72 74# define PUD_SHIFT 31
5a216a20 75# define PGDIR_SHIFT 42
f4815ac6 76#endif /* CONFIG_64BIT */
1da177e4
LT		 77
78#define PMD_SIZE (1UL << PMD_SHIFT)
79#define PMD_MASK (~(PMD_SIZE-1))
190a1d72
MS		 80#define PUD_SIZE (1UL << PUD_SHIFT)
81#define PUD_MASK (~(PUD_SIZE-1))
5a216a20
MS		 82#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
83#define PGDIR_MASK (~(PGDIR_SIZE-1))
1da177e4
LT		 84
85/*
86 * entries per page directory level: the S390 is two-level, so
87 * we don't really have any PMD directory physically.
88 * for S390 segment-table entries are combined to one PGD
89 * that leads to 1024 pte per pgd
90 */
146e4b3c 91#define PTRS_PER_PTE 256
f4815ac6 92#ifndef CONFIG_64BIT
146e4b3c 93#define PTRS_PER_PMD 1
5a216a20 94#define PTRS_PER_PUD 1
f4815ac6 95#else /* CONFIG_64BIT */
146e4b3c 96#define PTRS_PER_PMD 2048
5a216a20 97#define PTRS_PER_PUD 2048
f4815ac6 98#endif /* CONFIG_64BIT */
146e4b3c 99#define PTRS_PER_PGD 2048
1da177e4 100
d455a369
HD		 101#define FIRST_USER_ADDRESS 0
102
1da177e4
LT		 103#define pte_ERROR(e) \
104 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
105#define pmd_ERROR(e) \
106 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
190a1d72
MS		 107#define pud_ERROR(e) \
108 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
1da177e4
LT		 109#define pgd_ERROR(e) \
110 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
111
112#ifndef __ASSEMBLY__
113/*
c972cc60
HC		 114 * The vmalloc and module area will always be on the topmost area of the kernel
115 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
116 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
117 * modules will reside. That makes sure that inter module branches always
118 * happen without trampolines and in addition the placement within a 2GB frame
119 * is branch prediction unit friendly.
8b62bc96 120 */
239a6425 121extern unsigned long VMALLOC_START;
14045ebf
MS		 122extern unsigned long VMALLOC_END;
123extern struct page *vmemmap;
239a6425 124
14045ebf 125#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
5fd9c6e2 126
c972cc60
HC		 127#ifdef CONFIG_64BIT
128extern unsigned long MODULES_VADDR;
129extern unsigned long MODULES_END;
130#define MODULES_VADDR MODULES_VADDR
131#define MODULES_END MODULES_END
132#define MODULES_LEN (1UL << 31)
133#endif
134
1da177e4
LT		 135/*
136 * A 31 bit pagetable entry of S390 has following format:
137 * | PFRA | | OS |
138 * 0 0IP0
139 * 00000000001111111111222222222233
140 * 01234567890123456789012345678901
141 *
142 * I Page-Invalid Bit: Page is not available for address-translation
143 * P Page-Protection Bit: Store access not possible for page
144 *
145 * A 31 bit segmenttable entry of S390 has following format:
146 * | P-table origin | |PTL
147 * 0 IC
148 * 00000000001111111111222222222233
149 * 01234567890123456789012345678901
150 *
151 * I Segment-Invalid Bit: Segment is not available for address-translation
152 * C Common-Segment Bit: Segment is not private (PoP 3-30)
153 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
154 *
155 * The 31 bit segmenttable origin of S390 has following format:
156 *
157 * |S-table origin | | STL |
158 * X **GPS
159 * 00000000001111111111222222222233
160 * 01234567890123456789012345678901
161 *
162 * X Space-Switch event:
163 * G Segment-Invalid Bit: *
164 * P Private-Space Bit: Segment is not private (PoP 3-30)
165 * S Storage-Alteration:
166 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
167 *
168 * A 64 bit pagetable entry of S390 has following format:
6a985c61 169 * | PFRA |0IPC| OS |
1da177e4
LT		 170 * 0000000000111111111122222222223333333333444444444455555555556666
171 * 0123456789012345678901234567890123456789012345678901234567890123
172 *
173 * I Page-Invalid Bit: Page is not available for address-translation
174 * P Page-Protection Bit: Store access not possible for page
6a985c61 175 * C Change-bit override: HW is not required to set change bit
1da177e4
LT		 176 *
177 * A 64 bit segmenttable entry of S390 has following format:
178 * | P-table origin | TT
179 * 0000000000111111111122222222223333333333444444444455555555556666
180 * 0123456789012345678901234567890123456789012345678901234567890123
181 *
182 * I Segment-Invalid Bit: Segment is not available for address-translation
183 * C Common-Segment Bit: Segment is not private (PoP 3-30)
184 * P Page-Protection Bit: Store access not possible for page
185 * TT Type 00
186 *
187 * A 64 bit region table entry of S390 has following format:
188 * | S-table origin | TF TTTL
189 * 0000000000111111111122222222223333333333444444444455555555556666
190 * 0123456789012345678901234567890123456789012345678901234567890123
191 *
192 * I Segment-Invalid Bit: Segment is not available for address-translation
193 * TT Type 01
194 * TF
190a1d72 195 * TL Table length
1da177e4
LT		 196 *
197 * The 64 bit regiontable origin of S390 has following format:
198 * | region table origon | DTTL
199 * 0000000000111111111122222222223333333333444444444455555555556666
200 * 0123456789012345678901234567890123456789012345678901234567890123
201 *
202 * X Space-Switch event:
203 * G Segment-Invalid Bit:
204 * P Private-Space Bit:
205 * S Storage-Alteration:
206 * R Real space
207 * TL Table-Length:
208 *
209 * A storage key has the following format:
210 * | ACC |F|R|C|0|
211 * 0 3 4 5 6 7
212 * ACC: access key
213 * F : fetch protection bit
214 * R : referenced bit
215 * C : changed bit
216 */
217
218/* Hardware bits in the page table entry */
6a985c61 219#define _PAGE_CO 0x100 /* HW Change-bit override */
e5098611 220#define _PAGE_PROTECT 0x200 /* HW read-only bit */
83377484 221#define _PAGE_INVALID 0x400 /* HW invalid bit */
e5098611 222#define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
3610cce8
MS		 223
224/* Software bits in the page table entry */
e5098611
MS		 225#define _PAGE_PRESENT 0x001 /* SW pte present bit */
226#define _PAGE_TYPE 0x002 /* SW pte type bit */
227#define _PAGE_YOUNG 0x004 /* SW pte young bit */
228#define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
0944fe3f
MS		 229#define _PAGE_READ 0x010 /* SW pte read bit */
230#define _PAGE_WRITE 0x020 /* SW pte write bit */
231#define _PAGE_SPECIAL 0x040 /* SW associated with special page */
b31288fa 232#define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
a08cb629 233#define __HAVE_ARCH_PTE_SPECIAL
1da177e4 234
138c9021 235/* Set of bits not changed in pte_modify */
abf09bed 236#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \
e5098611 237 _PAGE_DIRTY | _PAGE_YOUNG)
53492b1d 238
83377484 239/*
e5098611
MS		 240 * handle_pte_fault uses pte_present, pte_none and pte_file to find out the
241 * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit
242 * is used to distinguish present from not-present ptes. It is changed only
243 * with the page table lock held.
83377484 244 *
e5098611
MS		 245 * The following table gives the different possible bit combinations for
246 * the pte hardware and software bits in the last 12 bits of a pte:
83377484 247 *
0944fe3f
MS		 248 * 842100000000
249 * 000084210000
250 * 000000008421
251 * .IR...wrdytp
252 * empty .10...000000
253 * swap .10...xxxx10
254 * file .11...xxxxx0
255 * prot-none, clean, old .11...000001
256 * prot-none, clean, young .11...000101
257 * prot-none, dirty, old .10...001001
258 * prot-none, dirty, young .10...001101
259 * read-only, clean, old .11...010001
260 * read-only, clean, young .01...010101
261 * read-only, dirty, old .11...011001
262 * read-only, dirty, young .01...011101
263 * read-write, clean, old .11...110001
264 * read-write, clean, young .01...110101
265 * read-write, dirty, old .10...111001
266 * read-write, dirty, young .00...111101
e5098611
MS		 267 *
268 * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001
269 * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400
270 * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600
271 * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402
83377484
MS		 272 */
273
f4815ac6 274#ifndef CONFIG_64BIT
1da177e4 275
3610cce8
MS		 276/* Bits in the segment table address-space-control-element */
277#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
278#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
279#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
280#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
281#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
1da177e4 282
3610cce8 283/* Bits in the segment table entry */
0944fe3f 284#define _SEGMENT_ENTRY_BITS 0x7fffffffUL /* Valid segment table bits */
3610cce8 285#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
e5098611
MS		 286#define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
287#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
3610cce8
MS		 288#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
289#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
0944fe3f 290#define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_PROTECT
1da177e4 291
3610cce8 292#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
e5098611 293#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
1da177e4 294
0944fe3f
MS		 295/*
296 * Segment table entry encoding (I = invalid, R = read-only bit):
297 * ..R...I.....
298 * prot-none ..1...1.....
299 * read-only ..1...0.....
300 * read-write ..0...0.....
301 * empty ..0...1.....
302 */
303
6c61cfe9 304/* Page status table bits for virtualization */
0d0dafc1
MS		 305#define PGSTE_ACC_BITS 0xf0000000UL
306#define PGSTE_FP_BIT 0x08000000UL
307#define PGSTE_PCL_BIT 0x00800000UL
308#define PGSTE_HR_BIT 0x00400000UL
309#define PGSTE_HC_BIT 0x00200000UL
310#define PGSTE_GR_BIT 0x00040000UL
311#define PGSTE_GC_BIT 0x00020000UL
0944fe3f 312#define PGSTE_IN_BIT 0x00008000UL /* IPTE notify bit */
6c61cfe9 313
f4815ac6 314#else /* CONFIG_64BIT */
1da177e4 315
3610cce8
MS		 316/* Bits in the segment/region table address-space-control-element */
317#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
318#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
319#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
320#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
321#define _ASCE_REAL_SPACE 0x20 /* real space control */
322#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
323#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
324#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
325#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
326#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
327#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
328
329/* Bits in the region table entry */
330#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
e5098611
MS		 331#define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
332#define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
3610cce8
MS		 333#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
334#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
335#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
336#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
337#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
338
339#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
e5098611 340#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
3610cce8 341#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
e5098611 342#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
3610cce8 343#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
e5098611 344#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
3610cce8 345
18da2369 346#define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
1819ed1f
HC		 347#define _REGION3_ENTRY_RO 0x200 /* page protection bit */
348#define _REGION3_ENTRY_CO 0x100 /* change-recording override */
18da2369 349
1da177e4 350/* Bits in the segment table entry */
0944fe3f
MS		 351#define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL
352#define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff1ff33UL
ea81531d 353#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
3610cce8 354#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
e5098611
MS		 355#define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
356#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
1da177e4 357
3610cce8 358#define _SEGMENT_ENTRY (0)
e5098611 359#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
3610cce8 360
53492b1d
GS		 361#define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
362#define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
e5098611 363#define _SEGMENT_ENTRY_SPLIT 0x001 /* THP splitting bit */
0944fe3f
MS		 364#define _SEGMENT_ENTRY_YOUNG 0x002 /* SW segment young bit */
365#define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_YOUNG
366
367/*
368 * Segment table entry encoding (R = read-only, I = invalid, y = young bit):
369 * ..R...I...y.
370 * prot-none, old ..0...1...1.
371 * prot-none, young ..1...1...1.
372 * read-only, old ..1...1...0.
373 * read-only, young ..1...0...1.
374 * read-write, old ..0...1...0.
375 * read-write, young ..0...0...1.
376 * The segment table origin is used to distinguish empty (origin==0) from
377 * read-write, old segment table entries (origin!=0)
378 */
e5098611 379
75077afb 380#define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */
53492b1d 381
1ae1c1d0
GS		 382/* Set of bits not changed in pmd_modify */
383#define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
384 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
385
6c61cfe9 386/* Page status table bits for virtualization */
0d0dafc1
MS		 387#define PGSTE_ACC_BITS 0xf000000000000000UL
388#define PGSTE_FP_BIT 0x0800000000000000UL
389#define PGSTE_PCL_BIT 0x0080000000000000UL
390#define PGSTE_HR_BIT 0x0040000000000000UL
391#define PGSTE_HC_BIT 0x0020000000000000UL
392#define PGSTE_GR_BIT 0x0004000000000000UL
393#define PGSTE_GC_BIT 0x0002000000000000UL
0944fe3f 394#define PGSTE_IN_BIT 0x0000800000000000UL /* IPTE notify bit */
6c61cfe9 395
f4815ac6 396#endif /* CONFIG_64BIT */
1da177e4 397
b31288fa
KW		 398/* Guest Page State used for virtualization */
399#define _PGSTE_GPS_ZERO 0x0000000080000000UL
400#define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL
401#define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL
402#define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL
403
1da177e4 404/*
3610cce8
MS		 405 * A user page table pointer has the space-switch-event bit, the
406 * private-space-control bit and the storage-alteration-event-control
407 * bit set. A kernel page table pointer doesn't need them.
1da177e4 408 */
3610cce8
MS		 409#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
410 _ASCE_ALT_EVENT)
1da177e4 411
1da177e4 412/*
9282ed92 413 * Page protection definitions.
1da177e4 414 */
e5098611 415#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID)
0944fe3f
MS		 416#define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \
417 _PAGE_INVALID | _PAGE_PROTECT)
418#define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
419 _PAGE_INVALID | _PAGE_PROTECT)
420
421#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
422 _PAGE_YOUNG | _PAGE_DIRTY)
423#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
424 _PAGE_YOUNG | _PAGE_DIRTY)
425#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
426 _PAGE_PROTECT)
1da177e4
LT		 427
428/*
043d0708
MS		 429 * On s390 the page table entry has an invalid bit and a read-only bit.
430 * Read permission implies execute permission and write permission
431 * implies read permission.
1da177e4
LT		 432 */
433 /*xwr*/
9282ed92 434#define __P000 PAGE_NONE
e5098611
MS		 435#define __P001 PAGE_READ
436#define __P010 PAGE_READ
437#define __P011 PAGE_READ
438#define __P100 PAGE_READ
439#define __P101 PAGE_READ
440#define __P110 PAGE_READ
441#define __P111 PAGE_READ
9282ed92
GS		 442
443#define __S000 PAGE_NONE
e5098611
MS		 444#define __S001 PAGE_READ
445#define __S010 PAGE_WRITE
446#define __S011 PAGE_WRITE
447#define __S100 PAGE_READ
448#define __S101 PAGE_READ
449#define __S110 PAGE_WRITE
450#define __S111 PAGE_WRITE
1da177e4 451
106c992a
GS		 452/*
453 * Segment entry (large page) protection definitions.
454 */
e5098611 455#define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
0944fe3f
MS		 456 _SEGMENT_ENTRY_NONE)
457#define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_INVALID | \
e5098611 458 _SEGMENT_ENTRY_PROTECT)
0944fe3f 459#define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_INVALID)
106c992a 460
b2fa47e6
MS		 461static inline int mm_has_pgste(struct mm_struct *mm)
462{
463#ifdef CONFIG_PGSTE
464 if (unlikely(mm->context.has_pgste))
465 return 1;
466#endif
467 return 0;
468}
1da177e4
LT		 469/*
470 * pgd/pmd/pte query functions
471 */
f4815ac6 472#ifndef CONFIG_64BIT
1da177e4 473
4448aaf0
AB		 474static inline int pgd_present(pgd_t pgd) { return 1; }
475static inline int pgd_none(pgd_t pgd) { return 0; }
476static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 477
190a1d72
MS		 478static inline int pud_present(pud_t pud) { return 1; }
479static inline int pud_none(pud_t pud) { return 0; }
18da2369 480static inline int pud_large(pud_t pud) { return 0; }
190a1d72
MS		 481static inline int pud_bad(pud_t pud) { return 0; }
482
f4815ac6 483#else /* CONFIG_64BIT */
1da177e4 484
5a216a20
MS		 485static inline int pgd_present(pgd_t pgd)
486{
6252d702
MS		 487 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
488 return 1;
5a216a20
MS		 489 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
490}
491
492static inline int pgd_none(pgd_t pgd)
493{
6252d702
MS		 494 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
495 return 0;
e5098611 496 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
5a216a20
MS		 497}
498
499static inline int pgd_bad(pgd_t pgd)
500{
6252d702
MS		 501 /*
502 * With dynamic page table levels the pgd can be a region table
503 * entry or a segment table entry. Check for the bit that are
504 * invalid for either table entry.
505 */
5a216a20 506 unsigned long mask =
e5098611 507 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
5a216a20
MS		 508 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
509 return (pgd_val(pgd) & mask) != 0;
510}
190a1d72
MS		 511
512static inline int pud_present(pud_t pud)
1da177e4 513{
6252d702
MS		 514 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
515 return 1;
0d017923 516 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 517}
518
190a1d72 519static inline int pud_none(pud_t pud)
1da177e4 520{
6252d702
MS		 521 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
522 return 0;
e5098611 523 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL;
1da177e4
LT		 524}
525
18da2369
HC		 526static inline int pud_large(pud_t pud)
527{
528 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
529 return 0;
530 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
531}
532
190a1d72 533static inline int pud_bad(pud_t pud)
1da177e4 534{
6252d702
MS		 535 /*
536 * With dynamic page table levels the pud can be a region table
537 * entry or a segment table entry. Check for the bit that are
538 * invalid for either table entry.
539 */
5a216a20 540 unsigned long mask =
e5098611 541 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
5a216a20
MS		 542 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
543 return (pud_val(pud) & mask) != 0;
1da177e4
LT		 544}
545
f4815ac6 546#endif /* CONFIG_64BIT */
3610cce8 547
4448aaf0 548static inline int pmd_present(pmd_t pmd)
1da177e4 549{
e5098611 550 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 551}
552
4448aaf0 553static inline int pmd_none(pmd_t pmd)
1da177e4 554{
e5098611 555 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 556}
557
378b1e7a
HC		 558static inline int pmd_large(pmd_t pmd)
559{
560#ifdef CONFIG_64BIT
e5098611 561 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
378b1e7a
HC		 562#else
563 return 0;
564#endif
565}
566
0944fe3f
MS		 567static inline int pmd_prot_none(pmd_t pmd)
568{
569 return (pmd_val(pmd) & _SEGMENT_ENTRY_INVALID) &&
570 (pmd_val(pmd) & _SEGMENT_ENTRY_NONE);
571}
572
4448aaf0 573static inline int pmd_bad(pmd_t pmd)
1da177e4 574{
0944fe3f
MS		 575#ifdef CONFIG_64BIT
576 if (pmd_large(pmd))
577 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0;
578#endif
579 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
1da177e4
LT		 580}
581
75077afb
GS		 582#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
583extern void pmdp_splitting_flush(struct vm_area_struct *vma,
584 unsigned long addr, pmd_t *pmdp);
585
1ae1c1d0
GS		 586#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
587extern int pmdp_set_access_flags(struct vm_area_struct *vma,
588 unsigned long address, pmd_t *pmdp,
589 pmd_t entry, int dirty);
590
591#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
592extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
593 unsigned long address, pmd_t *pmdp);
594
595#define __HAVE_ARCH_PMD_WRITE
596static inline int pmd_write(pmd_t pmd)
597{
0944fe3f
MS		 598 if (pmd_prot_none(pmd))
599 return 0;
e5098611 600 return (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) == 0;
1ae1c1d0
GS		 601}
602
603static inline int pmd_young(pmd_t pmd)
604{
0944fe3f
MS		 605 int young = 0;
606#ifdef CONFIG_64BIT
607 if (pmd_prot_none(pmd))
608 young = (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) != 0;
609 else
610 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
611#endif
612 return young;
1ae1c1d0
GS		 613}
614
e5098611 615static inline int pte_present(pte_t pte)
1da177e4 616{
e5098611
MS		 617 /* Bit pattern: (pte & 0x001) == 0x001 */
618 return (pte_val(pte) & _PAGE_PRESENT) != 0;
1da177e4
LT		 619}
620
e5098611 621static inline int pte_none(pte_t pte)
1da177e4 622{
e5098611
MS		 623 /* Bit pattern: pte == 0x400 */
624 return pte_val(pte) == _PAGE_INVALID;
1da177e4
LT		 625}
626
b31288fa
KW		 627static inline int pte_swap(pte_t pte)
628{
629 /* Bit pattern: (pte & 0x603) == 0x402 */
630 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT |
631 _PAGE_TYPE | _PAGE_PRESENT))
632 == (_PAGE_INVALID | _PAGE_TYPE);
633}
634
4448aaf0 635static inline int pte_file(pte_t pte)
1da177e4 636{
e5098611
MS		 637 /* Bit pattern: (pte & 0x601) == 0x600 */
638 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT))
639 == (_PAGE_INVALID | _PAGE_PROTECT);
1da177e4
LT		 640}
641
7e675137
NP		 642static inline int pte_special(pte_t pte)
643{
a08cb629 644 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 645}
646
ba8a9229 647#define __HAVE_ARCH_PTE_SAME
b2fa47e6
MS		 648static inline int pte_same(pte_t a, pte_t b)
649{
650 return pte_val(a) == pte_val(b);
651}
1da177e4 652
b2fa47e6 653static inline pgste_t pgste_get_lock(pte_t *ptep)
5b7baf05 654{
b2fa47e6 655 unsigned long new = 0;
5b7baf05 656#ifdef CONFIG_PGSTE
b2fa47e6
MS		 657 unsigned long old;
658
5b7baf05 659 preempt_disable();
b2fa47e6
MS		 660 asm(
661 " lg %0,%2\n"
662 "0: lgr %1,%0\n"
0d0dafc1
MS		 663 " nihh %0,0xff7f\n" /* clear PCL bit in old */
664 " oihh %1,0x0080\n" /* set PCL bit in new */
b2fa47e6
MS		 665 " csg %0,%1,%2\n"
666 " jl 0b\n"
667 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
a8f6e7f7 668 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
5b7baf05 669#endif
b2fa47e6 670 return __pgste(new);
5b7baf05
CB		 671}
672
b2fa47e6 673static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 674{
675#ifdef CONFIG_PGSTE
b2fa47e6 676 asm(
0d0dafc1 677 " nihh %1,0xff7f\n" /* clear PCL bit */
b2fa47e6
MS		 678 " stg %1,%0\n"
679 : "=Q" (ptep[PTRS_PER_PTE])
a8f6e7f7
CB		 680 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
681 : "cc", "memory");
5b7baf05
CB		 682 preempt_enable();
683#endif
684}
685
d56c893d
MS		 686static inline pgste_t pgste_get(pte_t *ptep)
687{
688 unsigned long pgste = 0;
689#ifdef CONFIG_PGSTE
690 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE);
691#endif
692 return __pgste(pgste);
693}
694
3a82603b
CB		 695static inline void pgste_set(pte_t *ptep, pgste_t pgste)
696{
697#ifdef CONFIG_PGSTE
698 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
699#endif
700}
701
b2fa47e6 702static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 703{
704#ifdef CONFIG_PGSTE
0944fe3f 705 unsigned long address, bits, skey;
b2fa47e6 706
b56433cb 707 if (pte_val(*ptep) & _PAGE_INVALID)
09b53883 708 return pgste;
a43a9d93 709 address = pte_val(*ptep) & PAGE_MASK;
0944fe3f 710 skey = (unsigned long) page_get_storage_key(address);
b2fa47e6 711 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
0944fe3f
MS		 712 if (!(pgste_val(pgste) & PGSTE_HC_BIT) && (bits & _PAGE_CHANGED)) {
713 /* Transfer dirty + referenced bit to host bits in pgste */
714 pgste_val(pgste) |= bits << 52;
abf09bed 715 page_set_storage_key(address, skey ^ bits, 0);
0944fe3f
MS		 716 } else if (!(pgste_val(pgste) & PGSTE_HR_BIT) &&
717 (bits & _PAGE_REFERENCED)) {
718 /* Transfer referenced bit to host bit in pgste */
719 pgste_val(pgste) |= PGSTE_HR_BIT;
7c81878b 720 page_reset_referenced(address);
0944fe3f 721 }
b2fa47e6 722 /* Transfer page changed & referenced bit to guest bits in pgste */
0d0dafc1 723 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */
b2fa47e6 724 /* Copy page access key and fetch protection bit to pgste */
0944fe3f
MS		 725 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
726 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
b2fa47e6
MS		 727#endif
728 return pgste;
729
730}
731
732static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
733{
734#ifdef CONFIG_PGSTE
b56433cb 735 if (pte_val(*ptep) & _PAGE_INVALID)
09b53883 736 return pgste;
abf09bed 737 /* Get referenced bit from storage key */
0944fe3f
MS		 738 if (page_reset_referenced(pte_val(*ptep) & PAGE_MASK))
739 pgste_val(pgste) |= PGSTE_HR_BIT | PGSTE_GR_BIT;
b2fa47e6
MS		 740#endif
741 return pgste;
b2fa47e6
MS		 742}
743
abf09bed 744static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
b2fa47e6
MS		 745{
746#ifdef CONFIG_PGSTE
a43a9d93 747 unsigned long address;
338679f7 748 unsigned long nkey;
b2fa47e6 749
b56433cb 750 if (pte_val(entry) & _PAGE_INVALID)
09b53883 751 return;
338679f7 752 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
09b53883 753 address = pte_val(entry) & PAGE_MASK;
338679f7
CB		 754 /*
755 * Set page access key and fetch protection bit from pgste.
756 * The guest C/R information is still in the PGSTE, set real
757 * key C/R to 0.
758 */
fe489bf4 759 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
338679f7 760 page_set_storage_key(address, nkey, 0);
5b7baf05
CB		 761#endif
762}
763
abf09bed
MS		 764static inline void pgste_set_pte(pte_t *ptep, pte_t entry)
765{
af0ebc40
MS		 766 if (!MACHINE_HAS_ESOP &&
767 (pte_val(entry) & _PAGE_PRESENT) &&
768 (pte_val(entry) & _PAGE_WRITE)) {
abf09bed
MS		 769 /*
770 * Without enhanced suppression-on-protection force
771 * the dirty bit on for all writable ptes.
772 */
e5098611
MS		 773 pte_val(entry) |= _PAGE_DIRTY;
774 pte_val(entry) &= ~_PAGE_PROTECT;
abf09bed
MS		 775 }
776 *ptep = entry;
777}
778
e5992f2e
MS		 779/**
780 * struct gmap_struct - guest address space
781 * @mm: pointer to the parent mm_struct
782 * @table: pointer to the page directory
480e5926 783 * @asce: address space control element for gmap page table
e5992f2e 784 * @crst_list: list of all crst tables used in the guest address space
24eb3a82 785 * @pfault_enabled: defines if pfaults are applicable for the guest
e5992f2e
MS		 786 */
787struct gmap {
788 struct list_head list;
789 struct mm_struct *mm;
790 unsigned long *table;
480e5926 791 unsigned long asce;
2c70fe44 792 void *private;
e5992f2e 793 struct list_head crst_list;
24eb3a82 794 bool pfault_enabled;
e5992f2e
MS		 795};
796
797/**
798 * struct gmap_rmap - reverse mapping for segment table entries
d3383632 799 * @gmap: pointer to the gmap_struct
e5992f2e 800 * @entry: pointer to a segment table entry
d3383632 801 * @vmaddr: virtual address in the guest address space
e5992f2e
MS		 802 */
803struct gmap_rmap {
804 struct list_head list;
d3383632 805 struct gmap *gmap;
e5992f2e 806 unsigned long *entry;
d3383632 807 unsigned long vmaddr;
e5992f2e
MS		 808};
809
810/**
811 * struct gmap_pgtable - gmap information attached to a page table
812 * @vmaddr: address of the 1MB segment in the process virtual memory
d3383632 813 * @mapper: list of segment table entries mapping a page table
e5992f2e
MS		 814 */
815struct gmap_pgtable {
816 unsigned long vmaddr;
817 struct list_head mapper;
818};
819
d3383632
MS		 820/**
821 * struct gmap_notifier - notify function block for page invalidation
822 * @notifier_call: address of callback function
823 */
824struct gmap_notifier {
825 struct list_head list;
826 void (*notifier_call)(struct gmap *gmap, unsigned long address);
827};
828
e5992f2e
MS		 829struct gmap *gmap_alloc(struct mm_struct *mm);
830void gmap_free(struct gmap *gmap);
831void gmap_enable(struct gmap *gmap);
832void gmap_disable(struct gmap *gmap);
833int gmap_map_segment(struct gmap *gmap, unsigned long from,
d3383632 834 unsigned long to, unsigned long len);
e5992f2e 835int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
c5034945
HC		 836unsigned long __gmap_translate(unsigned long address, struct gmap *);
837unsigned long gmap_translate(unsigned long address, struct gmap *);
499069e1 838unsigned long __gmap_fault(unsigned long address, struct gmap *);
e5992f2e 839unsigned long gmap_fault(unsigned long address, struct gmap *);
388186bc 840void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
b31288fa 841void __gmap_zap(unsigned long address, struct gmap *);
e5992f2e 842
d3383632
MS		 843void gmap_register_ipte_notifier(struct gmap_notifier *);
844void gmap_unregister_ipte_notifier(struct gmap_notifier *);
845int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
aaeff84a 846void gmap_do_ipte_notify(struct mm_struct *, pte_t *);
d3383632
MS		 847
848static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
d3383632
MS		 849 pte_t *ptep, pgste_t pgste)
850{
851#ifdef CONFIG_PGSTE
0d0dafc1
MS		 852 if (pgste_val(pgste) & PGSTE_IN_BIT) {
853 pgste_val(pgste) &= ~PGSTE_IN_BIT;
aaeff84a 854 gmap_do_ipte_notify(mm, ptep);
d3383632
MS		 855 }
856#endif
857 return pgste;
858}
859
b2fa47e6
MS		 860/*
861 * Certain architectures need to do special things when PTEs
862 * within a page table are directly modified. Thus, the following
863 * hook is made available.
864 */
865static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
866 pte_t *ptep, pte_t entry)
867{
868 pgste_t pgste;
869
870 if (mm_has_pgste(mm)) {
871 pgste = pgste_get_lock(ptep);
b31288fa 872 pgste_val(pgste) &= ~_PGSTE_GPS_ZERO;
abf09bed
MS		 873 pgste_set_key(ptep, pgste, entry);
874 pgste_set_pte(ptep, entry);
b2fa47e6 875 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 876 } else {
877 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1)
878 pte_val(entry) |= _PAGE_CO;
b2fa47e6 879 *ptep = entry;
abf09bed 880 }
b2fa47e6
MS		 881}
882
1da177e4
LT		 883/*
884 * query functions pte_write/pte_dirty/pte_young only work if
885 * pte_present() is true. Undefined behaviour if not..
886 */
4448aaf0 887static inline int pte_write(pte_t pte)
1da177e4 888{
e5098611 889 return (pte_val(pte) & _PAGE_WRITE) != 0;
1da177e4
LT		 890}
891
4448aaf0 892static inline int pte_dirty(pte_t pte)
1da177e4 893{
e5098611 894 return (pte_val(pte) & _PAGE_DIRTY) != 0;
1da177e4
LT		 895}
896
4448aaf0 897static inline int pte_young(pte_t pte)
1da177e4 898{
0944fe3f 899 return (pte_val(pte) & _PAGE_YOUNG) != 0;
1da177e4
LT		 900}
901
b31288fa
KW		 902#define __HAVE_ARCH_PTE_UNUSED
903static inline int pte_unused(pte_t pte)
904{
905 return pte_val(pte) & _PAGE_UNUSED;
906}
907
1da177e4
LT		 908/*
909 * pgd/pmd/pte modification functions
910 */
911
b2fa47e6 912static inline void pgd_clear(pgd_t *pgd)
5a216a20 913{
f4815ac6 914#ifdef CONFIG_64BIT
6252d702
MS		 915 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
916 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
b2fa47e6 917#endif
5a216a20
MS		 918}
919
b2fa47e6 920static inline void pud_clear(pud_t *pud)
1da177e4 921{
f4815ac6 922#ifdef CONFIG_64BIT
6252d702
MS		 923 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
924 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
b2fa47e6 925#endif
1da177e4
LT		 926}
927
b2fa47e6 928static inline void pmd_clear(pmd_t *pmdp)
1da177e4 929{
e5098611 930 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 931}
932
4448aaf0 933static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 934{
e5098611 935 pte_val(*ptep) = _PAGE_INVALID;
1da177e4
LT		 936}
937
938/*
939 * The following pte modification functions only work if
940 * pte_present() is true. Undefined behaviour if not..
941 */
4448aaf0 942static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 943{
138c9021 944 pte_val(pte) &= _PAGE_CHG_MASK;
1da177e4 945 pte_val(pte) |= pgprot_val(newprot);
0944fe3f
MS		 946 /*
947 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the
948 * invalid bit set, clear it again for readable, young pages
949 */
950 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
951 pte_val(pte) &= ~_PAGE_INVALID;
952 /*
953 * newprot for PAGE_READ and PAGE_WRITE has the page protection
954 * bit set, clear it again for writable, dirty pages
955 */
e5098611
MS		 956 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
957 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 958 return pte;
959}
960
4448aaf0 961static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 962{
e5098611
MS		 963 pte_val(pte) &= ~_PAGE_WRITE;
964 pte_val(pte) |= _PAGE_PROTECT;
1da177e4
LT		 965 return pte;
966}
967
4448aaf0 968static inline pte_t pte_mkwrite(pte_t pte)
1da177e4 969{
e5098611
MS		 970 pte_val(pte) |= _PAGE_WRITE;
971 if (pte_val(pte) & _PAGE_DIRTY)
972 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 973 return pte;
974}
975
4448aaf0 976static inline pte_t pte_mkclean(pte_t pte)
1da177e4 977{
e5098611
MS		 978 pte_val(pte) &= ~_PAGE_DIRTY;
979 pte_val(pte) |= _PAGE_PROTECT;
1da177e4
LT		 980 return pte;
981}
982
4448aaf0 983static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 984{
e5098611
MS		 985 pte_val(pte) |= _PAGE_DIRTY;
986 if (pte_val(pte) & _PAGE_WRITE)
987 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 988 return pte;
989}
990
4448aaf0 991static inline pte_t pte_mkold(pte_t pte)
1da177e4 992{
e5098611 993 pte_val(pte) &= ~_PAGE_YOUNG;
0944fe3f 994 pte_val(pte) |= _PAGE_INVALID;
1da177e4
LT		 995 return pte;
996}
997
4448aaf0 998static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 999{
0944fe3f
MS		 1000 pte_val(pte) |= _PAGE_YOUNG;
1001 if (pte_val(pte) & _PAGE_READ)
1002 pte_val(pte) &= ~_PAGE_INVALID;
1da177e4
LT		 1003 return pte;
1004}
1005
7e675137
NP		 1006static inline pte_t pte_mkspecial(pte_t pte)
1007{
a08cb629 1008 pte_val(pte) |= _PAGE_SPECIAL;
7e675137
NP		 1009 return pte;
1010}
1011
84afdcee
HC		 1012#ifdef CONFIG_HUGETLB_PAGE
1013static inline pte_t pte_mkhuge(pte_t pte)
1014{
e5098611 1015 pte_val(pte) |= _PAGE_LARGE;
84afdcee
HC		 1016 return pte;
1017}
1018#endif
1019
15e86b0c 1020/*
b2fa47e6 1021 * Get (and clear) the user dirty bit for a pte.
15e86b0c 1022 */
b2fa47e6
MS		 1023static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
1024 pte_t *ptep)
15e86b0c 1025{
b2fa47e6
MS		 1026 pgste_t pgste;
1027 int dirty = 0;
1028
1029 if (mm_has_pgste(mm)) {
1030 pgste = pgste_get_lock(ptep);
1031 pgste = pgste_update_all(ptep, pgste);
0944fe3f
MS		 1032 dirty = !!(pgste_val(pgste) & PGSTE_HC_BIT);
1033 pgste_val(pgste) &= ~PGSTE_HC_BIT;
b2fa47e6
MS		 1034 pgste_set_unlock(ptep, pgste);
1035 return dirty;
15e86b0c 1036 }
15e86b0c
FF		 1037 return dirty;
1038}
b2fa47e6
MS		 1039
1040/*
1041 * Get (and clear) the user referenced bit for a pte.
1042 */
1043static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
1044 pte_t *ptep)
1045{
1046 pgste_t pgste;
1047 int young = 0;
1048
1049 if (mm_has_pgste(mm)) {
1050 pgste = pgste_get_lock(ptep);
1051 pgste = pgste_update_young(ptep, pgste);
0944fe3f
MS		 1052 young = !!(pgste_val(pgste) & PGSTE_HR_BIT);
1053 pgste_val(pgste) &= ~PGSTE_HR_BIT;
b2fa47e6
MS		 1054 pgste_set_unlock(ptep, pgste);
1055 }
1056 return young;
1057}
15e86b0c 1058
9282ed92 1059static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 1060{
53e857f3
MS		 1061 unsigned long pto = (unsigned long) ptep;
1062
f4815ac6 1063#ifndef CONFIG_64BIT
53e857f3
MS		 1064 /* pto in ESA mode must point to the start of the segment table */
1065 pto &= 0x7ffffc00;
9282ed92 1066#endif
53e857f3
MS		 1067 /* Invalidation + global TLB flush for the pte */
1068 asm volatile(
1069 " ipte %2,%3"
1070 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
1071}
1072
1b948d6c
MS		 1073static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep)
1074{
1075 unsigned long pto = (unsigned long) ptep;
1076
1077#ifndef CONFIG_64BIT
1078 /* pto in ESA mode must point to the start of the segment table */
1079 pto &= 0x7ffffc00;
1080#endif
1081 /* Invalidation + local TLB flush for the pte */
1082 asm volatile(
1083 " .insn rrf,0xb2210000,%2,%3,0,1"
1084 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
1085}
1086
53e857f3
MS		 1087static inline void ptep_flush_direct(struct mm_struct *mm,
1088 unsigned long address, pte_t *ptep)
1089{
1b948d6c
MS		 1090 int active, count;
1091
53e857f3
MS		 1092 if (pte_val(*ptep) & _PAGE_INVALID)
1093 return;
1b948d6c
MS		 1094 active = (mm == current->active_mm) ? 1 : 0;
1095 count = atomic_add_return(0x10000, &mm->context.attach_count);
1096 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
1097 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1098 __ptep_ipte_local(address, ptep);
1099 else
1100 __ptep_ipte(address, ptep);
1101 atomic_sub(0x10000, &mm->context.attach_count);
9282ed92
GS		 1102}
1103
5c474a1e
MS		 1104static inline void ptep_flush_lazy(struct mm_struct *mm,
1105 unsigned long address, pte_t *ptep)
1106{
53e857f3 1107 int active, count;
5c474a1e 1108
53e857f3
MS		 1109 if (pte_val(*ptep) & _PAGE_INVALID)
1110 return;
1111 active = (mm == current->active_mm) ? 1 : 0;
1112 count = atomic_add_return(0x10000, &mm->context.attach_count);
1113 if ((count & 0xffff) <= active) {
1114 pte_val(*ptep) |= _PAGE_INVALID;
5c474a1e 1115 mm->context.flush_mm = 1;
53e857f3
MS		 1116 } else
1117 __ptep_ipte(address, ptep);
1118 atomic_sub(0x10000, &mm->context.attach_count);
5c474a1e
MS		 1119}
1120
0944fe3f
MS		 1121#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1122static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1123 unsigned long addr, pte_t *ptep)
1124{
1125 pgste_t pgste;
1126 pte_t pte;
1127 int young;
1128
1129 if (mm_has_pgste(vma->vm_mm)) {
1130 pgste = pgste_get_lock(ptep);
6e5a40a4 1131 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
0944fe3f
MS		 1132 }
1133
1134 pte = *ptep;
53e857f3 1135 ptep_flush_direct(vma->vm_mm, addr, ptep);
0944fe3f
MS		 1136 young = pte_young(pte);
1137 pte = pte_mkold(pte);
1138
1139 if (mm_has_pgste(vma->vm_mm)) {
1140 pgste_set_pte(ptep, pte);
1141 pgste_set_unlock(ptep, pgste);
1142 } else
1143 *ptep = pte;
1144
1145 return young;
1146}
1147
1148#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1149static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1150 unsigned long address, pte_t *ptep)
1151{
1152 return ptep_test_and_clear_young(vma, address, ptep);
1153}
1154
ba8a9229
MS		 1155/*
1156 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1157 * both clear the TLB for the unmapped pte. The reason is that
1158 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1159 * to modify an active pte. The sequence is
1160 * 1) ptep_get_and_clear
1161 * 2) set_pte_at
1162 * 3) flush_tlb_range
1163 * On s390 the tlb needs to get flushed with the modification of the pte
1164 * if the pte is active. The only way how this can be implemented is to
1165 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1166 * is a nop.
1167 */
1168#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
b2fa47e6
MS		 1169static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1170 unsigned long address, pte_t *ptep)
1171{
1172 pgste_t pgste;
1173 pte_t pte;
1174
d3383632 1175 if (mm_has_pgste(mm)) {
b2fa47e6 1176 pgste = pgste_get_lock(ptep);
6e5a40a4 1177 pgste = pgste_ipte_notify(mm, ptep, pgste);
d3383632 1178 }
b2fa47e6
MS		 1179
1180 pte = *ptep;
5c474a1e 1181 ptep_flush_lazy(mm, address, ptep);
e5098611 1182 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6
MS		 1183
1184 if (mm_has_pgste(mm)) {
1185 pgste = pgste_update_all(&pte, pgste);
1186 pgste_set_unlock(ptep, pgste);
1187 }
1188 return pte;
1189}
1190
1191#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1192static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1193 unsigned long address,
1194 pte_t *ptep)
1195{
d3383632 1196 pgste_t pgste;
b2fa47e6
MS		 1197 pte_t pte;
1198
d3383632
MS		 1199 if (mm_has_pgste(mm)) {
1200 pgste = pgste_get_lock(ptep);
6e5a40a4 1201 pgste_ipte_notify(mm, ptep, pgste);
d3383632 1202 }
b2fa47e6
MS		 1203
1204 pte = *ptep;
5c474a1e 1205 ptep_flush_lazy(mm, address, ptep);
b56433cb 1206
3a82603b 1207 if (mm_has_pgste(mm)) {
b56433cb 1208 pgste = pgste_update_all(&pte, pgste);
3a82603b
CB		 1209 pgste_set(ptep, pgste);
1210 }
b2fa47e6
MS		 1211 return pte;
1212}
1213
1214static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1215 unsigned long address,
1216 pte_t *ptep, pte_t pte)
1217{
b56433cb
CB		 1218 pgste_t pgste;
1219
abf09bed 1220 if (mm_has_pgste(mm)) {
d56c893d 1221 pgste = pgste_get(ptep);
b56433cb 1222 pgste_set_key(ptep, pgste, pte);
abf09bed 1223 pgste_set_pte(ptep, pte);
b56433cb 1224 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1225 } else
1226 *ptep = pte;
b2fa47e6 1227}
ba8a9229
MS		 1228
1229#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22
MS		 1230static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1231 unsigned long address, pte_t *ptep)
1232{
b2fa47e6
MS		 1233 pgste_t pgste;
1234 pte_t pte;
1235
d3383632 1236 if (mm_has_pgste(vma->vm_mm)) {
b2fa47e6 1237 pgste = pgste_get_lock(ptep);
6e5a40a4 1238 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
d3383632 1239 }
b2fa47e6
MS		 1240
1241 pte = *ptep;
53e857f3 1242 ptep_flush_direct(vma->vm_mm, address, ptep);
e5098611 1243 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6
MS		 1244
1245 if (mm_has_pgste(vma->vm_mm)) {
b31288fa
KW		 1246 if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) ==
1247 _PGSTE_GPS_USAGE_UNUSED)
1248 pte_val(pte) |= _PAGE_UNUSED;
b2fa47e6
MS		 1249 pgste = pgste_update_all(&pte, pgste);
1250 pgste_set_unlock(ptep, pgste);
1251 }
1da177e4
LT		 1252 return pte;
1253}
1254
ba8a9229
MS		 1255/*
1256 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1257 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1258 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1259 * cannot be accessed while the batched unmap is running. In this case
1260 * full==1 and a simple pte_clear is enough. See tlb.h.
1261 */
1262#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1263static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
b2fa47e6 1264 unsigned long address,
ba8a9229 1265 pte_t *ptep, int full)
1da177e4 1266{
b2fa47e6
MS		 1267 pgste_t pgste;
1268 pte_t pte;
1269
a055f66a 1270 if (!full && mm_has_pgste(mm)) {
b2fa47e6 1271 pgste = pgste_get_lock(ptep);
6e5a40a4 1272 pgste = pgste_ipte_notify(mm, ptep, pgste);
d3383632 1273 }
ba8a9229 1274
b2fa47e6
MS		 1275 pte = *ptep;
1276 if (!full)
5c474a1e 1277 ptep_flush_lazy(mm, address, ptep);
e5098611 1278 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6 1279
a055f66a 1280 if (!full && mm_has_pgste(mm)) {
b2fa47e6
MS		 1281 pgste = pgste_update_all(&pte, pgste);
1282 pgste_set_unlock(ptep, pgste);
1283 }
ba8a9229 1284 return pte;
1da177e4
LT		 1285}
1286
ba8a9229 1287#define __HAVE_ARCH_PTEP_SET_WRPROTECT
b2fa47e6
MS		 1288static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1289 unsigned long address, pte_t *ptep)
1290{
1291 pgste_t pgste;
1292 pte_t pte = *ptep;
1293
1294 if (pte_write(pte)) {
d3383632 1295 if (mm_has_pgste(mm)) {
b2fa47e6 1296 pgste = pgste_get_lock(ptep);
6e5a40a4 1297 pgste = pgste_ipte_notify(mm, ptep, pgste);
d3383632 1298 }
b2fa47e6 1299
5c474a1e 1300 ptep_flush_lazy(mm, address, ptep);
abf09bed 1301 pte = pte_wrprotect(pte);
b2fa47e6 1302
abf09bed
MS		 1303 if (mm_has_pgste(mm)) {
1304 pgste_set_pte(ptep, pte);
b2fa47e6 1305 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1306 } else
1307 *ptep = pte;
b2fa47e6
MS		 1308 }
1309 return pte;
1310}
ba8a9229
MS		 1311
1312#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
b2fa47e6
MS		 1313static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1314 unsigned long address, pte_t *ptep,
1315 pte_t entry, int dirty)
1316{
1317 pgste_t pgste;
1318
1319 if (pte_same(*ptep, entry))
1320 return 0;
d3383632 1321 if (mm_has_pgste(vma->vm_mm)) {
b2fa47e6 1322 pgste = pgste_get_lock(ptep);
6e5a40a4 1323 pgste = pgste_ipte_notify(vma->vm_mm, ptep, pgste);
d3383632 1324 }
b2fa47e6 1325
53e857f3 1326 ptep_flush_direct(vma->vm_mm, address, ptep);
b2fa47e6 1327
abf09bed
MS		 1328 if (mm_has_pgste(vma->vm_mm)) {
1329 pgste_set_pte(ptep, entry);
b2fa47e6 1330 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1331 } else
1332 *ptep = entry;
b2fa47e6
MS		 1333 return 1;
1334}
1da177e4 1335
1da177e4
LT		 1336/*
1337 * Conversion functions: convert a page and protection to a page entry,
1338 * and a page entry and page directory to the page they refer to.
1339 */
1340static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1341{
1342 pte_t __pte;
1343 pte_val(__pte) = physpage + pgprot_val(pgprot);
0944fe3f 1344 return pte_mkyoung(__pte);
1da177e4
LT		 1345}
1346
2dcea57a
HC		 1347static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1348{
0b2b6e1d 1349 unsigned long physpage = page_to_phys(page);
abf09bed 1350 pte_t __pte = mk_pte_phys(physpage, pgprot);
1da177e4 1351
e5098611
MS		 1352 if (pte_write(__pte) && PageDirty(page))
1353 __pte = pte_mkdirty(__pte);
abf09bed 1354 return __pte;
2dcea57a
HC		 1355}
1356
190a1d72
MS		 1357#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1358#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1359#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1360#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1da177e4 1361
190a1d72
MS		 1362#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1363#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4 1364
f4815ac6 1365#ifndef CONFIG_64BIT
1da177e4 1366
190a1d72
MS		 1367#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1368#define pud_deref(pmd) ({ BUG(); 0UL; })
1369#define pgd_deref(pmd) ({ BUG(); 0UL; })
46a82b2d 1370
190a1d72
MS		 1371#define pud_offset(pgd, address) ((pud_t *) pgd)
1372#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1da177e4 1373
f4815ac6 1374#else /* CONFIG_64BIT */
1da177e4 1375
190a1d72
MS		 1376#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1377#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
5a216a20 1378#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1da177e4 1379
5a216a20
MS		 1380static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1381{
6252d702
MS		 1382 pud_t *pud = (pud_t *) pgd;
1383 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1384 pud = (pud_t *) pgd_deref(*pgd);
5a216a20
MS		 1385 return pud + pud_index(address);
1386}
1da177e4 1387
190a1d72 1388static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1da177e4 1389{
6252d702
MS		 1390 pmd_t *pmd = (pmd_t *) pud;
1391 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1392 pmd = (pmd_t *) pud_deref(*pud);
190a1d72 1393 return pmd + pmd_index(address);
1da177e4
LT		 1394}
1395
f4815ac6 1396#endif /* CONFIG_64BIT */
1da177e4 1397
190a1d72
MS		 1398#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1399#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1400#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 1401
190a1d72 1402#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1da177e4 1403
190a1d72
MS		 1404/* Find an entry in the lowest level page table.. */
1405#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1406#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1da177e4 1407#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1da177e4 1408#define pte_unmap(pte) do { } while (0)
1da177e4 1409
106c992a 1410#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1ae1c1d0
GS		 1411static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1412{
d8e7a33d 1413 /*
e5098611 1414 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx)
d8e7a33d
GS		 1415 * Convert to segment table entry format.
1416 */
1417 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1418 return pgprot_val(SEGMENT_NONE);
e5098611
MS		 1419 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ))
1420 return pgprot_val(SEGMENT_READ);
1421 return pgprot_val(SEGMENT_WRITE);
1ae1c1d0
GS		 1422}
1423
0944fe3f
MS		 1424static inline pmd_t pmd_mkyoung(pmd_t pmd)
1425{
1426#ifdef CONFIG_64BIT
1427 if (pmd_prot_none(pmd)) {
1428 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1429 } else {
1430 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
1431 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID;
1432 }
1433#endif
1434 return pmd;
1435}
1436
1437static inline pmd_t pmd_mkold(pmd_t pmd)
1438{
1439#ifdef CONFIG_64BIT
1440 if (pmd_prot_none(pmd)) {
1441 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1442 } else {
1443 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG;
1444 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1445 }
1446#endif
1447 return pmd;
1448}
1449
1ae1c1d0
GS		 1450static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1451{
0944fe3f
MS		 1452 int young;
1453
1454 young = pmd_young(pmd);
1ae1c1d0
GS		 1455 pmd_val(pmd) &= _SEGMENT_CHG_MASK;
1456 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
0944fe3f
MS		 1457 if (young)
1458 pmd = pmd_mkyoung(pmd);
1ae1c1d0
GS		 1459 return pmd;
1460}
1461
106c992a 1462static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1ae1c1d0 1463{
106c992a
GS		 1464 pmd_t __pmd;
1465 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
0944fe3f 1466 return pmd_mkyoung(__pmd);
1ae1c1d0
GS		 1467}
1468
1469static inline pmd_t pmd_mkwrite(pmd_t pmd)
1470{
0944fe3f
MS		 1471 /* Do not clobber PROT_NONE segments! */
1472 if (!pmd_prot_none(pmd))
e5098611 1473 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1ae1c1d0
GS		 1474 return pmd;
1475}
106c992a
GS		 1476#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1477
1b948d6c
MS		 1478static inline void __pmdp_csp(pmd_t *pmdp)
1479{
1480 register unsigned long reg2 asm("2") = pmd_val(*pmdp);
1481 register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
1482 _SEGMENT_ENTRY_INVALID;
1483 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
1484
1485 asm volatile(
1486 " csp %1,%3"
1487 : "=m" (*pmdp)
1488 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
1489}
1490
1491static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp)
1492{
1493 unsigned long sto;
1494
1495 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
1496 asm volatile(
1497 " .insn rrf,0xb98e0000,%2,%3,0,0"
1498 : "=m" (*pmdp)
1499 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
1500 : "cc" );
1501}
1502
1503static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp)
1504{
1505 unsigned long sto;
1506
1507 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
1508 asm volatile(
1509 " .insn rrf,0xb98e0000,%2,%3,0,1"
1510 : "=m" (*pmdp)
1511 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
1512 : "cc" );
1513}
1514
1515static inline void pmdp_flush_direct(struct mm_struct *mm,
1516 unsigned long address, pmd_t *pmdp)
1517{
1518 int active, count;
1519
1520 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
1521 return;
1522 if (!MACHINE_HAS_IDTE) {
1523 __pmdp_csp(pmdp);
1524 return;
1525 }
1526 active = (mm == current->active_mm) ? 1 : 0;
1527 count = atomic_add_return(0x10000, &mm->context.attach_count);
1528 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
1529 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1530 __pmdp_idte_local(address, pmdp);
1531 else
1532 __pmdp_idte(address, pmdp);
1533 atomic_sub(0x10000, &mm->context.attach_count);
1534}
1535
3eabaee9
MS		 1536static inline void pmdp_flush_lazy(struct mm_struct *mm,
1537 unsigned long address, pmd_t *pmdp)
1538{
53e857f3 1539 int active, count;
3eabaee9 1540
1b948d6c
MS		 1541 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
1542 return;
53e857f3
MS		 1543 active = (mm == current->active_mm) ? 1 : 0;
1544 count = atomic_add_return(0x10000, &mm->context.attach_count);
1545 if ((count & 0xffff) <= active) {
1546 pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID;
3eabaee9 1547 mm->context.flush_mm = 1;
1b948d6c
MS		 1548 } else if (MACHINE_HAS_IDTE)
1549 __pmdp_idte(address, pmdp);
1550 else
1551 __pmdp_csp(pmdp);
53e857f3 1552 atomic_sub(0x10000, &mm->context.attach_count);
3eabaee9
MS		 1553}
1554
106c992a
GS		 1555#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1556
1557#define __HAVE_ARCH_PGTABLE_DEPOSIT
6b0b50b0
AK		 1558extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1559 pgtable_t pgtable);
106c992a
GS		 1560
1561#define __HAVE_ARCH_PGTABLE_WITHDRAW
6b0b50b0 1562extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
106c992a
GS		 1563
1564static inline int pmd_trans_splitting(pmd_t pmd)
1565{
1566 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
1567}
1568
1569static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1570 pmd_t *pmdp, pmd_t entry)
1571{
e5098611 1572 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INVALID) && MACHINE_HAS_EDAT1)
106c992a
GS		 1573 pmd_val(entry) |= _SEGMENT_ENTRY_CO;
1574 *pmdp = entry;
1575}
1576
1577static inline pmd_t pmd_mkhuge(pmd_t pmd)
1578{
1579 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1580 return pmd;
1581}
1ae1c1d0
GS		 1582
1583static inline pmd_t pmd_wrprotect(pmd_t pmd)
1584{
0944fe3f
MS		 1585 /* Do not clobber PROT_NONE segments! */
1586 if (!pmd_prot_none(pmd))
1587 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1ae1c1d0
GS		 1588 return pmd;
1589}
1590
1591static inline pmd_t pmd_mkdirty(pmd_t pmd)
1592{
1593 /* No dirty bit in the segment table entry. */
1594 return pmd;
1595}
1596
1ae1c1d0
GS		 1597#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1598static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1599 unsigned long address, pmd_t *pmdp)
1600{
0944fe3f 1601 pmd_t pmd;
1ae1c1d0 1602
0944fe3f 1603 pmd = *pmdp;
1b948d6c 1604 pmdp_flush_direct(vma->vm_mm, address, pmdp);
0944fe3f
MS		 1605 *pmdp = pmd_mkold(pmd);
1606 return pmd_young(pmd);
1ae1c1d0
GS		 1607}
1608
1609#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1610static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1611 unsigned long address, pmd_t *pmdp)
1612{
1613 pmd_t pmd = *pmdp;
1614
1b948d6c 1615 pmdp_flush_direct(mm, address, pmdp);
1ae1c1d0
GS		 1616 pmd_clear(pmdp);
1617 return pmd;
1618}
1619
1620#define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1621static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1622 unsigned long address, pmd_t *pmdp)
1623{
1624 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1625}
1626
1627#define __HAVE_ARCH_PMDP_INVALIDATE
1628static inline void pmdp_invalidate(struct vm_area_struct *vma,
1629 unsigned long address, pmd_t *pmdp)
1630{
1b948d6c 1631 pmdp_flush_direct(vma->vm_mm, address, pmdp);
1ae1c1d0
GS		 1632}
1633
be328650
GS		 1634#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1635static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1636 unsigned long address, pmd_t *pmdp)
1637{
1638 pmd_t pmd = *pmdp;
1639
1640 if (pmd_write(pmd)) {
1b948d6c 1641 pmdp_flush_direct(mm, address, pmdp);
be328650
GS		 1642 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1643 }
1644}
1645
1ae1c1d0
GS		 1646#define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1647#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1648
1649static inline int pmd_trans_huge(pmd_t pmd)
1650{
1651 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1652}
1653
1654static inline int has_transparent_hugepage(void)
1655{
1656 return MACHINE_HAS_HPAGE ? 1 : 0;
1657}
1658
1659static inline unsigned long pmd_pfn(pmd_t pmd)
1660{
171c4006 1661 return pmd_val(pmd) >> PAGE_SHIFT;
1ae1c1d0 1662}
75077afb
GS		 1663#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1664
1da177e4
LT		 1665/*
1666 * 31 bit swap entry format:
1667 * A page-table entry has some bits we have to treat in a special way.
1668 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1669 * exception will occur instead of a page translation exception. The
1670 * specifiation exception has the bad habit not to store necessary
1671 * information in the lowcore.
e5098611
MS		 1672 * Bits 21, 22, 30 and 31 are used to indicate the page type.
1673 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1da177e4
LT		 1674 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1675 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1676 * plus 24 for the offset.
1677 * 0| offset |0110|o|type |00|
1678 * 0 0000000001111111111 2222 2 22222 33
1679 * 0 1234567890123456789 0123 4 56789 01
1680 *
1681 * 64 bit swap entry format:
1682 * A page-table entry has some bits we have to treat in a special way.
1683 * Bits 52 and bit 55 have to be zero, otherwise an specification
1684 * exception will occur instead of a page translation exception. The
1685 * specifiation exception has the bad habit not to store necessary
1686 * information in the lowcore.
e5098611
MS		 1687 * Bits 53, 54, 62 and 63 are used to indicate the page type.
1688 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1da177e4
LT		 1689 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1690 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1691 * plus 56 for the offset.
1692 * | offset |0110|o|type |00|
1693 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1694 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1695 */
f4815ac6 1696#ifndef CONFIG_64BIT
1da177e4
LT		 1697#define __SWP_OFFSET_MASK (~0UL >> 12)
1698#else
1699#define __SWP_OFFSET_MASK (~0UL >> 11)
1700#endif
4448aaf0 1701static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT		 1702{
1703 pte_t pte;
1704 offset &= __SWP_OFFSET_MASK;
e5098611 1705 pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) |
1da177e4
LT		 1706 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1707 return pte;
1708}
1709
1710#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1711#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1712#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1713
1714#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1715#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1716
f4815ac6 1717#ifndef CONFIG_64BIT
1da177e4 1718# define PTE_FILE_MAX_BITS 26
f4815ac6 1719#else /* CONFIG_64BIT */
1da177e4 1720# define PTE_FILE_MAX_BITS 59
f4815ac6 1721#endif /* CONFIG_64BIT */
1da177e4
LT		 1722
1723#define pte_to_pgoff(__pte) \
1724 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1725
1726#define pgoff_to_pte(__off) \
1727 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
e5098611 1728 | _PAGE_INVALID | _PAGE_PROTECT })
1da177e4
LT		 1729
1730#endif /* !__ASSEMBLY__ */
1731
1732#define kern_addr_valid(addr) (1)
1733
17f34580
HC		 1734extern int vmem_add_mapping(unsigned long start, unsigned long size);
1735extern int vmem_remove_mapping(unsigned long start, unsigned long size);
402b0862 1736extern int s390_enable_sie(void);
f4eb07c1 1737
1da177e4
LT		 1738/*
1739 * No page table caches to initialise
1740 */
765a0cac
HC		 1741static inline void pgtable_cache_init(void) { }
1742static inline void check_pgt_cache(void) { }
1da177e4 1743
1da177e4
LT		 1744#include <asm-generic/pgtable.h>
1745
1746#endif /* _S390_PAGE_H */
Linux kernel - Deliverables
This page took 0.795643 seconds and 5 git commands to generate.