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s390/mm,kvm: fix software dirty bits vs. kvm for old machines
[deliverable/linux.git] / arch / s390 / include / asm / pgtable.h
CommitLineData
1da177e4 1/*
1da177e4 2 * S390 version
a53c8fab 3 * Copyright IBM Corp. 1999, 2000
1da177e4
LT		 4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11#ifndef _ASM_S390_PGTABLE_H
12#define _ASM_S390_PGTABLE_H
13
1da177e4
LT		 14/*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29#ifndef __ASSEMBLY__
9789db08 30#include <linux/sched.h>
2dcea57a 31#include <linux/mm_types.h>
abf09bed 32#include <linux/page-flags.h>
1da177e4 33#include <asm/bug.h>
b2fa47e6 34#include <asm/page.h>
1da177e4 35
1da177e4
LT		 36extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
37extern void paging_init(void);
2b67fc46 38extern void vmem_map_init(void);
1da177e4
LT		 39
40/*
41 * The S390 doesn't have any external MMU info: the kernel page
42 * tables contain all the necessary information.
43 */
4b3073e1 44#define update_mmu_cache(vma, address, ptep) do { } while (0)
b113da65 45#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
1da177e4
LT		 46
47/*
238ec4ef 48 * ZERO_PAGE is a global shared page that is always zero; used
1da177e4
LT		 49 * for zero-mapped memory areas etc..
50 */
238ec4ef
MS		 51
52extern unsigned long empty_zero_page;
53extern unsigned long zero_page_mask;
54
55#define ZERO_PAGE(vaddr) \
56 (virt_to_page((void *)(empty_zero_page + \
57 (((unsigned long)(vaddr)) &zero_page_mask))))
816422ad 58#define __HAVE_COLOR_ZERO_PAGE
238ec4ef 59
4f2e2903 60/* TODO: s390 cannot support io_remap_pfn_range... */
1da177e4
LT		 61#endif /* !__ASSEMBLY__ */
62
63/*
64 * PMD_SHIFT determines the size of the area a second-level page
65 * table can map
66 * PGDIR_SHIFT determines what a third-level page table entry can map
67 */
f4815ac6 68#ifndef CONFIG_64BIT
146e4b3c
MS		 69# define PMD_SHIFT 20
70# define PUD_SHIFT 20
71# define PGDIR_SHIFT 20
f4815ac6 72#else /* CONFIG_64BIT */
146e4b3c 73# define PMD_SHIFT 20
190a1d72 74# define PUD_SHIFT 31
5a216a20 75# define PGDIR_SHIFT 42
f4815ac6 76#endif /* CONFIG_64BIT */
1da177e4
LT		 77
78#define PMD_SIZE (1UL << PMD_SHIFT)
79#define PMD_MASK (~(PMD_SIZE-1))
190a1d72
MS		 80#define PUD_SIZE (1UL << PUD_SHIFT)
81#define PUD_MASK (~(PUD_SIZE-1))
5a216a20
MS		 82#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
83#define PGDIR_MASK (~(PGDIR_SIZE-1))
1da177e4
LT		 84
85/*
86 * entries per page directory level: the S390 is two-level, so
87 * we don't really have any PMD directory physically.
88 * for S390 segment-table entries are combined to one PGD
89 * that leads to 1024 pte per pgd
90 */
146e4b3c 91#define PTRS_PER_PTE 256
f4815ac6 92#ifndef CONFIG_64BIT
146e4b3c 93#define PTRS_PER_PMD 1
5a216a20 94#define PTRS_PER_PUD 1
f4815ac6 95#else /* CONFIG_64BIT */
146e4b3c 96#define PTRS_PER_PMD 2048
5a216a20 97#define PTRS_PER_PUD 2048
f4815ac6 98#endif /* CONFIG_64BIT */
146e4b3c 99#define PTRS_PER_PGD 2048
1da177e4 100
d455a369
HD		 101#define FIRST_USER_ADDRESS 0
102
1da177e4
LT		 103#define pte_ERROR(e) \
104 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
105#define pmd_ERROR(e) \
106 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
190a1d72
MS		 107#define pud_ERROR(e) \
108 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
1da177e4
LT		 109#define pgd_ERROR(e) \
110 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
111
112#ifndef __ASSEMBLY__
113/*
c972cc60
HC		 114 * The vmalloc and module area will always be on the topmost area of the kernel
115 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
116 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
117 * modules will reside. That makes sure that inter module branches always
118 * happen without trampolines and in addition the placement within a 2GB frame
119 * is branch prediction unit friendly.
8b62bc96 120 */
239a6425 121extern unsigned long VMALLOC_START;
14045ebf
MS		 122extern unsigned long VMALLOC_END;
123extern struct page *vmemmap;
239a6425 124
14045ebf 125#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
5fd9c6e2 126
c972cc60
HC		 127#ifdef CONFIG_64BIT
128extern unsigned long MODULES_VADDR;
129extern unsigned long MODULES_END;
130#define MODULES_VADDR MODULES_VADDR
131#define MODULES_END MODULES_END
132#define MODULES_LEN (1UL << 31)
133#endif
134
1da177e4
LT		 135/*
136 * A 31 bit pagetable entry of S390 has following format:
137 * | PFRA | | OS |
138 * 0 0IP0
139 * 00000000001111111111222222222233
140 * 01234567890123456789012345678901
141 *
142 * I Page-Invalid Bit: Page is not available for address-translation
143 * P Page-Protection Bit: Store access not possible for page
144 *
145 * A 31 bit segmenttable entry of S390 has following format:
146 * | P-table origin | |PTL
147 * 0 IC
148 * 00000000001111111111222222222233
149 * 01234567890123456789012345678901
150 *
151 * I Segment-Invalid Bit: Segment is not available for address-translation
152 * C Common-Segment Bit: Segment is not private (PoP 3-30)
153 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
154 *
155 * The 31 bit segmenttable origin of S390 has following format:
156 *
157 * |S-table origin | | STL |
158 * X **GPS
159 * 00000000001111111111222222222233
160 * 01234567890123456789012345678901
161 *
162 * X Space-Switch event:
163 * G Segment-Invalid Bit: *
164 * P Private-Space Bit: Segment is not private (PoP 3-30)
165 * S Storage-Alteration:
166 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
167 *
168 * A 64 bit pagetable entry of S390 has following format:
6a985c61 169 * | PFRA |0IPC| OS |
1da177e4
LT		 170 * 0000000000111111111122222222223333333333444444444455555555556666
171 * 0123456789012345678901234567890123456789012345678901234567890123
172 *
173 * I Page-Invalid Bit: Page is not available for address-translation
174 * P Page-Protection Bit: Store access not possible for page
6a985c61 175 * C Change-bit override: HW is not required to set change bit
1da177e4
LT		 176 *
177 * A 64 bit segmenttable entry of S390 has following format:
178 * | P-table origin | TT
179 * 0000000000111111111122222222223333333333444444444455555555556666
180 * 0123456789012345678901234567890123456789012345678901234567890123
181 *
182 * I Segment-Invalid Bit: Segment is not available for address-translation
183 * C Common-Segment Bit: Segment is not private (PoP 3-30)
184 * P Page-Protection Bit: Store access not possible for page
185 * TT Type 00
186 *
187 * A 64 bit region table entry of S390 has following format:
188 * | S-table origin | TF TTTL
189 * 0000000000111111111122222222223333333333444444444455555555556666
190 * 0123456789012345678901234567890123456789012345678901234567890123
191 *
192 * I Segment-Invalid Bit: Segment is not available for address-translation
193 * TT Type 01
194 * TF
190a1d72 195 * TL Table length
1da177e4
LT		 196 *
197 * The 64 bit regiontable origin of S390 has following format:
198 * | region table origon | DTTL
199 * 0000000000111111111122222222223333333333444444444455555555556666
200 * 0123456789012345678901234567890123456789012345678901234567890123
201 *
202 * X Space-Switch event:
203 * G Segment-Invalid Bit:
204 * P Private-Space Bit:
205 * S Storage-Alteration:
206 * R Real space
207 * TL Table-Length:
208 *
209 * A storage key has the following format:
210 * | ACC |F|R|C|0|
211 * 0 3 4 5 6 7
212 * ACC: access key
213 * F : fetch protection bit
214 * R : referenced bit
215 * C : changed bit
216 */
217
218/* Hardware bits in the page table entry */
6a985c61 219#define _PAGE_CO 0x100 /* HW Change-bit override */
e5098611 220#define _PAGE_PROTECT 0x200 /* HW read-only bit */
83377484 221#define _PAGE_INVALID 0x400 /* HW invalid bit */
e5098611 222#define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
3610cce8
MS		 223
224/* Software bits in the page table entry */
e5098611
MS		 225#define _PAGE_PRESENT 0x001 /* SW pte present bit */
226#define _PAGE_TYPE 0x002 /* SW pte type bit */
227#define _PAGE_YOUNG 0x004 /* SW pte young bit */
228#define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
0944fe3f
MS		 229#define _PAGE_READ 0x010 /* SW pte read bit */
230#define _PAGE_WRITE 0x020 /* SW pte write bit */
231#define _PAGE_SPECIAL 0x040 /* SW associated with special page */
a08cb629 232#define __HAVE_ARCH_PTE_SPECIAL
1da177e4 233
138c9021 234/* Set of bits not changed in pte_modify */
abf09bed 235#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \
e5098611 236 _PAGE_DIRTY | _PAGE_YOUNG)
53492b1d 237
83377484 238/*
e5098611
MS		 239 * handle_pte_fault uses pte_present, pte_none and pte_file to find out the
240 * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit
241 * is used to distinguish present from not-present ptes. It is changed only
242 * with the page table lock held.
83377484 243 *
e5098611
MS		 244 * The following table gives the different possible bit combinations for
245 * the pte hardware and software bits in the last 12 bits of a pte:
83377484 246 *
0944fe3f
MS		 247 * 842100000000
248 * 000084210000
249 * 000000008421
250 * .IR...wrdytp
251 * empty .10...000000
252 * swap .10...xxxx10
253 * file .11...xxxxx0
254 * prot-none, clean, old .11...000001
255 * prot-none, clean, young .11...000101
256 * prot-none, dirty, old .10...001001
257 * prot-none, dirty, young .10...001101
258 * read-only, clean, old .11...010001
259 * read-only, clean, young .01...010101
260 * read-only, dirty, old .11...011001
261 * read-only, dirty, young .01...011101
262 * read-write, clean, old .11...110001
263 * read-write, clean, young .01...110101
264 * read-write, dirty, old .10...111001
265 * read-write, dirty, young .00...111101
e5098611
MS		 266 *
267 * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001
268 * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400
269 * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600
270 * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402
83377484
MS		 271 */
272
f4815ac6 273#ifndef CONFIG_64BIT
1da177e4 274
3610cce8
MS		 275/* Bits in the segment table address-space-control-element */
276#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
277#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
278#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
279#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
280#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
1da177e4 281
3610cce8 282/* Bits in the segment table entry */
0944fe3f 283#define _SEGMENT_ENTRY_BITS 0x7fffffffUL /* Valid segment table bits */
3610cce8 284#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
e5098611
MS		 285#define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
286#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
3610cce8
MS		 287#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
288#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
0944fe3f 289#define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_PROTECT
1da177e4 290
3610cce8 291#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
e5098611 292#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
1da177e4 293
0944fe3f
MS		 294/*
295 * Segment table entry encoding (I = invalid, R = read-only bit):
296 * ..R...I.....
297 * prot-none ..1...1.....
298 * read-only ..1...0.....
299 * read-write ..0...0.....
300 * empty ..0...1.....
301 */
302
6c61cfe9 303/* Page status table bits for virtualization */
0d0dafc1
MS		 304#define PGSTE_ACC_BITS 0xf0000000UL
305#define PGSTE_FP_BIT 0x08000000UL
306#define PGSTE_PCL_BIT 0x00800000UL
307#define PGSTE_HR_BIT 0x00400000UL
308#define PGSTE_HC_BIT 0x00200000UL
309#define PGSTE_GR_BIT 0x00040000UL
310#define PGSTE_GC_BIT 0x00020000UL
0944fe3f 311#define PGSTE_IN_BIT 0x00008000UL /* IPTE notify bit */
6c61cfe9 312
f4815ac6 313#else /* CONFIG_64BIT */
1da177e4 314
3610cce8
MS		 315/* Bits in the segment/region table address-space-control-element */
316#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
317#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
318#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
319#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
320#define _ASCE_REAL_SPACE 0x20 /* real space control */
321#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
322#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
323#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
324#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
325#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
326#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
327
328/* Bits in the region table entry */
329#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
e5098611
MS		 330#define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
331#define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
3610cce8
MS		 332#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
333#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
334#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
335#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
336#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
337
338#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
e5098611 339#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
3610cce8 340#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
e5098611 341#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
3610cce8 342#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
e5098611 343#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
3610cce8 344
18da2369 345#define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
1819ed1f
HC		 346#define _REGION3_ENTRY_RO 0x200 /* page protection bit */
347#define _REGION3_ENTRY_CO 0x100 /* change-recording override */
18da2369 348
1da177e4 349/* Bits in the segment table entry */
0944fe3f
MS		 350#define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL
351#define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff1ff33UL
ea81531d 352#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
3610cce8 353#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
e5098611
MS		 354#define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
355#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
1da177e4 356
3610cce8 357#define _SEGMENT_ENTRY (0)
e5098611 358#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
3610cce8 359
53492b1d
GS		 360#define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
361#define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
e5098611 362#define _SEGMENT_ENTRY_SPLIT 0x001 /* THP splitting bit */
0944fe3f
MS		 363#define _SEGMENT_ENTRY_YOUNG 0x002 /* SW segment young bit */
364#define _SEGMENT_ENTRY_NONE _SEGMENT_ENTRY_YOUNG
365
366/*
367 * Segment table entry encoding (R = read-only, I = invalid, y = young bit):
368 * ..R...I...y.
369 * prot-none, old ..0...1...1.
370 * prot-none, young ..1...1...1.
371 * read-only, old ..1...1...0.
372 * read-only, young ..1...0...1.
373 * read-write, old ..0...1...0.
374 * read-write, young ..0...0...1.
375 * The segment table origin is used to distinguish empty (origin==0) from
376 * read-write, old segment table entries (origin!=0)
377 */
e5098611 378
75077afb 379#define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */
53492b1d 380
1ae1c1d0
GS		 381/* Set of bits not changed in pmd_modify */
382#define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
383 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
384
6c61cfe9 385/* Page status table bits for virtualization */
0d0dafc1
MS		 386#define PGSTE_ACC_BITS 0xf000000000000000UL
387#define PGSTE_FP_BIT 0x0800000000000000UL
388#define PGSTE_PCL_BIT 0x0080000000000000UL
389#define PGSTE_HR_BIT 0x0040000000000000UL
390#define PGSTE_HC_BIT 0x0020000000000000UL
391#define PGSTE_GR_BIT 0x0004000000000000UL
392#define PGSTE_GC_BIT 0x0002000000000000UL
0944fe3f 393#define PGSTE_IN_BIT 0x0000800000000000UL /* IPTE notify bit */
6c61cfe9 394
f4815ac6 395#endif /* CONFIG_64BIT */
1da177e4
LT		 396
397/*
3610cce8
MS		 398 * A user page table pointer has the space-switch-event bit, the
399 * private-space-control bit and the storage-alteration-event-control
400 * bit set. A kernel page table pointer doesn't need them.
1da177e4 401 */
3610cce8
MS		 402#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
403 _ASCE_ALT_EVENT)
1da177e4 404
1da177e4 405/*
9282ed92 406 * Page protection definitions.
1da177e4 407 */
e5098611 408#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID)
0944fe3f
MS		 409#define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \
410 _PAGE_INVALID | _PAGE_PROTECT)
411#define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
412 _PAGE_INVALID | _PAGE_PROTECT)
413
414#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
415 _PAGE_YOUNG | _PAGE_DIRTY)
416#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
417 _PAGE_YOUNG | _PAGE_DIRTY)
418#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
419 _PAGE_PROTECT)
1da177e4
LT		 420
421/*
043d0708
MS		 422 * On s390 the page table entry has an invalid bit and a read-only bit.
423 * Read permission implies execute permission and write permission
424 * implies read permission.
1da177e4
LT		 425 */
426 /*xwr*/
9282ed92 427#define __P000 PAGE_NONE
e5098611
MS		 428#define __P001 PAGE_READ
429#define __P010 PAGE_READ
430#define __P011 PAGE_READ
431#define __P100 PAGE_READ
432#define __P101 PAGE_READ
433#define __P110 PAGE_READ
434#define __P111 PAGE_READ
9282ed92
GS		 435
436#define __S000 PAGE_NONE
e5098611
MS		 437#define __S001 PAGE_READ
438#define __S010 PAGE_WRITE
439#define __S011 PAGE_WRITE
440#define __S100 PAGE_READ
441#define __S101 PAGE_READ
442#define __S110 PAGE_WRITE
443#define __S111 PAGE_WRITE
1da177e4 444
106c992a
GS		 445/*
446 * Segment entry (large page) protection definitions.
447 */
e5098611 448#define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
0944fe3f
MS		 449 _SEGMENT_ENTRY_NONE)
450#define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_INVALID | \
e5098611 451 _SEGMENT_ENTRY_PROTECT)
0944fe3f 452#define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_INVALID)
106c992a 453
b2fa47e6
MS		 454static inline int mm_has_pgste(struct mm_struct *mm)
455{
456#ifdef CONFIG_PGSTE
457 if (unlikely(mm->context.has_pgste))
458 return 1;
459#endif
460 return 0;
461}
1da177e4
LT		 462/*
463 * pgd/pmd/pte query functions
464 */
f4815ac6 465#ifndef CONFIG_64BIT
1da177e4 466
4448aaf0
AB		 467static inline int pgd_present(pgd_t pgd) { return 1; }
468static inline int pgd_none(pgd_t pgd) { return 0; }
469static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 470
190a1d72
MS		 471static inline int pud_present(pud_t pud) { return 1; }
472static inline int pud_none(pud_t pud) { return 0; }
18da2369 473static inline int pud_large(pud_t pud) { return 0; }
190a1d72
MS		 474static inline int pud_bad(pud_t pud) { return 0; }
475
f4815ac6 476#else /* CONFIG_64BIT */
1da177e4 477
5a216a20
MS		 478static inline int pgd_present(pgd_t pgd)
479{
6252d702
MS		 480 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
481 return 1;
5a216a20
MS		 482 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
483}
484
485static inline int pgd_none(pgd_t pgd)
486{
6252d702
MS		 487 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
488 return 0;
e5098611 489 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
5a216a20
MS		 490}
491
492static inline int pgd_bad(pgd_t pgd)
493{
6252d702
MS		 494 /*
495 * With dynamic page table levels the pgd can be a region table
496 * entry or a segment table entry. Check for the bit that are
497 * invalid for either table entry.
498 */
5a216a20 499 unsigned long mask =
e5098611 500 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
5a216a20
MS		 501 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
502 return (pgd_val(pgd) & mask) != 0;
503}
190a1d72
MS		 504
505static inline int pud_present(pud_t pud)
1da177e4 506{
6252d702
MS		 507 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
508 return 1;
0d017923 509 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 510}
511
190a1d72 512static inline int pud_none(pud_t pud)
1da177e4 513{
6252d702
MS		 514 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
515 return 0;
e5098611 516 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL;
1da177e4
LT		 517}
518
18da2369
HC		 519static inline int pud_large(pud_t pud)
520{
521 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
522 return 0;
523 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
524}
525
190a1d72 526static inline int pud_bad(pud_t pud)
1da177e4 527{
6252d702
MS		 528 /*
529 * With dynamic page table levels the pud can be a region table
530 * entry or a segment table entry. Check for the bit that are
531 * invalid for either table entry.
532 */
5a216a20 533 unsigned long mask =
e5098611 534 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
5a216a20
MS		 535 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
536 return (pud_val(pud) & mask) != 0;
1da177e4
LT		 537}
538
f4815ac6 539#endif /* CONFIG_64BIT */
3610cce8 540
4448aaf0 541static inline int pmd_present(pmd_t pmd)
1da177e4 542{
e5098611 543 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 544}
545
4448aaf0 546static inline int pmd_none(pmd_t pmd)
1da177e4 547{
e5098611 548 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 549}
550
378b1e7a
HC		 551static inline int pmd_large(pmd_t pmd)
552{
553#ifdef CONFIG_64BIT
e5098611 554 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
378b1e7a
HC		 555#else
556 return 0;
557#endif
558}
559
0944fe3f
MS		 560static inline int pmd_prot_none(pmd_t pmd)
561{
562 return (pmd_val(pmd) & _SEGMENT_ENTRY_INVALID) &&
563 (pmd_val(pmd) & _SEGMENT_ENTRY_NONE);
564}
565
4448aaf0 566static inline int pmd_bad(pmd_t pmd)
1da177e4 567{
0944fe3f
MS		 568#ifdef CONFIG_64BIT
569 if (pmd_large(pmd))
570 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0;
571#endif
572 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
1da177e4
LT		 573}
574
75077afb
GS		 575#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
576extern void pmdp_splitting_flush(struct vm_area_struct *vma,
577 unsigned long addr, pmd_t *pmdp);
578
1ae1c1d0
GS		 579#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
580extern int pmdp_set_access_flags(struct vm_area_struct *vma,
581 unsigned long address, pmd_t *pmdp,
582 pmd_t entry, int dirty);
583
584#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
585extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
586 unsigned long address, pmd_t *pmdp);
587
588#define __HAVE_ARCH_PMD_WRITE
589static inline int pmd_write(pmd_t pmd)
590{
0944fe3f
MS		 591 if (pmd_prot_none(pmd))
592 return 0;
e5098611 593 return (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) == 0;
1ae1c1d0
GS		 594}
595
596static inline int pmd_young(pmd_t pmd)
597{
0944fe3f
MS		 598 int young = 0;
599#ifdef CONFIG_64BIT
600 if (pmd_prot_none(pmd))
601 young = (pmd_val(pmd) & _SEGMENT_ENTRY_PROTECT) != 0;
602 else
603 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
604#endif
605 return young;
1ae1c1d0
GS		 606}
607
e5098611 608static inline int pte_present(pte_t pte)
1da177e4 609{
e5098611
MS		 610 /* Bit pattern: (pte & 0x001) == 0x001 */
611 return (pte_val(pte) & _PAGE_PRESENT) != 0;
1da177e4
LT		 612}
613
e5098611 614static inline int pte_none(pte_t pte)
1da177e4 615{
e5098611
MS		 616 /* Bit pattern: pte == 0x400 */
617 return pte_val(pte) == _PAGE_INVALID;
1da177e4
LT		 618}
619
4448aaf0 620static inline int pte_file(pte_t pte)
1da177e4 621{
e5098611
MS		 622 /* Bit pattern: (pte & 0x601) == 0x600 */
623 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT))
624 == (_PAGE_INVALID | _PAGE_PROTECT);
1da177e4
LT		 625}
626
7e675137
NP		 627static inline int pte_special(pte_t pte)
628{
a08cb629 629 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 630}
631
ba8a9229 632#define __HAVE_ARCH_PTE_SAME
b2fa47e6
MS		 633static inline int pte_same(pte_t a, pte_t b)
634{
635 return pte_val(a) == pte_val(b);
636}
1da177e4 637
b2fa47e6 638static inline pgste_t pgste_get_lock(pte_t *ptep)
5b7baf05 639{
b2fa47e6 640 unsigned long new = 0;
5b7baf05 641#ifdef CONFIG_PGSTE
b2fa47e6
MS		 642 unsigned long old;
643
5b7baf05 644 preempt_disable();
b2fa47e6
MS		 645 asm(
646 " lg %0,%2\n"
647 "0: lgr %1,%0\n"
0d0dafc1
MS		 648 " nihh %0,0xff7f\n" /* clear PCL bit in old */
649 " oihh %1,0x0080\n" /* set PCL bit in new */
b2fa47e6
MS		 650 " csg %0,%1,%2\n"
651 " jl 0b\n"
652 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
a8f6e7f7 653 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
5b7baf05 654#endif
b2fa47e6 655 return __pgste(new);
5b7baf05
CB		 656}
657
b2fa47e6 658static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 659{
660#ifdef CONFIG_PGSTE
b2fa47e6 661 asm(
0d0dafc1 662 " nihh %1,0xff7f\n" /* clear PCL bit */
b2fa47e6
MS		 663 " stg %1,%0\n"
664 : "=Q" (ptep[PTRS_PER_PTE])
a8f6e7f7
CB		 665 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
666 : "cc", "memory");
5b7baf05
CB		 667 preempt_enable();
668#endif
669}
670
d56c893d
MS		 671static inline pgste_t pgste_get(pte_t *ptep)
672{
673 unsigned long pgste = 0;
674#ifdef CONFIG_PGSTE
675 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE);
676#endif
677 return __pgste(pgste);
678}
679
3a82603b
CB		 680static inline void pgste_set(pte_t *ptep, pgste_t pgste)
681{
682#ifdef CONFIG_PGSTE
683 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
684#endif
685}
686
b2fa47e6 687static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 688{
689#ifdef CONFIG_PGSTE
0944fe3f 690 unsigned long address, bits, skey;
b2fa47e6 691
b56433cb 692 if (pte_val(*ptep) & _PAGE_INVALID)
09b53883 693 return pgste;
a43a9d93 694 address = pte_val(*ptep) & PAGE_MASK;
0944fe3f 695 skey = (unsigned long) page_get_storage_key(address);
b2fa47e6 696 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
0944fe3f
MS		 697 if (!(pgste_val(pgste) & PGSTE_HC_BIT) && (bits & _PAGE_CHANGED)) {
698 /* Transfer dirty + referenced bit to host bits in pgste */
699 pgste_val(pgste) |= bits << 52;
abf09bed 700 page_set_storage_key(address, skey ^ bits, 0);
0944fe3f
MS		 701 } else if (!(pgste_val(pgste) & PGSTE_HR_BIT) &&
702 (bits & _PAGE_REFERENCED)) {
703 /* Transfer referenced bit to host bit in pgste */
704 pgste_val(pgste) |= PGSTE_HR_BIT;
7c81878b 705 page_reset_referenced(address);
0944fe3f 706 }
b2fa47e6 707 /* Transfer page changed & referenced bit to guest bits in pgste */
0d0dafc1 708 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */
b2fa47e6 709 /* Copy page access key and fetch protection bit to pgste */
0944fe3f
MS		 710 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
711 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
b2fa47e6
MS		 712#endif
713 return pgste;
714
715}
716
717static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
718{
719#ifdef CONFIG_PGSTE
b56433cb 720 if (pte_val(*ptep) & _PAGE_INVALID)
09b53883 721 return pgste;
abf09bed 722 /* Get referenced bit from storage key */
0944fe3f
MS		 723 if (page_reset_referenced(pte_val(*ptep) & PAGE_MASK))
724 pgste_val(pgste) |= PGSTE_HR_BIT | PGSTE_GR_BIT;
b2fa47e6
MS		 725#endif
726 return pgste;
b2fa47e6
MS		 727}
728
abf09bed 729static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
b2fa47e6
MS		 730{
731#ifdef CONFIG_PGSTE
a43a9d93 732 unsigned long address;
338679f7 733 unsigned long nkey;
b2fa47e6 734
b56433cb 735 if (pte_val(entry) & _PAGE_INVALID)
09b53883 736 return;
338679f7 737 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
09b53883 738 address = pte_val(entry) & PAGE_MASK;
338679f7
CB		 739 /*
740 * Set page access key and fetch protection bit from pgste.
741 * The guest C/R information is still in the PGSTE, set real
742 * key C/R to 0.
743 */
fe489bf4 744 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
338679f7 745 page_set_storage_key(address, nkey, 0);
5b7baf05
CB		 746#endif
747}
748
abf09bed
MS		 749static inline void pgste_set_pte(pte_t *ptep, pte_t entry)
750{
af0ebc40
MS		 751 if (!MACHINE_HAS_ESOP &&
752 (pte_val(entry) & _PAGE_PRESENT) &&
753 (pte_val(entry) & _PAGE_WRITE)) {
abf09bed
MS		 754 /*
755 * Without enhanced suppression-on-protection force
756 * the dirty bit on for all writable ptes.
757 */
e5098611
MS		 758 pte_val(entry) |= _PAGE_DIRTY;
759 pte_val(entry) &= ~_PAGE_PROTECT;
abf09bed
MS		 760 }
761 *ptep = entry;
762}
763
e5992f2e
MS		 764/**
765 * struct gmap_struct - guest address space
766 * @mm: pointer to the parent mm_struct
767 * @table: pointer to the page directory
480e5926 768 * @asce: address space control element for gmap page table
e5992f2e
MS		 769 * @crst_list: list of all crst tables used in the guest address space
770 */
771struct gmap {
772 struct list_head list;
773 struct mm_struct *mm;
774 unsigned long *table;
480e5926 775 unsigned long asce;
2c70fe44 776 void *private;
e5992f2e
MS		 777 struct list_head crst_list;
778};
779
780/**
781 * struct gmap_rmap - reverse mapping for segment table entries
d3383632 782 * @gmap: pointer to the gmap_struct
e5992f2e 783 * @entry: pointer to a segment table entry
d3383632 784 * @vmaddr: virtual address in the guest address space
e5992f2e
MS		 785 */
786struct gmap_rmap {
787 struct list_head list;
d3383632 788 struct gmap *gmap;
e5992f2e 789 unsigned long *entry;
d3383632 790 unsigned long vmaddr;
e5992f2e
MS		 791};
792
793/**
794 * struct gmap_pgtable - gmap information attached to a page table
795 * @vmaddr: address of the 1MB segment in the process virtual memory
d3383632 796 * @mapper: list of segment table entries mapping a page table
e5992f2e
MS		 797 */
798struct gmap_pgtable {
799 unsigned long vmaddr;
800 struct list_head mapper;
801};
802
d3383632
MS		 803/**
804 * struct gmap_notifier - notify function block for page invalidation
805 * @notifier_call: address of callback function
806 */
807struct gmap_notifier {
808 struct list_head list;
809 void (*notifier_call)(struct gmap *gmap, unsigned long address);
810};
811
e5992f2e
MS		 812struct gmap *gmap_alloc(struct mm_struct *mm);
813void gmap_free(struct gmap *gmap);
814void gmap_enable(struct gmap *gmap);
815void gmap_disable(struct gmap *gmap);
816int gmap_map_segment(struct gmap *gmap, unsigned long from,
d3383632 817 unsigned long to, unsigned long len);
e5992f2e 818int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
c5034945
HC		 819unsigned long __gmap_translate(unsigned long address, struct gmap *);
820unsigned long gmap_translate(unsigned long address, struct gmap *);
499069e1 821unsigned long __gmap_fault(unsigned long address, struct gmap *);
e5992f2e 822unsigned long gmap_fault(unsigned long address, struct gmap *);
388186bc 823void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
e5992f2e 824
d3383632
MS		 825void gmap_register_ipte_notifier(struct gmap_notifier *);
826void gmap_unregister_ipte_notifier(struct gmap_notifier *);
827int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
828void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);
829
830static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
831 unsigned long addr,
832 pte_t *ptep, pgste_t pgste)
833{
834#ifdef CONFIG_PGSTE
0d0dafc1
MS		 835 if (pgste_val(pgste) & PGSTE_IN_BIT) {
836 pgste_val(pgste) &= ~PGSTE_IN_BIT;
d3383632
MS		 837 gmap_do_ipte_notify(mm, addr, ptep);
838 }
839#endif
840 return pgste;
841}
842
b2fa47e6
MS		 843/*
844 * Certain architectures need to do special things when PTEs
845 * within a page table are directly modified. Thus, the following
846 * hook is made available.
847 */
848static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
849 pte_t *ptep, pte_t entry)
850{
851 pgste_t pgste;
852
853 if (mm_has_pgste(mm)) {
854 pgste = pgste_get_lock(ptep);
abf09bed
MS		 855 pgste_set_key(ptep, pgste, entry);
856 pgste_set_pte(ptep, entry);
b2fa47e6 857 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 858 } else {
859 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1)
860 pte_val(entry) |= _PAGE_CO;
b2fa47e6 861 *ptep = entry;
abf09bed 862 }
b2fa47e6
MS		 863}
864
1da177e4
LT		 865/*
866 * query functions pte_write/pte_dirty/pte_young only work if
867 * pte_present() is true. Undefined behaviour if not..
868 */
4448aaf0 869static inline int pte_write(pte_t pte)
1da177e4 870{
e5098611 871 return (pte_val(pte) & _PAGE_WRITE) != 0;
1da177e4
LT		 872}
873
4448aaf0 874static inline int pte_dirty(pte_t pte)
1da177e4 875{
e5098611 876 return (pte_val(pte) & _PAGE_DIRTY) != 0;
1da177e4
LT		 877}
878
4448aaf0 879static inline int pte_young(pte_t pte)
1da177e4 880{
0944fe3f 881 return (pte_val(pte) & _PAGE_YOUNG) != 0;
1da177e4
LT		 882}
883
1da177e4
LT		 884/*
885 * pgd/pmd/pte modification functions
886 */
887
b2fa47e6 888static inline void pgd_clear(pgd_t *pgd)
5a216a20 889{
f4815ac6 890#ifdef CONFIG_64BIT
6252d702
MS		 891 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
892 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
b2fa47e6 893#endif
5a216a20
MS		 894}
895
b2fa47e6 896static inline void pud_clear(pud_t *pud)
1da177e4 897{
f4815ac6 898#ifdef CONFIG_64BIT
6252d702
MS		 899 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
900 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
b2fa47e6 901#endif
1da177e4
LT		 902}
903
b2fa47e6 904static inline void pmd_clear(pmd_t *pmdp)
1da177e4 905{
e5098611 906 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 907}
908
4448aaf0 909static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 910{
e5098611 911 pte_val(*ptep) = _PAGE_INVALID;
1da177e4
LT		 912}
913
914/*
915 * The following pte modification functions only work if
916 * pte_present() is true. Undefined behaviour if not..
917 */
4448aaf0 918static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 919{
138c9021 920 pte_val(pte) &= _PAGE_CHG_MASK;
1da177e4 921 pte_val(pte) |= pgprot_val(newprot);
0944fe3f
MS		 922 /*
923 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the
924 * invalid bit set, clear it again for readable, young pages
925 */
926 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
927 pte_val(pte) &= ~_PAGE_INVALID;
928 /*
929 * newprot for PAGE_READ and PAGE_WRITE has the page protection
930 * bit set, clear it again for writable, dirty pages
931 */
e5098611
MS		 932 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
933 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 934 return pte;
935}
936
4448aaf0 937static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 938{
e5098611
MS		 939 pte_val(pte) &= ~_PAGE_WRITE;
940 pte_val(pte) |= _PAGE_PROTECT;
1da177e4
LT		 941 return pte;
942}
943
4448aaf0 944static inline pte_t pte_mkwrite(pte_t pte)
1da177e4 945{
e5098611
MS		 946 pte_val(pte) |= _PAGE_WRITE;
947 if (pte_val(pte) & _PAGE_DIRTY)
948 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 949 return pte;
950}
951
4448aaf0 952static inline pte_t pte_mkclean(pte_t pte)
1da177e4 953{
e5098611
MS		 954 pte_val(pte) &= ~_PAGE_DIRTY;
955 pte_val(pte) |= _PAGE_PROTECT;
1da177e4
LT		 956 return pte;
957}
958
4448aaf0 959static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 960{
e5098611
MS		 961 pte_val(pte) |= _PAGE_DIRTY;
962 if (pte_val(pte) & _PAGE_WRITE)
963 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 964 return pte;
965}
966
4448aaf0 967static inline pte_t pte_mkold(pte_t pte)
1da177e4 968{
e5098611 969 pte_val(pte) &= ~_PAGE_YOUNG;
0944fe3f 970 pte_val(pte) |= _PAGE_INVALID;
1da177e4
LT		 971 return pte;
972}
973
4448aaf0 974static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 975{
0944fe3f
MS		 976 pte_val(pte) |= _PAGE_YOUNG;
977 if (pte_val(pte) & _PAGE_READ)
978 pte_val(pte) &= ~_PAGE_INVALID;
1da177e4
LT		 979 return pte;
980}
981
7e675137
NP		 982static inline pte_t pte_mkspecial(pte_t pte)
983{
a08cb629 984 pte_val(pte) |= _PAGE_SPECIAL;
7e675137
NP		 985 return pte;
986}
987
84afdcee
HC		 988#ifdef CONFIG_HUGETLB_PAGE
989static inline pte_t pte_mkhuge(pte_t pte)
990{
e5098611 991 pte_val(pte) |= _PAGE_LARGE;
84afdcee
HC		 992 return pte;
993}
994#endif
995
15e86b0c 996/*
b2fa47e6 997 * Get (and clear) the user dirty bit for a pte.
15e86b0c 998 */
b2fa47e6
MS		 999static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
1000 pte_t *ptep)
15e86b0c 1001{
b2fa47e6
MS		 1002 pgste_t pgste;
1003 int dirty = 0;
1004
1005 if (mm_has_pgste(mm)) {
1006 pgste = pgste_get_lock(ptep);
1007 pgste = pgste_update_all(ptep, pgste);
0944fe3f
MS		 1008 dirty = !!(pgste_val(pgste) & PGSTE_HC_BIT);
1009 pgste_val(pgste) &= ~PGSTE_HC_BIT;
b2fa47e6
MS		 1010 pgste_set_unlock(ptep, pgste);
1011 return dirty;
15e86b0c 1012 }
15e86b0c
FF		 1013 return dirty;
1014}
b2fa47e6
MS		 1015
1016/*
1017 * Get (and clear) the user referenced bit for a pte.
1018 */
1019static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
1020 pte_t *ptep)
1021{
1022 pgste_t pgste;
1023 int young = 0;
1024
1025 if (mm_has_pgste(mm)) {
1026 pgste = pgste_get_lock(ptep);
1027 pgste = pgste_update_young(ptep, pgste);
0944fe3f
MS		 1028 young = !!(pgste_val(pgste) & PGSTE_HR_BIT);
1029 pgste_val(pgste) &= ~PGSTE_HR_BIT;
b2fa47e6
MS		 1030 pgste_set_unlock(ptep, pgste);
1031 }
1032 return young;
1033}
15e86b0c 1034
9282ed92 1035static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 1036{
9282ed92 1037 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
f4815ac6 1038#ifndef CONFIG_64BIT
146e4b3c 1039 /* pto must point to the start of the segment table */
1da177e4 1040 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
9282ed92
GS		 1041#else
1042 /* ipte in zarch mode can do the math */
1043 pte_t *pto = ptep;
1044#endif
94c12cc7
MS		 1045 asm volatile(
1046 " ipte %2,%3"
1047 : "=m" (*ptep) : "m" (*ptep),
1048 "a" (pto), "a" (address));
1da177e4 1049 }
9282ed92
GS		 1050}
1051
5c474a1e
MS		 1052static inline void ptep_flush_lazy(struct mm_struct *mm,
1053 unsigned long address, pte_t *ptep)
1054{
1055 int active = (mm == current->active_mm) ? 1 : 0;
1056
1057 if (atomic_read(&mm->context.attach_count) > active)
1058 __ptep_ipte(address, ptep);
1059 else
1060 mm->context.flush_mm = 1;
1061}
1062
0944fe3f
MS		 1063#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1064static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1065 unsigned long addr, pte_t *ptep)
1066{
1067 pgste_t pgste;
1068 pte_t pte;
1069 int young;
1070
1071 if (mm_has_pgste(vma->vm_mm)) {
1072 pgste = pgste_get_lock(ptep);
1073 pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste);
1074 }
1075
1076 pte = *ptep;
1077 __ptep_ipte(addr, ptep);
1078 young = pte_young(pte);
1079 pte = pte_mkold(pte);
1080
1081 if (mm_has_pgste(vma->vm_mm)) {
1082 pgste_set_pte(ptep, pte);
1083 pgste_set_unlock(ptep, pgste);
1084 } else
1085 *ptep = pte;
1086
1087 return young;
1088}
1089
1090#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1091static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1092 unsigned long address, pte_t *ptep)
1093{
1094 return ptep_test_and_clear_young(vma, address, ptep);
1095}
1096
ba8a9229
MS		 1097/*
1098 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1099 * both clear the TLB for the unmapped pte. The reason is that
1100 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1101 * to modify an active pte. The sequence is
1102 * 1) ptep_get_and_clear
1103 * 2) set_pte_at
1104 * 3) flush_tlb_range
1105 * On s390 the tlb needs to get flushed with the modification of the pte
1106 * if the pte is active. The only way how this can be implemented is to
1107 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1108 * is a nop.
1109 */
1110#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
b2fa47e6
MS		 1111static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1112 unsigned long address, pte_t *ptep)
1113{
1114 pgste_t pgste;
1115 pte_t pte;
1116
d3383632 1117 if (mm_has_pgste(mm)) {
b2fa47e6 1118 pgste = pgste_get_lock(ptep);
d3383632
MS		 1119 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1120 }
b2fa47e6
MS		 1121
1122 pte = *ptep;
5c474a1e 1123 ptep_flush_lazy(mm, address, ptep);
e5098611 1124 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6
MS		 1125
1126 if (mm_has_pgste(mm)) {
1127 pgste = pgste_update_all(&pte, pgste);
1128 pgste_set_unlock(ptep, pgste);
1129 }
1130 return pte;
1131}
1132
1133#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1134static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1135 unsigned long address,
1136 pte_t *ptep)
1137{
d3383632 1138 pgste_t pgste;
b2fa47e6
MS		 1139 pte_t pte;
1140
d3383632
MS		 1141 if (mm_has_pgste(mm)) {
1142 pgste = pgste_get_lock(ptep);
1143 pgste_ipte_notify(mm, address, ptep, pgste);
1144 }
b2fa47e6
MS		 1145
1146 pte = *ptep;
5c474a1e 1147 ptep_flush_lazy(mm, address, ptep);
0196c642 1148 pte_val(*ptep) |= _PAGE_INVALID;
b56433cb 1149
3a82603b 1150 if (mm_has_pgste(mm)) {
b56433cb 1151 pgste = pgste_update_all(&pte, pgste);
3a82603b
CB		 1152 pgste_set(ptep, pgste);
1153 }
b2fa47e6
MS		 1154 return pte;
1155}
1156
1157static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1158 unsigned long address,
1159 pte_t *ptep, pte_t pte)
1160{
b56433cb
CB		 1161 pgste_t pgste;
1162
abf09bed 1163 if (mm_has_pgste(mm)) {
d56c893d 1164 pgste = pgste_get(ptep);
b56433cb 1165 pgste_set_key(ptep, pgste, pte);
abf09bed 1166 pgste_set_pte(ptep, pte);
b56433cb 1167 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1168 } else
1169 *ptep = pte;
b2fa47e6 1170}
ba8a9229
MS		 1171
1172#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22
MS		 1173static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1174 unsigned long address, pte_t *ptep)
1175{
b2fa47e6
MS		 1176 pgste_t pgste;
1177 pte_t pte;
1178
d3383632 1179 if (mm_has_pgste(vma->vm_mm)) {
b2fa47e6 1180 pgste = pgste_get_lock(ptep);
d3383632
MS		 1181 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1182 }
b2fa47e6
MS		 1183
1184 pte = *ptep;
1185 __ptep_ipte(address, ptep);
e5098611 1186 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6
MS		 1187
1188 if (mm_has_pgste(vma->vm_mm)) {
1189 pgste = pgste_update_all(&pte, pgste);
1190 pgste_set_unlock(ptep, pgste);
1191 }
1da177e4
LT		 1192 return pte;
1193}
1194
ba8a9229
MS		 1195/*
1196 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1197 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1198 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1199 * cannot be accessed while the batched unmap is running. In this case
1200 * full==1 and a simple pte_clear is enough. See tlb.h.
1201 */
1202#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1203static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
b2fa47e6 1204 unsigned long address,
ba8a9229 1205 pte_t *ptep, int full)
1da177e4 1206{
b2fa47e6
MS		 1207 pgste_t pgste;
1208 pte_t pte;
1209
a055f66a 1210 if (!full && mm_has_pgste(mm)) {
b2fa47e6 1211 pgste = pgste_get_lock(ptep);
a055f66a 1212 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
d3383632 1213 }
ba8a9229 1214
b2fa47e6
MS		 1215 pte = *ptep;
1216 if (!full)
5c474a1e 1217 ptep_flush_lazy(mm, address, ptep);
e5098611 1218 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6 1219
a055f66a 1220 if (!full && mm_has_pgste(mm)) {
b2fa47e6
MS		 1221 pgste = pgste_update_all(&pte, pgste);
1222 pgste_set_unlock(ptep, pgste);
1223 }
ba8a9229 1224 return pte;
1da177e4
LT		 1225}
1226
ba8a9229 1227#define __HAVE_ARCH_PTEP_SET_WRPROTECT
b2fa47e6
MS		 1228static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1229 unsigned long address, pte_t *ptep)
1230{
1231 pgste_t pgste;
1232 pte_t pte = *ptep;
1233
1234 if (pte_write(pte)) {
d3383632 1235 if (mm_has_pgste(mm)) {
b2fa47e6 1236 pgste = pgste_get_lock(ptep);
d3383632
MS		 1237 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1238 }
b2fa47e6 1239
5c474a1e 1240 ptep_flush_lazy(mm, address, ptep);
abf09bed 1241 pte = pte_wrprotect(pte);
b2fa47e6 1242
abf09bed
MS		 1243 if (mm_has_pgste(mm)) {
1244 pgste_set_pte(ptep, pte);
b2fa47e6 1245 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1246 } else
1247 *ptep = pte;
b2fa47e6
MS		 1248 }
1249 return pte;
1250}
ba8a9229
MS		 1251
1252#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
b2fa47e6
MS		 1253static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1254 unsigned long address, pte_t *ptep,
1255 pte_t entry, int dirty)
1256{
1257 pgste_t pgste;
1258
1259 if (pte_same(*ptep, entry))
1260 return 0;
d3383632 1261 if (mm_has_pgste(vma->vm_mm)) {
b2fa47e6 1262 pgste = pgste_get_lock(ptep);
d3383632
MS		 1263 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1264 }
b2fa47e6
MS		 1265
1266 __ptep_ipte(address, ptep);
b2fa47e6 1267
abf09bed
MS		 1268 if (mm_has_pgste(vma->vm_mm)) {
1269 pgste_set_pte(ptep, entry);
b2fa47e6 1270 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1271 } else
1272 *ptep = entry;
b2fa47e6
MS		 1273 return 1;
1274}
1da177e4 1275
1da177e4
LT		 1276/*
1277 * Conversion functions: convert a page and protection to a page entry,
1278 * and a page entry and page directory to the page they refer to.
1279 */
1280static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1281{
1282 pte_t __pte;
1283 pte_val(__pte) = physpage + pgprot_val(pgprot);
0944fe3f 1284 return pte_mkyoung(__pte);
1da177e4
LT		 1285}
1286
2dcea57a
HC		 1287static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1288{
0b2b6e1d 1289 unsigned long physpage = page_to_phys(page);
abf09bed 1290 pte_t __pte = mk_pte_phys(physpage, pgprot);
1da177e4 1291
e5098611
MS		 1292 if (pte_write(__pte) && PageDirty(page))
1293 __pte = pte_mkdirty(__pte);
abf09bed 1294 return __pte;
2dcea57a
HC		 1295}
1296
190a1d72
MS		 1297#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1298#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1299#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1300#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1da177e4 1301
190a1d72
MS		 1302#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1303#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4 1304
f4815ac6 1305#ifndef CONFIG_64BIT
1da177e4 1306
190a1d72
MS		 1307#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1308#define pud_deref(pmd) ({ BUG(); 0UL; })
1309#define pgd_deref(pmd) ({ BUG(); 0UL; })
46a82b2d 1310
190a1d72
MS		 1311#define pud_offset(pgd, address) ((pud_t *) pgd)
1312#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1da177e4 1313
f4815ac6 1314#else /* CONFIG_64BIT */
1da177e4 1315
190a1d72
MS		 1316#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1317#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
5a216a20 1318#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1da177e4 1319
5a216a20
MS		 1320static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1321{
6252d702
MS		 1322 pud_t *pud = (pud_t *) pgd;
1323 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1324 pud = (pud_t *) pgd_deref(*pgd);
5a216a20
MS		 1325 return pud + pud_index(address);
1326}
1da177e4 1327
190a1d72 1328static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1da177e4 1329{
6252d702
MS		 1330 pmd_t *pmd = (pmd_t *) pud;
1331 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1332 pmd = (pmd_t *) pud_deref(*pud);
190a1d72 1333 return pmd + pmd_index(address);
1da177e4
LT		 1334}
1335
f4815ac6 1336#endif /* CONFIG_64BIT */
1da177e4 1337
190a1d72
MS		 1338#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1339#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1340#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 1341
190a1d72 1342#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1da177e4 1343
190a1d72
MS		 1344/* Find an entry in the lowest level page table.. */
1345#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1346#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1da177e4 1347#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1da177e4 1348#define pte_unmap(pte) do { } while (0)
1da177e4 1349
1ae1c1d0
GS		 1350static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
1351{
1352 unsigned long sto = (unsigned long) pmdp -
1353 pmd_index(address) * sizeof(pmd_t);
1354
e5098611 1355 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)) {
1ae1c1d0
GS		 1356 asm volatile(
1357 " .insn rrf,0xb98e0000,%2,%3,0,0"
1358 : "=m" (*pmdp)
1359 : "m" (*pmdp), "a" (sto),
1360 "a" ((address & HPAGE_MASK))
1361 : "cc"
1362 );
1363 }
1364}
1365
e5098611
MS		 1366static inline void __pmd_csp(pmd_t *pmdp)
1367{
1368 register unsigned long reg2 asm("2") = pmd_val(*pmdp);
1369 register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
1370 _SEGMENT_ENTRY_INVALID;
1371 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
1372
1373 asm volatile(
1374 " csp %1,%3"
1375 : "=m" (*pmdp)
1376 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
1377}
1378
106c992a 1379#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1ae1c1d0
GS		 1380static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1381{
d8e7a33d 1382 /*
e5098611 1383 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx)
d8e7a33d
GS		 1384 * Convert to segment table entry format.
1385 */
1386 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1387 return pgprot_val(SEGMENT_NONE);
e5098611
MS		 1388 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ))
1389 return pgprot_val(SEGMENT_READ);
1390 return pgprot_val(SEGMENT_WRITE);
1ae1c1d0
GS		 1391}
1392
0944fe3f
MS		 1393static inline pmd_t pmd_mkyoung(pmd_t pmd)
1394{
1395#ifdef CONFIG_64BIT
1396 if (pmd_prot_none(pmd)) {
1397 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1398 } else {
1399 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
1400 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID;
1401 }
1402#endif
1403 return pmd;
1404}
1405
1406static inline pmd_t pmd_mkold(pmd_t pmd)
1407{
1408#ifdef CONFIG_64BIT
1409 if (pmd_prot_none(pmd)) {
1410 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1411 } else {
1412 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG;
1413 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1414 }
1415#endif
1416 return pmd;
1417}
1418
1ae1c1d0
GS		 1419static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1420{
0944fe3f
MS		 1421 int young;
1422
1423 young = pmd_young(pmd);
1ae1c1d0
GS		 1424 pmd_val(pmd) &= _SEGMENT_CHG_MASK;
1425 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
0944fe3f
MS		 1426 if (young)
1427 pmd = pmd_mkyoung(pmd);
1ae1c1d0
GS		 1428 return pmd;
1429}
1430
106c992a 1431static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1ae1c1d0 1432{
106c992a
GS		 1433 pmd_t __pmd;
1434 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
0944fe3f 1435 return pmd_mkyoung(__pmd);
1ae1c1d0
GS		 1436}
1437
1438static inline pmd_t pmd_mkwrite(pmd_t pmd)
1439{
0944fe3f
MS		 1440 /* Do not clobber PROT_NONE segments! */
1441 if (!pmd_prot_none(pmd))
e5098611 1442 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1ae1c1d0
GS		 1443 return pmd;
1444}
106c992a
GS		 1445#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1446
3eabaee9
MS		 1447static inline void pmdp_flush_lazy(struct mm_struct *mm,
1448 unsigned long address, pmd_t *pmdp)
1449{
1450 int active = (mm == current->active_mm) ? 1 : 0;
1451
1452 if ((atomic_read(&mm->context.attach_count) & 0xffff) > active)
1453 __pmd_idte(address, pmdp);
1454 else
1455 mm->context.flush_mm = 1;
1456}
1457
106c992a
GS		 1458#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1459
1460#define __HAVE_ARCH_PGTABLE_DEPOSIT
6b0b50b0
AK		 1461extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1462 pgtable_t pgtable);
106c992a
GS		 1463
1464#define __HAVE_ARCH_PGTABLE_WITHDRAW
6b0b50b0 1465extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
106c992a
GS		 1466
1467static inline int pmd_trans_splitting(pmd_t pmd)
1468{
1469 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
1470}
1471
1472static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1473 pmd_t *pmdp, pmd_t entry)
1474{
e5098611 1475 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INVALID) && MACHINE_HAS_EDAT1)
106c992a
GS		 1476 pmd_val(entry) |= _SEGMENT_ENTRY_CO;
1477 *pmdp = entry;
1478}
1479
1480static inline pmd_t pmd_mkhuge(pmd_t pmd)
1481{
1482 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1483 return pmd;
1484}
1ae1c1d0
GS		 1485
1486static inline pmd_t pmd_wrprotect(pmd_t pmd)
1487{
0944fe3f
MS		 1488 /* Do not clobber PROT_NONE segments! */
1489 if (!pmd_prot_none(pmd))
1490 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1ae1c1d0
GS		 1491 return pmd;
1492}
1493
1494static inline pmd_t pmd_mkdirty(pmd_t pmd)
1495{
1496 /* No dirty bit in the segment table entry. */
1497 return pmd;
1498}
1499
1ae1c1d0
GS		 1500#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1501static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1502 unsigned long address, pmd_t *pmdp)
1503{
0944fe3f 1504 pmd_t pmd;
1ae1c1d0 1505
0944fe3f
MS		 1506 pmd = *pmdp;
1507 __pmd_idte(address, pmdp);
1508 *pmdp = pmd_mkold(pmd);
1509 return pmd_young(pmd);
1ae1c1d0
GS		 1510}
1511
1512#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1513static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1514 unsigned long address, pmd_t *pmdp)
1515{
1516 pmd_t pmd = *pmdp;
1517
1518 __pmd_idte(address, pmdp);
1519 pmd_clear(pmdp);
1520 return pmd;
1521}
1522
1523#define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1524static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1525 unsigned long address, pmd_t *pmdp)
1526{
1527 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1528}
1529
1530#define __HAVE_ARCH_PMDP_INVALIDATE
1531static inline void pmdp_invalidate(struct vm_area_struct *vma,
1532 unsigned long address, pmd_t *pmdp)
1533{
1534 __pmd_idte(address, pmdp);
1535}
1536
be328650
GS		 1537#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1538static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1539 unsigned long address, pmd_t *pmdp)
1540{
1541 pmd_t pmd = *pmdp;
1542
1543 if (pmd_write(pmd)) {
1544 __pmd_idte(address, pmdp);
1545 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1546 }
1547}
1548
1ae1c1d0
GS		 1549#define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1550#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1551
1552static inline int pmd_trans_huge(pmd_t pmd)
1553{
1554 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1555}
1556
1557static inline int has_transparent_hugepage(void)
1558{
1559 return MACHINE_HAS_HPAGE ? 1 : 0;
1560}
1561
1562static inline unsigned long pmd_pfn(pmd_t pmd)
1563{
171c4006 1564 return pmd_val(pmd) >> PAGE_SHIFT;
1ae1c1d0 1565}
75077afb
GS		 1566#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1567
1da177e4
LT		 1568/*
1569 * 31 bit swap entry format:
1570 * A page-table entry has some bits we have to treat in a special way.
1571 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1572 * exception will occur instead of a page translation exception. The
1573 * specifiation exception has the bad habit not to store necessary
1574 * information in the lowcore.
e5098611
MS		 1575 * Bits 21, 22, 30 and 31 are used to indicate the page type.
1576 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1da177e4
LT		 1577 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1578 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1579 * plus 24 for the offset.
1580 * 0| offset |0110|o|type |00|
1581 * 0 0000000001111111111 2222 2 22222 33
1582 * 0 1234567890123456789 0123 4 56789 01
1583 *
1584 * 64 bit swap entry format:
1585 * A page-table entry has some bits we have to treat in a special way.
1586 * Bits 52 and bit 55 have to be zero, otherwise an specification
1587 * exception will occur instead of a page translation exception. The
1588 * specifiation exception has the bad habit not to store necessary
1589 * information in the lowcore.
e5098611
MS		 1590 * Bits 53, 54, 62 and 63 are used to indicate the page type.
1591 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1da177e4
LT		 1592 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1593 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1594 * plus 56 for the offset.
1595 * | offset |0110|o|type |00|
1596 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1597 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1598 */
f4815ac6 1599#ifndef CONFIG_64BIT
1da177e4
LT		 1600#define __SWP_OFFSET_MASK (~0UL >> 12)
1601#else
1602#define __SWP_OFFSET_MASK (~0UL >> 11)
1603#endif
4448aaf0 1604static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT		 1605{
1606 pte_t pte;
1607 offset &= __SWP_OFFSET_MASK;
e5098611 1608 pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) |
1da177e4
LT		 1609 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1610 return pte;
1611}
1612
1613#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1614#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1615#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1616
1617#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1618#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1619
f4815ac6 1620#ifndef CONFIG_64BIT
1da177e4 1621# define PTE_FILE_MAX_BITS 26
f4815ac6 1622#else /* CONFIG_64BIT */
1da177e4 1623# define PTE_FILE_MAX_BITS 59
f4815ac6 1624#endif /* CONFIG_64BIT */
1da177e4
LT		 1625
1626#define pte_to_pgoff(__pte) \
1627 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1628
1629#define pgoff_to_pte(__off) \
1630 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
e5098611 1631 | _PAGE_INVALID | _PAGE_PROTECT })
1da177e4
LT		 1632
1633#endif /* !__ASSEMBLY__ */
1634
1635#define kern_addr_valid(addr) (1)
1636
17f34580
HC		 1637extern int vmem_add_mapping(unsigned long start, unsigned long size);
1638extern int vmem_remove_mapping(unsigned long start, unsigned long size);
402b0862 1639extern int s390_enable_sie(void);
f4eb07c1 1640
1da177e4
LT		 1641/*
1642 * No page table caches to initialise
1643 */
765a0cac
HC		 1644static inline void pgtable_cache_init(void) { }
1645static inline void check_pgt_cache(void) { }
1da177e4 1646
1da177e4
LT		 1647#include <asm-generic/pgtable.h>
1648
1649#endif /* _S390_PAGE_H */
Linux kernel - Deliverables
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