Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999, 2000 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com) |
5 | * Ulrich Weigand (weigand@de.ibm.com) | |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
7 | * | |
8 | * Derived from "include/asm-i386/pgtable.h" | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_S390_PGTABLE_H | |
12 | #define _ASM_S390_PGTABLE_H | |
13 | ||
1da177e4 | 14 | /* |
a1c843b8 MS |
15 | * The Linux memory management assumes a three-level page table setup. |
16 | * For s390 64 bit we use up to four of the five levels the hardware | |
17 | * provides (region first tables are not used). | |
1da177e4 LT |
18 | * |
19 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
20 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
21 | * into the pgd entry) | |
22 | * | |
23 | * This file contains the functions and defines necessary to modify and use | |
24 | * the S390 page table tree. | |
25 | */ | |
26 | #ifndef __ASSEMBLY__ | |
9789db08 | 27 | #include <linux/sched.h> |
2dcea57a | 28 | #include <linux/mm_types.h> |
abf09bed | 29 | #include <linux/page-flags.h> |
527e30b4 | 30 | #include <linux/radix-tree.h> |
1da177e4 | 31 | #include <asm/bug.h> |
b2fa47e6 | 32 | #include <asm/page.h> |
1da177e4 | 33 | |
1da177e4 LT |
34 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
35 | extern void paging_init(void); | |
2b67fc46 | 36 | extern void vmem_map_init(void); |
1da177e4 LT |
37 | |
38 | /* | |
39 | * The S390 doesn't have any external MMU info: the kernel page | |
40 | * tables contain all the necessary information. | |
41 | */ | |
4b3073e1 | 42 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
b113da65 | 43 | #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) |
1da177e4 LT |
44 | |
45 | /* | |
238ec4ef | 46 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
47 | * for zero-mapped memory areas etc.. |
48 | */ | |
238ec4ef MS |
49 | |
50 | extern unsigned long empty_zero_page; | |
51 | extern unsigned long zero_page_mask; | |
52 | ||
53 | #define ZERO_PAGE(vaddr) \ | |
54 | (virt_to_page((void *)(empty_zero_page + \ | |
55 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
816422ad | 56 | #define __HAVE_COLOR_ZERO_PAGE |
238ec4ef | 57 | |
4f2e2903 | 58 | /* TODO: s390 cannot support io_remap_pfn_range... */ |
1da177e4 LT |
59 | #endif /* !__ASSEMBLY__ */ |
60 | ||
61 | /* | |
62 | * PMD_SHIFT determines the size of the area a second-level page | |
63 | * table can map | |
64 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
65 | */ | |
5a79859a HC |
66 | #define PMD_SHIFT 20 |
67 | #define PUD_SHIFT 31 | |
68 | #define PGDIR_SHIFT 42 | |
1da177e4 LT |
69 | |
70 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
71 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
72 | #define PUD_SIZE (1UL << PUD_SHIFT) |
73 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
74 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
75 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
76 | |
77 | /* | |
78 | * entries per page directory level: the S390 is two-level, so | |
79 | * we don't really have any PMD directory physically. | |
80 | * for S390 segment-table entries are combined to one PGD | |
81 | * that leads to 1024 pte per pgd | |
82 | */ | |
146e4b3c | 83 | #define PTRS_PER_PTE 256 |
146e4b3c | 84 | #define PTRS_PER_PMD 2048 |
5a216a20 | 85 | #define PTRS_PER_PUD 2048 |
146e4b3c | 86 | #define PTRS_PER_PGD 2048 |
1da177e4 | 87 | |
d016bf7e | 88 | #define FIRST_USER_ADDRESS 0UL |
d455a369 | 89 | |
1da177e4 LT |
90 | #define pte_ERROR(e) \ |
91 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
92 | #define pmd_ERROR(e) \ | |
93 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
94 | #define pud_ERROR(e) \ |
95 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
96 | #define pgd_ERROR(e) \ |
97 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
98 | ||
99 | #ifndef __ASSEMBLY__ | |
100 | /* | |
a1c843b8 MS |
101 | * The vmalloc and module area will always be on the topmost area of the |
102 | * kernel mapping. We reserve 128GB (64bit) for vmalloc and modules. | |
c972cc60 HC |
103 | * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where |
104 | * modules will reside. That makes sure that inter module branches always | |
105 | * happen without trampolines and in addition the placement within a 2GB frame | |
106 | * is branch prediction unit friendly. | |
8b62bc96 | 107 | */ |
239a6425 | 108 | extern unsigned long VMALLOC_START; |
14045ebf MS |
109 | extern unsigned long VMALLOC_END; |
110 | extern struct page *vmemmap; | |
239a6425 | 111 | |
14045ebf | 112 | #define VMEM_MAX_PHYS ((unsigned long) vmemmap) |
5fd9c6e2 | 113 | |
c972cc60 HC |
114 | extern unsigned long MODULES_VADDR; |
115 | extern unsigned long MODULES_END; | |
116 | #define MODULES_VADDR MODULES_VADDR | |
117 | #define MODULES_END MODULES_END | |
118 | #define MODULES_LEN (1UL << 31) | |
c972cc60 | 119 | |
c933146a HC |
120 | static inline int is_module_addr(void *addr) |
121 | { | |
c933146a HC |
122 | BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); |
123 | if (addr < (void *)MODULES_VADDR) | |
124 | return 0; | |
125 | if (addr > (void *)MODULES_END) | |
126 | return 0; | |
c933146a HC |
127 | return 1; |
128 | } | |
129 | ||
1da177e4 | 130 | /* |
1da177e4 | 131 | * A 64 bit pagetable entry of S390 has following format: |
6a985c61 | 132 | * | PFRA |0IPC| OS | |
1da177e4 LT |
133 | * 0000000000111111111122222222223333333333444444444455555555556666 |
134 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
135 | * | |
136 | * I Page-Invalid Bit: Page is not available for address-translation | |
137 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 138 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
139 | * |
140 | * A 64 bit segmenttable entry of S390 has following format: | |
141 | * | P-table origin | TT | |
142 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
143 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
144 | * | |
145 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
146 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
147 | * P Page-Protection Bit: Store access not possible for page | |
148 | * TT Type 00 | |
149 | * | |
150 | * A 64 bit region table entry of S390 has following format: | |
151 | * | S-table origin | TF TTTL | |
152 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
153 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
154 | * | |
155 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
156 | * TT Type 01 | |
157 | * TF | |
190a1d72 | 158 | * TL Table length |
1da177e4 LT |
159 | * |
160 | * The 64 bit regiontable origin of S390 has following format: | |
161 | * | region table origon | DTTL | |
162 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
163 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
164 | * | |
165 | * X Space-Switch event: | |
166 | * G Segment-Invalid Bit: | |
167 | * P Private-Space Bit: | |
168 | * S Storage-Alteration: | |
169 | * R Real space | |
170 | * TL Table-Length: | |
171 | * | |
172 | * A storage key has the following format: | |
173 | * | ACC |F|R|C|0| | |
174 | * 0 3 4 5 6 7 | |
175 | * ACC: access key | |
176 | * F : fetch protection bit | |
177 | * R : referenced bit | |
178 | * C : changed bit | |
179 | */ | |
180 | ||
181 | /* Hardware bits in the page table entry */ | |
e5098611 | 182 | #define _PAGE_PROTECT 0x200 /* HW read-only bit */ |
83377484 | 183 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ |
e5098611 | 184 | #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ |
3610cce8 MS |
185 | |
186 | /* Software bits in the page table entry */ | |
e5098611 | 187 | #define _PAGE_PRESENT 0x001 /* SW pte present bit */ |
e5098611 MS |
188 | #define _PAGE_YOUNG 0x004 /* SW pte young bit */ |
189 | #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ | |
0944fe3f MS |
190 | #define _PAGE_READ 0x010 /* SW pte read bit */ |
191 | #define _PAGE_WRITE 0x020 /* SW pte write bit */ | |
192 | #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ | |
b31288fa | 193 | #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ |
a08cb629 | 194 | #define __HAVE_ARCH_PTE_SPECIAL |
1da177e4 | 195 | |
138c9021 | 196 | /* Set of bits not changed in pte_modify */ |
6a5c1482 HC |
197 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ |
198 | _PAGE_YOUNG) | |
53492b1d | 199 | |
83377484 | 200 | /* |
6e76d4b2 KS |
201 | * handle_pte_fault uses pte_present and pte_none to find out the pte type |
202 | * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to | |
203 | * distinguish present from not-present ptes. It is changed only with the page | |
204 | * table lock held. | |
83377484 | 205 | * |
e5098611 | 206 | * The following table gives the different possible bit combinations for |
a1c843b8 MS |
207 | * the pte hardware and software bits in the last 12 bits of a pte |
208 | * (. unassigned bit, x don't care, t swap type): | |
83377484 | 209 | * |
0944fe3f MS |
210 | * 842100000000 |
211 | * 000084210000 | |
212 | * 000000008421 | |
a1c843b8 MS |
213 | * .IR.uswrdy.p |
214 | * empty .10.00000000 | |
215 | * swap .11..ttttt.0 | |
216 | * prot-none, clean, old .11.xx0000.1 | |
217 | * prot-none, clean, young .11.xx0001.1 | |
218 | * prot-none, dirty, old .10.xx0010.1 | |
219 | * prot-none, dirty, young .10.xx0011.1 | |
220 | * read-only, clean, old .11.xx0100.1 | |
221 | * read-only, clean, young .01.xx0101.1 | |
222 | * read-only, dirty, old .11.xx0110.1 | |
223 | * read-only, dirty, young .01.xx0111.1 | |
224 | * read-write, clean, old .11.xx1100.1 | |
225 | * read-write, clean, young .01.xx1101.1 | |
226 | * read-write, dirty, old .10.xx1110.1 | |
227 | * read-write, dirty, young .00.xx1111.1 | |
228 | * HW-bits: R read-only, I invalid | |
229 | * SW-bits: p present, y young, d dirty, r read, w write, s special, | |
230 | * u unused, l large | |
e5098611 | 231 | * |
a1c843b8 MS |
232 | * pte_none is true for the bit pattern .10.00000000, pte == 0x400 |
233 | * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 | |
234 | * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 | |
83377484 MS |
235 | */ |
236 | ||
3610cce8 MS |
237 | /* Bits in the segment/region table address-space-control-element */ |
238 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
239 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
240 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
241 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
242 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
243 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
244 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
245 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
246 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
247 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
248 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
249 | ||
250 | /* Bits in the region table entry */ | |
251 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
e5098611 MS |
252 | #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ |
253 | #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ | |
3610cce8 MS |
254 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ |
255 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
256 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
257 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
258 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
259 | ||
260 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
e5098611 | 261 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) |
3610cce8 | 262 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) |
e5098611 | 263 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) |
3610cce8 | 264 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) |
e5098611 | 265 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) |
3610cce8 | 266 | |
18da2369 | 267 | #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ |
1819ed1f | 268 | #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ |
18da2369 | 269 | |
1da177e4 | 270 | /* Bits in the segment table entry */ |
0944fe3f | 271 | #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL |
152125b7 | 272 | #define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL |
ea81531d | 273 | #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ |
3610cce8 | 274 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
e5098611 MS |
275 | #define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */ |
276 | #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ | |
1da177e4 | 277 | |
3610cce8 | 278 | #define _SEGMENT_ENTRY (0) |
e5098611 | 279 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) |
3610cce8 | 280 | |
152125b7 MS |
281 | #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ |
282 | #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ | |
283 | #define _SEGMENT_ENTRY_SPLIT 0x0800 /* THP splitting bit */ | |
284 | #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ | |
152125b7 MS |
285 | #define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */ |
286 | #define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */ | |
0944fe3f MS |
287 | |
288 | /* | |
289 | * Segment table entry encoding (R = read-only, I = invalid, y = young bit): | |
152125b7 MS |
290 | * dy..R...I...wr |
291 | * prot-none, clean, old 00..1...1...00 | |
292 | * prot-none, clean, young 01..1...1...00 | |
293 | * prot-none, dirty, old 10..1...1...00 | |
294 | * prot-none, dirty, young 11..1...1...00 | |
295 | * read-only, clean, old 00..1...1...01 | |
296 | * read-only, clean, young 01..1...0...01 | |
297 | * read-only, dirty, old 10..1...1...01 | |
298 | * read-only, dirty, young 11..1...0...01 | |
299 | * read-write, clean, old 00..1...1...11 | |
300 | * read-write, clean, young 01..1...0...11 | |
301 | * read-write, dirty, old 10..0...1...11 | |
302 | * read-write, dirty, young 11..0...0...11 | |
0944fe3f MS |
303 | * The segment table origin is used to distinguish empty (origin==0) from |
304 | * read-write, old segment table entries (origin!=0) | |
a1c843b8 MS |
305 | * HW-bits: R read-only, I invalid |
306 | * SW-bits: y young, d dirty, r read, w write | |
0944fe3f | 307 | */ |
e5098611 | 308 | |
152125b7 | 309 | #define _SEGMENT_ENTRY_SPLIT_BIT 11 /* THP splitting bit number */ |
1ae1c1d0 | 310 | |
6c61cfe9 | 311 | /* Page status table bits for virtualization */ |
0d0dafc1 MS |
312 | #define PGSTE_ACC_BITS 0xf000000000000000UL |
313 | #define PGSTE_FP_BIT 0x0800000000000000UL | |
314 | #define PGSTE_PCL_BIT 0x0080000000000000UL | |
315 | #define PGSTE_HR_BIT 0x0040000000000000UL | |
316 | #define PGSTE_HC_BIT 0x0020000000000000UL | |
317 | #define PGSTE_GR_BIT 0x0004000000000000UL | |
318 | #define PGSTE_GC_BIT 0x0002000000000000UL | |
0a61b222 MS |
319 | #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ |
320 | #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ | |
6c61cfe9 | 321 | |
b31288fa KW |
322 | /* Guest Page State used for virtualization */ |
323 | #define _PGSTE_GPS_ZERO 0x0000000080000000UL | |
324 | #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL | |
325 | #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL | |
326 | #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL | |
327 | ||
1da177e4 | 328 | /* |
3610cce8 MS |
329 | * A user page table pointer has the space-switch-event bit, the |
330 | * private-space-control bit and the storage-alteration-event-control | |
331 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 332 | */ |
3610cce8 MS |
333 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
334 | _ASCE_ALT_EVENT) | |
1da177e4 | 335 | |
1da177e4 | 336 | /* |
9282ed92 | 337 | * Page protection definitions. |
1da177e4 | 338 | */ |
e5098611 | 339 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID) |
0944fe3f MS |
340 | #define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \ |
341 | _PAGE_INVALID | _PAGE_PROTECT) | |
342 | #define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
343 | _PAGE_INVALID | _PAGE_PROTECT) | |
344 | ||
345 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
346 | _PAGE_YOUNG | _PAGE_DIRTY) | |
347 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ | |
348 | _PAGE_YOUNG | _PAGE_DIRTY) | |
349 | #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ | |
350 | _PAGE_PROTECT) | |
1da177e4 LT |
351 | |
352 | /* | |
043d0708 MS |
353 | * On s390 the page table entry has an invalid bit and a read-only bit. |
354 | * Read permission implies execute permission and write permission | |
355 | * implies read permission. | |
1da177e4 LT |
356 | */ |
357 | /*xwr*/ | |
9282ed92 | 358 | #define __P000 PAGE_NONE |
e5098611 MS |
359 | #define __P001 PAGE_READ |
360 | #define __P010 PAGE_READ | |
361 | #define __P011 PAGE_READ | |
362 | #define __P100 PAGE_READ | |
363 | #define __P101 PAGE_READ | |
364 | #define __P110 PAGE_READ | |
365 | #define __P111 PAGE_READ | |
9282ed92 GS |
366 | |
367 | #define __S000 PAGE_NONE | |
e5098611 MS |
368 | #define __S001 PAGE_READ |
369 | #define __S010 PAGE_WRITE | |
370 | #define __S011 PAGE_WRITE | |
371 | #define __S100 PAGE_READ | |
372 | #define __S101 PAGE_READ | |
373 | #define __S110 PAGE_WRITE | |
374 | #define __S111 PAGE_WRITE | |
1da177e4 | 375 | |
106c992a GS |
376 | /* |
377 | * Segment entry (large page) protection definitions. | |
378 | */ | |
e5098611 MS |
379 | #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ |
380 | _SEGMENT_ENTRY_PROTECT) | |
152125b7 MS |
381 | #define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \ |
382 | _SEGMENT_ENTRY_READ) | |
383 | #define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \ | |
384 | _SEGMENT_ENTRY_WRITE) | |
106c992a | 385 | |
b2fa47e6 MS |
386 | static inline int mm_has_pgste(struct mm_struct *mm) |
387 | { | |
388 | #ifdef CONFIG_PGSTE | |
389 | if (unlikely(mm->context.has_pgste)) | |
390 | return 1; | |
391 | #endif | |
392 | return 0; | |
393 | } | |
65eef335 | 394 | |
0b46e0a3 MS |
395 | static inline int mm_alloc_pgste(struct mm_struct *mm) |
396 | { | |
397 | #ifdef CONFIG_PGSTE | |
398 | if (unlikely(mm->context.alloc_pgste)) | |
399 | return 1; | |
400 | #endif | |
401 | return 0; | |
402 | } | |
403 | ||
2faee8ff DD |
404 | /* |
405 | * In the case that a guest uses storage keys | |
406 | * faults should no longer be backed by zero pages | |
407 | */ | |
408 | #define mm_forbids_zeropage mm_use_skey | |
65eef335 DD |
409 | static inline int mm_use_skey(struct mm_struct *mm) |
410 | { | |
411 | #ifdef CONFIG_PGSTE | |
412 | if (mm->context.use_skey) | |
413 | return 1; | |
414 | #endif | |
415 | return 0; | |
416 | } | |
417 | ||
1da177e4 LT |
418 | /* |
419 | * pgd/pmd/pte query functions | |
420 | */ | |
5a216a20 MS |
421 | static inline int pgd_present(pgd_t pgd) |
422 | { | |
6252d702 MS |
423 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
424 | return 1; | |
5a216a20 MS |
425 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
426 | } | |
427 | ||
428 | static inline int pgd_none(pgd_t pgd) | |
429 | { | |
6252d702 MS |
430 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
431 | return 0; | |
e5098611 | 432 | return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; |
5a216a20 MS |
433 | } |
434 | ||
435 | static inline int pgd_bad(pgd_t pgd) | |
436 | { | |
6252d702 MS |
437 | /* |
438 | * With dynamic page table levels the pgd can be a region table | |
439 | * entry or a segment table entry. Check for the bit that are | |
440 | * invalid for either table entry. | |
441 | */ | |
5a216a20 | 442 | unsigned long mask = |
e5098611 | 443 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
444 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
445 | return (pgd_val(pgd) & mask) != 0; | |
446 | } | |
190a1d72 MS |
447 | |
448 | static inline int pud_present(pud_t pud) | |
1da177e4 | 449 | { |
6252d702 MS |
450 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
451 | return 1; | |
0d017923 | 452 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
453 | } |
454 | ||
190a1d72 | 455 | static inline int pud_none(pud_t pud) |
1da177e4 | 456 | { |
6252d702 MS |
457 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
458 | return 0; | |
e5098611 | 459 | return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL; |
1da177e4 LT |
460 | } |
461 | ||
18da2369 HC |
462 | static inline int pud_large(pud_t pud) |
463 | { | |
464 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) | |
465 | return 0; | |
466 | return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); | |
467 | } | |
468 | ||
190a1d72 | 469 | static inline int pud_bad(pud_t pud) |
1da177e4 | 470 | { |
6252d702 MS |
471 | /* |
472 | * With dynamic page table levels the pud can be a region table | |
473 | * entry or a segment table entry. Check for the bit that are | |
474 | * invalid for either table entry. | |
475 | */ | |
5a216a20 | 476 | unsigned long mask = |
e5098611 | 477 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID & |
5a216a20 MS |
478 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
479 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
480 | } |
481 | ||
4448aaf0 | 482 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 483 | { |
e5098611 | 484 | return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
485 | } |
486 | ||
4448aaf0 | 487 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 488 | { |
e5098611 | 489 | return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
490 | } |
491 | ||
378b1e7a HC |
492 | static inline int pmd_large(pmd_t pmd) |
493 | { | |
e5098611 | 494 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; |
378b1e7a HC |
495 | } |
496 | ||
7cded342 | 497 | static inline unsigned long pmd_pfn(pmd_t pmd) |
0944fe3f | 498 | { |
152125b7 MS |
499 | unsigned long origin_mask; |
500 | ||
501 | origin_mask = _SEGMENT_ENTRY_ORIGIN; | |
502 | if (pmd_large(pmd)) | |
503 | origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; | |
504 | return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT; | |
0944fe3f MS |
505 | } |
506 | ||
4448aaf0 | 507 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 508 | { |
0944fe3f MS |
509 | if (pmd_large(pmd)) |
510 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0; | |
0944fe3f | 511 | return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; |
1da177e4 LT |
512 | } |
513 | ||
75077afb GS |
514 | #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH |
515 | extern void pmdp_splitting_flush(struct vm_area_struct *vma, | |
516 | unsigned long addr, pmd_t *pmdp); | |
517 | ||
1ae1c1d0 GS |
518 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
519 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
520 | unsigned long address, pmd_t *pmdp, | |
521 | pmd_t entry, int dirty); | |
522 | ||
523 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
524 | extern int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
525 | unsigned long address, pmd_t *pmdp); | |
526 | ||
527 | #define __HAVE_ARCH_PMD_WRITE | |
528 | static inline int pmd_write(pmd_t pmd) | |
529 | { | |
152125b7 MS |
530 | return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; |
531 | } | |
532 | ||
533 | static inline int pmd_dirty(pmd_t pmd) | |
534 | { | |
535 | int dirty = 1; | |
536 | if (pmd_large(pmd)) | |
537 | dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; | |
538 | return dirty; | |
1ae1c1d0 GS |
539 | } |
540 | ||
541 | static inline int pmd_young(pmd_t pmd) | |
542 | { | |
152125b7 MS |
543 | int young = 1; |
544 | if (pmd_large(pmd)) | |
0944fe3f | 545 | young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; |
0944fe3f | 546 | return young; |
1ae1c1d0 GS |
547 | } |
548 | ||
e5098611 | 549 | static inline int pte_present(pte_t pte) |
1da177e4 | 550 | { |
e5098611 MS |
551 | /* Bit pattern: (pte & 0x001) == 0x001 */ |
552 | return (pte_val(pte) & _PAGE_PRESENT) != 0; | |
1da177e4 LT |
553 | } |
554 | ||
e5098611 | 555 | static inline int pte_none(pte_t pte) |
1da177e4 | 556 | { |
e5098611 MS |
557 | /* Bit pattern: pte == 0x400 */ |
558 | return pte_val(pte) == _PAGE_INVALID; | |
1da177e4 LT |
559 | } |
560 | ||
b31288fa KW |
561 | static inline int pte_swap(pte_t pte) |
562 | { | |
a1c843b8 MS |
563 | /* Bit pattern: (pte & 0x201) == 0x200 */ |
564 | return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) | |
565 | == _PAGE_PROTECT; | |
b31288fa KW |
566 | } |
567 | ||
7e675137 NP |
568 | static inline int pte_special(pte_t pte) |
569 | { | |
a08cb629 | 570 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
571 | } |
572 | ||
ba8a9229 | 573 | #define __HAVE_ARCH_PTE_SAME |
b2fa47e6 MS |
574 | static inline int pte_same(pte_t a, pte_t b) |
575 | { | |
576 | return pte_val(a) == pte_val(b); | |
577 | } | |
1da177e4 | 578 | |
b54565b8 MS |
579 | #ifdef CONFIG_NUMA_BALANCING |
580 | static inline int pte_protnone(pte_t pte) | |
581 | { | |
582 | return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); | |
583 | } | |
584 | ||
585 | static inline int pmd_protnone(pmd_t pmd) | |
586 | { | |
587 | /* pmd_large(pmd) implies pmd_present(pmd) */ | |
588 | return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); | |
589 | } | |
590 | #endif | |
591 | ||
b2fa47e6 | 592 | static inline pgste_t pgste_get_lock(pte_t *ptep) |
5b7baf05 | 593 | { |
b2fa47e6 | 594 | unsigned long new = 0; |
5b7baf05 | 595 | #ifdef CONFIG_PGSTE |
b2fa47e6 MS |
596 | unsigned long old; |
597 | ||
5b7baf05 | 598 | preempt_disable(); |
b2fa47e6 MS |
599 | asm( |
600 | " lg %0,%2\n" | |
601 | "0: lgr %1,%0\n" | |
0d0dafc1 MS |
602 | " nihh %0,0xff7f\n" /* clear PCL bit in old */ |
603 | " oihh %1,0x0080\n" /* set PCL bit in new */ | |
b2fa47e6 MS |
604 | " csg %0,%1,%2\n" |
605 | " jl 0b\n" | |
606 | : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 | 607 | : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); |
5b7baf05 | 608 | #endif |
b2fa47e6 | 609 | return __pgste(new); |
5b7baf05 CB |
610 | } |
611 | ||
b2fa47e6 | 612 | static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) |
5b7baf05 CB |
613 | { |
614 | #ifdef CONFIG_PGSTE | |
b2fa47e6 | 615 | asm( |
0d0dafc1 | 616 | " nihh %1,0xff7f\n" /* clear PCL bit */ |
b2fa47e6 MS |
617 | " stg %1,%0\n" |
618 | : "=Q" (ptep[PTRS_PER_PTE]) | |
a8f6e7f7 CB |
619 | : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) |
620 | : "cc", "memory"); | |
5b7baf05 CB |
621 | preempt_enable(); |
622 | #endif | |
623 | } | |
624 | ||
d56c893d MS |
625 | static inline pgste_t pgste_get(pte_t *ptep) |
626 | { | |
627 | unsigned long pgste = 0; | |
628 | #ifdef CONFIG_PGSTE | |
629 | pgste = *(unsigned long *)(ptep + PTRS_PER_PTE); | |
630 | #endif | |
631 | return __pgste(pgste); | |
632 | } | |
633 | ||
3a82603b CB |
634 | static inline void pgste_set(pte_t *ptep, pgste_t pgste) |
635 | { | |
636 | #ifdef CONFIG_PGSTE | |
637 | *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; | |
638 | #endif | |
639 | } | |
640 | ||
65eef335 DD |
641 | static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, |
642 | struct mm_struct *mm) | |
5b7baf05 CB |
643 | { |
644 | #ifdef CONFIG_PGSTE | |
0944fe3f | 645 | unsigned long address, bits, skey; |
b2fa47e6 | 646 | |
65eef335 | 647 | if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) |
09b53883 | 648 | return pgste; |
a43a9d93 | 649 | address = pte_val(*ptep) & PAGE_MASK; |
0944fe3f | 650 | skey = (unsigned long) page_get_storage_key(address); |
b2fa47e6 | 651 | bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); |
b2fa47e6 | 652 | /* Transfer page changed & referenced bit to guest bits in pgste */ |
0d0dafc1 | 653 | pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ |
b2fa47e6 | 654 | /* Copy page access key and fetch protection bit to pgste */ |
0944fe3f MS |
655 | pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT); |
656 | pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; | |
b2fa47e6 MS |
657 | #endif |
658 | return pgste; | |
659 | ||
660 | } | |
661 | ||
65eef335 DD |
662 | static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, |
663 | struct mm_struct *mm) | |
b2fa47e6 MS |
664 | { |
665 | #ifdef CONFIG_PGSTE | |
a43a9d93 | 666 | unsigned long address; |
338679f7 | 667 | unsigned long nkey; |
b2fa47e6 | 668 | |
65eef335 | 669 | if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID) |
09b53883 | 670 | return; |
338679f7 | 671 | VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); |
09b53883 | 672 | address = pte_val(entry) & PAGE_MASK; |
338679f7 CB |
673 | /* |
674 | * Set page access key and fetch protection bit from pgste. | |
675 | * The guest C/R information is still in the PGSTE, set real | |
676 | * key C/R to 0. | |
677 | */ | |
fe489bf4 | 678 | nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; |
0a61b222 | 679 | nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48; |
338679f7 | 680 | page_set_storage_key(address, nkey, 0); |
5b7baf05 CB |
681 | #endif |
682 | } | |
683 | ||
0a61b222 | 684 | static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) |
abf09bed | 685 | { |
0a61b222 MS |
686 | if ((pte_val(entry) & _PAGE_PRESENT) && |
687 | (pte_val(entry) & _PAGE_WRITE) && | |
688 | !(pte_val(entry) & _PAGE_INVALID)) { | |
689 | if (!MACHINE_HAS_ESOP) { | |
690 | /* | |
691 | * Without enhanced suppression-on-protection force | |
692 | * the dirty bit on for all writable ptes. | |
693 | */ | |
694 | pte_val(entry) |= _PAGE_DIRTY; | |
695 | pte_val(entry) &= ~_PAGE_PROTECT; | |
696 | } | |
697 | if (!(pte_val(entry) & _PAGE_PROTECT)) | |
698 | /* This pte allows write access, set user-dirty */ | |
699 | pgste_val(pgste) |= PGSTE_UC_BIT; | |
abf09bed MS |
700 | } |
701 | *ptep = entry; | |
0a61b222 | 702 | return pgste; |
abf09bed MS |
703 | } |
704 | ||
e5992f2e MS |
705 | /** |
706 | * struct gmap_struct - guest address space | |
527e30b4 | 707 | * @crst_list: list of all crst tables used in the guest address space |
e5992f2e | 708 | * @mm: pointer to the parent mm_struct |
527e30b4 MS |
709 | * @guest_to_host: radix tree with guest to host address translation |
710 | * @host_to_guest: radix tree with pointer to segment table entries | |
711 | * @guest_table_lock: spinlock to protect all entries in the guest page table | |
e5992f2e | 712 | * @table: pointer to the page directory |
480e5926 | 713 | * @asce: address space control element for gmap page table |
24eb3a82 | 714 | * @pfault_enabled: defines if pfaults are applicable for the guest |
e5992f2e MS |
715 | */ |
716 | struct gmap { | |
717 | struct list_head list; | |
527e30b4 | 718 | struct list_head crst_list; |
e5992f2e | 719 | struct mm_struct *mm; |
527e30b4 MS |
720 | struct radix_tree_root guest_to_host; |
721 | struct radix_tree_root host_to_guest; | |
722 | spinlock_t guest_table_lock; | |
e5992f2e | 723 | unsigned long *table; |
480e5926 | 724 | unsigned long asce; |
c6c956b8 | 725 | unsigned long asce_end; |
2c70fe44 | 726 | void *private; |
24eb3a82 | 727 | bool pfault_enabled; |
e5992f2e MS |
728 | }; |
729 | ||
d3383632 MS |
730 | /** |
731 | * struct gmap_notifier - notify function block for page invalidation | |
732 | * @notifier_call: address of callback function | |
733 | */ | |
734 | struct gmap_notifier { | |
735 | struct list_head list; | |
6e0a0431 | 736 | void (*notifier_call)(struct gmap *gmap, unsigned long gaddr); |
d3383632 MS |
737 | }; |
738 | ||
c6c956b8 | 739 | struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit); |
e5992f2e MS |
740 | void gmap_free(struct gmap *gmap); |
741 | void gmap_enable(struct gmap *gmap); | |
742 | void gmap_disable(struct gmap *gmap); | |
743 | int gmap_map_segment(struct gmap *gmap, unsigned long from, | |
d3383632 | 744 | unsigned long to, unsigned long len); |
e5992f2e | 745 | int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); |
6e0a0431 MS |
746 | unsigned long __gmap_translate(struct gmap *, unsigned long gaddr); |
747 | unsigned long gmap_translate(struct gmap *, unsigned long gaddr); | |
527e30b4 MS |
748 | int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr); |
749 | int gmap_fault(struct gmap *, unsigned long gaddr, unsigned int fault_flags); | |
6e0a0431 MS |
750 | void gmap_discard(struct gmap *, unsigned long from, unsigned long to); |
751 | void __gmap_zap(struct gmap *, unsigned long gaddr); | |
a0bf4f14 DD |
752 | bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *); |
753 | ||
e5992f2e | 754 | |
d3383632 MS |
755 | void gmap_register_ipte_notifier(struct gmap_notifier *); |
756 | void gmap_unregister_ipte_notifier(struct gmap_notifier *); | |
757 | int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); | |
9da4e380 | 758 | void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *); |
d3383632 MS |
759 | |
760 | static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, | |
55dbbdd9 | 761 | unsigned long addr, |
d3383632 MS |
762 | pte_t *ptep, pgste_t pgste) |
763 | { | |
764 | #ifdef CONFIG_PGSTE | |
0d0dafc1 MS |
765 | if (pgste_val(pgste) & PGSTE_IN_BIT) { |
766 | pgste_val(pgste) &= ~PGSTE_IN_BIT; | |
9da4e380 | 767 | gmap_do_ipte_notify(mm, addr, ptep); |
d3383632 MS |
768 | } |
769 | #endif | |
770 | return pgste; | |
771 | } | |
772 | ||
b2fa47e6 MS |
773 | /* |
774 | * Certain architectures need to do special things when PTEs | |
775 | * within a page table are directly modified. Thus, the following | |
776 | * hook is made available. | |
777 | */ | |
778 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
779 | pte_t *ptep, pte_t entry) | |
780 | { | |
781 | pgste_t pgste; | |
782 | ||
783 | if (mm_has_pgste(mm)) { | |
784 | pgste = pgste_get_lock(ptep); | |
b31288fa | 785 | pgste_val(pgste) &= ~_PGSTE_GPS_ZERO; |
65eef335 | 786 | pgste_set_key(ptep, pgste, entry, mm); |
0a61b222 | 787 | pgste = pgste_set_pte(ptep, pgste, entry); |
b2fa47e6 | 788 | pgste_set_unlock(ptep, pgste); |
abf09bed | 789 | } else { |
b2fa47e6 | 790 | *ptep = entry; |
abf09bed | 791 | } |
b2fa47e6 MS |
792 | } |
793 | ||
1da177e4 LT |
794 | /* |
795 | * query functions pte_write/pte_dirty/pte_young only work if | |
796 | * pte_present() is true. Undefined behaviour if not.. | |
797 | */ | |
4448aaf0 | 798 | static inline int pte_write(pte_t pte) |
1da177e4 | 799 | { |
e5098611 | 800 | return (pte_val(pte) & _PAGE_WRITE) != 0; |
1da177e4 LT |
801 | } |
802 | ||
4448aaf0 | 803 | static inline int pte_dirty(pte_t pte) |
1da177e4 | 804 | { |
e5098611 | 805 | return (pte_val(pte) & _PAGE_DIRTY) != 0; |
1da177e4 LT |
806 | } |
807 | ||
4448aaf0 | 808 | static inline int pte_young(pte_t pte) |
1da177e4 | 809 | { |
0944fe3f | 810 | return (pte_val(pte) & _PAGE_YOUNG) != 0; |
1da177e4 LT |
811 | } |
812 | ||
b31288fa KW |
813 | #define __HAVE_ARCH_PTE_UNUSED |
814 | static inline int pte_unused(pte_t pte) | |
815 | { | |
816 | return pte_val(pte) & _PAGE_UNUSED; | |
817 | } | |
818 | ||
1da177e4 LT |
819 | /* |
820 | * pgd/pmd/pte modification functions | |
821 | */ | |
822 | ||
b2fa47e6 | 823 | static inline void pgd_clear(pgd_t *pgd) |
5a216a20 | 824 | { |
6252d702 MS |
825 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
826 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
827 | } |
828 | ||
b2fa47e6 | 829 | static inline void pud_clear(pud_t *pud) |
1da177e4 | 830 | { |
6252d702 MS |
831 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
832 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
833 | } |
834 | ||
b2fa47e6 | 835 | static inline void pmd_clear(pmd_t *pmdp) |
1da177e4 | 836 | { |
e5098611 | 837 | pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID; |
1da177e4 LT |
838 | } |
839 | ||
4448aaf0 | 840 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 841 | { |
e5098611 | 842 | pte_val(*ptep) = _PAGE_INVALID; |
1da177e4 LT |
843 | } |
844 | ||
845 | /* | |
846 | * The following pte modification functions only work if | |
847 | * pte_present() is true. Undefined behaviour if not.. | |
848 | */ | |
4448aaf0 | 849 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 850 | { |
138c9021 | 851 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 | 852 | pte_val(pte) |= pgprot_val(newprot); |
0944fe3f MS |
853 | /* |
854 | * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the | |
855 | * invalid bit set, clear it again for readable, young pages | |
856 | */ | |
857 | if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) | |
858 | pte_val(pte) &= ~_PAGE_INVALID; | |
859 | /* | |
860 | * newprot for PAGE_READ and PAGE_WRITE has the page protection | |
861 | * bit set, clear it again for writable, dirty pages | |
862 | */ | |
e5098611 MS |
863 | if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) |
864 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
865 | return pte; |
866 | } | |
867 | ||
4448aaf0 | 868 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 869 | { |
e5098611 MS |
870 | pte_val(pte) &= ~_PAGE_WRITE; |
871 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
872 | return pte; |
873 | } | |
874 | ||
4448aaf0 | 875 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 | 876 | { |
e5098611 MS |
877 | pte_val(pte) |= _PAGE_WRITE; |
878 | if (pte_val(pte) & _PAGE_DIRTY) | |
879 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
880 | return pte; |
881 | } | |
882 | ||
4448aaf0 | 883 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 | 884 | { |
e5098611 MS |
885 | pte_val(pte) &= ~_PAGE_DIRTY; |
886 | pte_val(pte) |= _PAGE_PROTECT; | |
1da177e4 LT |
887 | return pte; |
888 | } | |
889 | ||
4448aaf0 | 890 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 | 891 | { |
e5098611 MS |
892 | pte_val(pte) |= _PAGE_DIRTY; |
893 | if (pte_val(pte) & _PAGE_WRITE) | |
894 | pte_val(pte) &= ~_PAGE_PROTECT; | |
1da177e4 LT |
895 | return pte; |
896 | } | |
897 | ||
4448aaf0 | 898 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 | 899 | { |
e5098611 | 900 | pte_val(pte) &= ~_PAGE_YOUNG; |
0944fe3f | 901 | pte_val(pte) |= _PAGE_INVALID; |
1da177e4 LT |
902 | return pte; |
903 | } | |
904 | ||
4448aaf0 | 905 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 | 906 | { |
0944fe3f MS |
907 | pte_val(pte) |= _PAGE_YOUNG; |
908 | if (pte_val(pte) & _PAGE_READ) | |
909 | pte_val(pte) &= ~_PAGE_INVALID; | |
1da177e4 LT |
910 | return pte; |
911 | } | |
912 | ||
7e675137 NP |
913 | static inline pte_t pte_mkspecial(pte_t pte) |
914 | { | |
a08cb629 | 915 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
916 | return pte; |
917 | } | |
918 | ||
84afdcee HC |
919 | #ifdef CONFIG_HUGETLB_PAGE |
920 | static inline pte_t pte_mkhuge(pte_t pte) | |
921 | { | |
e5098611 | 922 | pte_val(pte) |= _PAGE_LARGE; |
84afdcee HC |
923 | return pte; |
924 | } | |
925 | #endif | |
926 | ||
9282ed92 | 927 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 928 | { |
53e857f3 MS |
929 | unsigned long pto = (unsigned long) ptep; |
930 | ||
53e857f3 MS |
931 | /* Invalidation + global TLB flush for the pte */ |
932 | asm volatile( | |
933 | " ipte %2,%3" | |
934 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
935 | } | |
936 | ||
1b948d6c MS |
937 | static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep) |
938 | { | |
939 | unsigned long pto = (unsigned long) ptep; | |
940 | ||
1b948d6c MS |
941 | /* Invalidation + local TLB flush for the pte */ |
942 | asm volatile( | |
943 | " .insn rrf,0xb2210000,%2,%3,0,1" | |
944 | : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address)); | |
945 | } | |
946 | ||
cfb0b241 HC |
947 | static inline void __ptep_ipte_range(unsigned long address, int nr, pte_t *ptep) |
948 | { | |
949 | unsigned long pto = (unsigned long) ptep; | |
950 | ||
cfb0b241 HC |
951 | /* Invalidate a range of ptes + global TLB flush of the ptes */ |
952 | do { | |
953 | asm volatile( | |
954 | " .insn rrf,0xb2210000,%2,%0,%1,0" | |
955 | : "+a" (address), "+a" (nr) : "a" (pto) : "memory"); | |
956 | } while (nr != 255); | |
957 | } | |
958 | ||
53e857f3 MS |
959 | static inline void ptep_flush_direct(struct mm_struct *mm, |
960 | unsigned long address, pte_t *ptep) | |
961 | { | |
1b948d6c MS |
962 | int active, count; |
963 | ||
53e857f3 MS |
964 | if (pte_val(*ptep) & _PAGE_INVALID) |
965 | return; | |
1b948d6c MS |
966 | active = (mm == current->active_mm) ? 1 : 0; |
967 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
968 | if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && | |
969 | cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) | |
970 | __ptep_ipte_local(address, ptep); | |
971 | else | |
972 | __ptep_ipte(address, ptep); | |
973 | atomic_sub(0x10000, &mm->context.attach_count); | |
9282ed92 GS |
974 | } |
975 | ||
5c474a1e MS |
976 | static inline void ptep_flush_lazy(struct mm_struct *mm, |
977 | unsigned long address, pte_t *ptep) | |
978 | { | |
53e857f3 | 979 | int active, count; |
5c474a1e | 980 | |
53e857f3 MS |
981 | if (pte_val(*ptep) & _PAGE_INVALID) |
982 | return; | |
983 | active = (mm == current->active_mm) ? 1 : 0; | |
984 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
985 | if ((count & 0xffff) <= active) { | |
986 | pte_val(*ptep) |= _PAGE_INVALID; | |
5c474a1e | 987 | mm->context.flush_mm = 1; |
53e857f3 MS |
988 | } else |
989 | __ptep_ipte(address, ptep); | |
990 | atomic_sub(0x10000, &mm->context.attach_count); | |
5c474a1e MS |
991 | } |
992 | ||
0a61b222 MS |
993 | /* |
994 | * Get (and clear) the user dirty bit for a pte. | |
995 | */ | |
996 | static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, | |
997 | unsigned long addr, | |
998 | pte_t *ptep) | |
999 | { | |
1000 | pgste_t pgste; | |
1001 | pte_t pte; | |
1002 | int dirty; | |
1003 | ||
1004 | if (!mm_has_pgste(mm)) | |
1005 | return 0; | |
1006 | pgste = pgste_get_lock(ptep); | |
1007 | dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT); | |
1008 | pgste_val(pgste) &= ~PGSTE_UC_BIT; | |
1009 | pte = *ptep; | |
1010 | if (dirty && (pte_val(pte) & _PAGE_PRESENT)) { | |
55dbbdd9 | 1011 | pgste = pgste_ipte_notify(mm, addr, ptep, pgste); |
0a61b222 MS |
1012 | __ptep_ipte(addr, ptep); |
1013 | if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE)) | |
1014 | pte_val(pte) |= _PAGE_PROTECT; | |
1015 | else | |
1016 | pte_val(pte) |= _PAGE_INVALID; | |
1017 | *ptep = pte; | |
1018 | } | |
1019 | pgste_set_unlock(ptep, pgste); | |
1020 | return dirty; | |
1021 | } | |
1022 | ||
0944fe3f MS |
1023 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
1024 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
1025 | unsigned long addr, pte_t *ptep) | |
1026 | { | |
1027 | pgste_t pgste; | |
3e03d4c4 | 1028 | pte_t pte, oldpte; |
0944fe3f MS |
1029 | int young; |
1030 | ||
1031 | if (mm_has_pgste(vma->vm_mm)) { | |
1032 | pgste = pgste_get_lock(ptep); | |
55dbbdd9 | 1033 | pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste); |
0944fe3f MS |
1034 | } |
1035 | ||
3e03d4c4 | 1036 | oldpte = pte = *ptep; |
53e857f3 | 1037 | ptep_flush_direct(vma->vm_mm, addr, ptep); |
0944fe3f MS |
1038 | young = pte_young(pte); |
1039 | pte = pte_mkold(pte); | |
1040 | ||
1041 | if (mm_has_pgste(vma->vm_mm)) { | |
3e03d4c4 | 1042 | pgste = pgste_update_all(&oldpte, pgste, vma->vm_mm); |
0a61b222 | 1043 | pgste = pgste_set_pte(ptep, pgste, pte); |
0944fe3f MS |
1044 | pgste_set_unlock(ptep, pgste); |
1045 | } else | |
1046 | *ptep = pte; | |
1047 | ||
1048 | return young; | |
1049 | } | |
1050 | ||
1051 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
1052 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
1053 | unsigned long address, pte_t *ptep) | |
1054 | { | |
1055 | return ptep_test_and_clear_young(vma, address, ptep); | |
1056 | } | |
1057 | ||
ba8a9229 MS |
1058 | /* |
1059 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
1060 | * both clear the TLB for the unmapped pte. The reason is that | |
1061 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
1062 | * to modify an active pte. The sequence is | |
1063 | * 1) ptep_get_and_clear | |
1064 | * 2) set_pte_at | |
1065 | * 3) flush_tlb_range | |
1066 | * On s390 the tlb needs to get flushed with the modification of the pte | |
1067 | * if the pte is active. The only way how this can be implemented is to | |
1068 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
1069 | * is a nop. | |
1070 | */ | |
1071 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
b2fa47e6 MS |
1072 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
1073 | unsigned long address, pte_t *ptep) | |
1074 | { | |
1075 | pgste_t pgste; | |
1076 | pte_t pte; | |
1077 | ||
d3383632 | 1078 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1079 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1080 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1081 | } |
b2fa47e6 MS |
1082 | |
1083 | pte = *ptep; | |
5c474a1e | 1084 | ptep_flush_lazy(mm, address, ptep); |
e5098611 | 1085 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 MS |
1086 | |
1087 | if (mm_has_pgste(mm)) { | |
65eef335 | 1088 | pgste = pgste_update_all(&pte, pgste, mm); |
b2fa47e6 MS |
1089 | pgste_set_unlock(ptep, pgste); |
1090 | } | |
1091 | return pte; | |
1092 | } | |
1093 | ||
1094 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
1095 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, | |
1096 | unsigned long address, | |
1097 | pte_t *ptep) | |
1098 | { | |
d3383632 | 1099 | pgste_t pgste; |
b2fa47e6 MS |
1100 | pte_t pte; |
1101 | ||
d3383632 MS |
1102 | if (mm_has_pgste(mm)) { |
1103 | pgste = pgste_get_lock(ptep); | |
55dbbdd9 | 1104 | pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1105 | } |
b2fa47e6 MS |
1106 | |
1107 | pte = *ptep; | |
5c474a1e | 1108 | ptep_flush_lazy(mm, address, ptep); |
b56433cb | 1109 | |
3a82603b | 1110 | if (mm_has_pgste(mm)) { |
65eef335 | 1111 | pgste = pgste_update_all(&pte, pgste, mm); |
3a82603b CB |
1112 | pgste_set(ptep, pgste); |
1113 | } | |
b2fa47e6 MS |
1114 | return pte; |
1115 | } | |
1116 | ||
1117 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, | |
1118 | unsigned long address, | |
1119 | pte_t *ptep, pte_t pte) | |
1120 | { | |
b56433cb CB |
1121 | pgste_t pgste; |
1122 | ||
abf09bed | 1123 | if (mm_has_pgste(mm)) { |
d56c893d | 1124 | pgste = pgste_get(ptep); |
65eef335 | 1125 | pgste_set_key(ptep, pgste, pte, mm); |
0a61b222 | 1126 | pgste = pgste_set_pte(ptep, pgste, pte); |
b56433cb | 1127 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1128 | } else |
1129 | *ptep = pte; | |
b2fa47e6 | 1130 | } |
ba8a9229 MS |
1131 | |
1132 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
1133 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
1134 | unsigned long address, pte_t *ptep) | |
1135 | { | |
b2fa47e6 MS |
1136 | pgste_t pgste; |
1137 | pte_t pte; | |
1138 | ||
d3383632 | 1139 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1140 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1141 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
d3383632 | 1142 | } |
b2fa47e6 MS |
1143 | |
1144 | pte = *ptep; | |
53e857f3 | 1145 | ptep_flush_direct(vma->vm_mm, address, ptep); |
e5098611 | 1146 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 MS |
1147 | |
1148 | if (mm_has_pgste(vma->vm_mm)) { | |
b31288fa KW |
1149 | if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) == |
1150 | _PGSTE_GPS_USAGE_UNUSED) | |
1151 | pte_val(pte) |= _PAGE_UNUSED; | |
65eef335 | 1152 | pgste = pgste_update_all(&pte, pgste, vma->vm_mm); |
b2fa47e6 MS |
1153 | pgste_set_unlock(ptep, pgste); |
1154 | } | |
1da177e4 LT |
1155 | return pte; |
1156 | } | |
1157 | ||
ba8a9229 MS |
1158 | /* |
1159 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
1160 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
1161 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
1162 | * cannot be accessed while the batched unmap is running. In this case | |
1163 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
1164 | */ | |
1165 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
1166 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
b2fa47e6 | 1167 | unsigned long address, |
ba8a9229 | 1168 | pte_t *ptep, int full) |
1da177e4 | 1169 | { |
b2fa47e6 MS |
1170 | pgste_t pgste; |
1171 | pte_t pte; | |
1172 | ||
a055f66a | 1173 | if (!full && mm_has_pgste(mm)) { |
b2fa47e6 | 1174 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1175 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1176 | } |
ba8a9229 | 1177 | |
b2fa47e6 MS |
1178 | pte = *ptep; |
1179 | if (!full) | |
5c474a1e | 1180 | ptep_flush_lazy(mm, address, ptep); |
e5098611 | 1181 | pte_val(*ptep) = _PAGE_INVALID; |
b2fa47e6 | 1182 | |
a055f66a | 1183 | if (!full && mm_has_pgste(mm)) { |
65eef335 | 1184 | pgste = pgste_update_all(&pte, pgste, mm); |
b2fa47e6 MS |
1185 | pgste_set_unlock(ptep, pgste); |
1186 | } | |
ba8a9229 | 1187 | return pte; |
1da177e4 LT |
1188 | } |
1189 | ||
ba8a9229 | 1190 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
b2fa47e6 MS |
1191 | static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, |
1192 | unsigned long address, pte_t *ptep) | |
1193 | { | |
1194 | pgste_t pgste; | |
1195 | pte_t pte = *ptep; | |
1196 | ||
1197 | if (pte_write(pte)) { | |
d3383632 | 1198 | if (mm_has_pgste(mm)) { |
b2fa47e6 | 1199 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1200 | pgste = pgste_ipte_notify(mm, address, ptep, pgste); |
d3383632 | 1201 | } |
b2fa47e6 | 1202 | |
5c474a1e | 1203 | ptep_flush_lazy(mm, address, ptep); |
abf09bed | 1204 | pte = pte_wrprotect(pte); |
b2fa47e6 | 1205 | |
abf09bed | 1206 | if (mm_has_pgste(mm)) { |
0a61b222 | 1207 | pgste = pgste_set_pte(ptep, pgste, pte); |
b2fa47e6 | 1208 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1209 | } else |
1210 | *ptep = pte; | |
b2fa47e6 MS |
1211 | } |
1212 | return pte; | |
1213 | } | |
ba8a9229 MS |
1214 | |
1215 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
b2fa47e6 MS |
1216 | static inline int ptep_set_access_flags(struct vm_area_struct *vma, |
1217 | unsigned long address, pte_t *ptep, | |
1218 | pte_t entry, int dirty) | |
1219 | { | |
1220 | pgste_t pgste; | |
1221 | ||
1222 | if (pte_same(*ptep, entry)) | |
1223 | return 0; | |
d3383632 | 1224 | if (mm_has_pgste(vma->vm_mm)) { |
b2fa47e6 | 1225 | pgste = pgste_get_lock(ptep); |
55dbbdd9 | 1226 | pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); |
d3383632 | 1227 | } |
b2fa47e6 | 1228 | |
53e857f3 | 1229 | ptep_flush_direct(vma->vm_mm, address, ptep); |
b2fa47e6 | 1230 | |
abf09bed | 1231 | if (mm_has_pgste(vma->vm_mm)) { |
1951497d | 1232 | pgste_set_key(ptep, pgste, entry, vma->vm_mm); |
0a61b222 | 1233 | pgste = pgste_set_pte(ptep, pgste, entry); |
b2fa47e6 | 1234 | pgste_set_unlock(ptep, pgste); |
abf09bed MS |
1235 | } else |
1236 | *ptep = entry; | |
b2fa47e6 MS |
1237 | return 1; |
1238 | } | |
1da177e4 | 1239 | |
1da177e4 LT |
1240 | /* |
1241 | * Conversion functions: convert a page and protection to a page entry, | |
1242 | * and a page entry and page directory to the page they refer to. | |
1243 | */ | |
1244 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1245 | { | |
1246 | pte_t __pte; | |
1247 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
0944fe3f | 1248 | return pte_mkyoung(__pte); |
1da177e4 LT |
1249 | } |
1250 | ||
2dcea57a HC |
1251 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1252 | { | |
0b2b6e1d | 1253 | unsigned long physpage = page_to_phys(page); |
abf09bed | 1254 | pte_t __pte = mk_pte_phys(physpage, pgprot); |
1da177e4 | 1255 | |
e5098611 MS |
1256 | if (pte_write(__pte) && PageDirty(page)) |
1257 | __pte = pte_mkdirty(__pte); | |
abf09bed | 1258 | return __pte; |
2dcea57a HC |
1259 | } |
1260 | ||
190a1d72 MS |
1261 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1262 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
1263 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1264 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1265 | |
190a1d72 MS |
1266 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1267 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1268 | |
190a1d72 MS |
1269 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1270 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 1271 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1272 | |
5a216a20 MS |
1273 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
1274 | { | |
6252d702 MS |
1275 | pud_t *pud = (pud_t *) pgd; |
1276 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1277 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
1278 | return pud + pud_index(address); |
1279 | } | |
1da177e4 | 1280 | |
190a1d72 | 1281 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1282 | { |
6252d702 MS |
1283 | pmd_t *pmd = (pmd_t *) pud; |
1284 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
1285 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1286 | return pmd + pmd_index(address); |
1da177e4 LT |
1287 | } |
1288 | ||
190a1d72 MS |
1289 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1290 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1291 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1292 | |
152125b7 | 1293 | #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) |
1da177e4 | 1294 | |
190a1d72 MS |
1295 | /* Find an entry in the lowest level page table.. */ |
1296 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1297 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 | 1298 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1da177e4 | 1299 | #define pte_unmap(pte) do { } while (0) |
1da177e4 | 1300 | |
106c992a | 1301 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) |
1ae1c1d0 GS |
1302 | static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) |
1303 | { | |
d8e7a33d | 1304 | /* |
e5098611 | 1305 | * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx) |
d8e7a33d GS |
1306 | * Convert to segment table entry format. |
1307 | */ | |
1308 | if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) | |
1309 | return pgprot_val(SEGMENT_NONE); | |
e5098611 MS |
1310 | if (pgprot_val(pgprot) == pgprot_val(PAGE_READ)) |
1311 | return pgprot_val(SEGMENT_READ); | |
1312 | return pgprot_val(SEGMENT_WRITE); | |
1ae1c1d0 GS |
1313 | } |
1314 | ||
152125b7 | 1315 | static inline pmd_t pmd_wrprotect(pmd_t pmd) |
0944fe3f | 1316 | { |
152125b7 MS |
1317 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE; |
1318 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1319 | return pmd; | |
1320 | } | |
1321 | ||
1322 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
1323 | { | |
1324 | pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE; | |
1325 | if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1326 | return pmd; | |
1327 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1328 | return pmd; | |
1329 | } | |
1330 | ||
1331 | static inline pmd_t pmd_mkclean(pmd_t pmd) | |
1332 | { | |
1333 | if (pmd_large(pmd)) { | |
1334 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY; | |
0944fe3f | 1335 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; |
152125b7 MS |
1336 | } |
1337 | return pmd; | |
1338 | } | |
1339 | ||
1340 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
1341 | { | |
1342 | if (pmd_large(pmd)) { | |
1343 | pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY; | |
1344 | if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) | |
1345 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT; | |
1346 | } | |
1347 | return pmd; | |
1348 | } | |
1349 | ||
1350 | static inline pmd_t pmd_mkyoung(pmd_t pmd) | |
1351 | { | |
1352 | if (pmd_large(pmd)) { | |
0944fe3f | 1353 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
152125b7 MS |
1354 | if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) |
1355 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID; | |
0944fe3f | 1356 | } |
0944fe3f MS |
1357 | return pmd; |
1358 | } | |
1359 | ||
1360 | static inline pmd_t pmd_mkold(pmd_t pmd) | |
1361 | { | |
152125b7 | 1362 | if (pmd_large(pmd)) { |
0944fe3f MS |
1363 | pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG; |
1364 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1365 | } | |
0944fe3f MS |
1366 | return pmd; |
1367 | } | |
1368 | ||
1ae1c1d0 GS |
1369 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
1370 | { | |
152125b7 MS |
1371 | if (pmd_large(pmd)) { |
1372 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE | | |
1373 | _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG | | |
1374 | _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SPLIT; | |
1375 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); | |
1376 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) | |
1377 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1378 | if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) | |
1379 | pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID; | |
1380 | return pmd; | |
1381 | } | |
1382 | pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN; | |
1ae1c1d0 GS |
1383 | pmd_val(pmd) |= massage_pgprot_pmd(newprot); |
1384 | return pmd; | |
1385 | } | |
1386 | ||
106c992a | 1387 | static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) |
1ae1c1d0 | 1388 | { |
106c992a GS |
1389 | pmd_t __pmd; |
1390 | pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); | |
152125b7 | 1391 | return __pmd; |
1ae1c1d0 GS |
1392 | } |
1393 | ||
106c992a GS |
1394 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ |
1395 | ||
1b948d6c MS |
1396 | static inline void __pmdp_csp(pmd_t *pmdp) |
1397 | { | |
1398 | register unsigned long reg2 asm("2") = pmd_val(*pmdp); | |
1399 | register unsigned long reg3 asm("3") = pmd_val(*pmdp) | | |
1400 | _SEGMENT_ENTRY_INVALID; | |
1401 | register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5; | |
1402 | ||
1403 | asm volatile( | |
1404 | " csp %1,%3" | |
1405 | : "=m" (*pmdp) | |
1406 | : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc"); | |
1407 | } | |
1408 | ||
1409 | static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp) | |
1410 | { | |
1411 | unsigned long sto; | |
1412 | ||
1413 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1414 | asm volatile( | |
1415 | " .insn rrf,0xb98e0000,%2,%3,0,0" | |
1416 | : "=m" (*pmdp) | |
1417 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1418 | : "cc" ); | |
1419 | } | |
1420 | ||
1421 | static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp) | |
1422 | { | |
1423 | unsigned long sto; | |
1424 | ||
1425 | sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t); | |
1426 | asm volatile( | |
1427 | " .insn rrf,0xb98e0000,%2,%3,0,1" | |
1428 | : "=m" (*pmdp) | |
1429 | : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK)) | |
1430 | : "cc" ); | |
1431 | } | |
1432 | ||
1433 | static inline void pmdp_flush_direct(struct mm_struct *mm, | |
1434 | unsigned long address, pmd_t *pmdp) | |
1435 | { | |
1436 | int active, count; | |
1437 | ||
1438 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) | |
1439 | return; | |
1440 | if (!MACHINE_HAS_IDTE) { | |
1441 | __pmdp_csp(pmdp); | |
1442 | return; | |
1443 | } | |
1444 | active = (mm == current->active_mm) ? 1 : 0; | |
1445 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1446 | if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active && | |
1447 | cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) | |
1448 | __pmdp_idte_local(address, pmdp); | |
1449 | else | |
1450 | __pmdp_idte(address, pmdp); | |
1451 | atomic_sub(0x10000, &mm->context.attach_count); | |
1452 | } | |
1453 | ||
3eabaee9 MS |
1454 | static inline void pmdp_flush_lazy(struct mm_struct *mm, |
1455 | unsigned long address, pmd_t *pmdp) | |
1456 | { | |
53e857f3 | 1457 | int active, count; |
3eabaee9 | 1458 | |
1b948d6c MS |
1459 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) |
1460 | return; | |
53e857f3 MS |
1461 | active = (mm == current->active_mm) ? 1 : 0; |
1462 | count = atomic_add_return(0x10000, &mm->context.attach_count); | |
1463 | if ((count & 0xffff) <= active) { | |
1464 | pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID; | |
3eabaee9 | 1465 | mm->context.flush_mm = 1; |
1b948d6c MS |
1466 | } else if (MACHINE_HAS_IDTE) |
1467 | __pmdp_idte(address, pmdp); | |
1468 | else | |
1469 | __pmdp_csp(pmdp); | |
53e857f3 | 1470 | atomic_sub(0x10000, &mm->context.attach_count); |
3eabaee9 MS |
1471 | } |
1472 | ||
106c992a GS |
1473 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1474 | ||
1475 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
6b0b50b0 AK |
1476 | extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
1477 | pgtable_t pgtable); | |
106c992a GS |
1478 | |
1479 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
6b0b50b0 | 1480 | extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
106c992a GS |
1481 | |
1482 | static inline int pmd_trans_splitting(pmd_t pmd) | |
1483 | { | |
152125b7 MS |
1484 | return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) && |
1485 | (pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT); | |
106c992a GS |
1486 | } |
1487 | ||
1488 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1489 | pmd_t *pmdp, pmd_t entry) | |
1490 | { | |
106c992a GS |
1491 | *pmdp = entry; |
1492 | } | |
1493 | ||
1494 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1495 | { | |
1496 | pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; | |
152125b7 MS |
1497 | pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG; |
1498 | pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT; | |
1ae1c1d0 GS |
1499 | return pmd; |
1500 | } | |
1501 | ||
1ae1c1d0 GS |
1502 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1503 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1504 | unsigned long address, pmd_t *pmdp) | |
1505 | { | |
0944fe3f | 1506 | pmd_t pmd; |
1ae1c1d0 | 1507 | |
0944fe3f | 1508 | pmd = *pmdp; |
1b948d6c | 1509 | pmdp_flush_direct(vma->vm_mm, address, pmdp); |
0944fe3f MS |
1510 | *pmdp = pmd_mkold(pmd); |
1511 | return pmd_young(pmd); | |
1ae1c1d0 GS |
1512 | } |
1513 | ||
8809aa2d AK |
1514 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
1515 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
1516 | unsigned long address, pmd_t *pmdp) | |
1ae1c1d0 GS |
1517 | { |
1518 | pmd_t pmd = *pmdp; | |
1519 | ||
1b948d6c | 1520 | pmdp_flush_direct(mm, address, pmdp); |
1ae1c1d0 GS |
1521 | pmd_clear(pmdp); |
1522 | return pmd; | |
1523 | } | |
1524 | ||
8809aa2d AK |
1525 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1526 | static inline pmd_t pmdp_huge_get_and_clear_full(struct mm_struct *mm, | |
1527 | unsigned long address, | |
1528 | pmd_t *pmdp, int full) | |
fcbe08d6 MS |
1529 | { |
1530 | pmd_t pmd = *pmdp; | |
1531 | ||
1532 | if (!full) | |
1533 | pmdp_flush_lazy(mm, address, pmdp); | |
1534 | pmd_clear(pmdp); | |
1535 | return pmd; | |
1536 | } | |
1537 | ||
8809aa2d AK |
1538 | #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH |
1539 | static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, | |
1540 | unsigned long address, pmd_t *pmdp) | |
1ae1c1d0 | 1541 | { |
8809aa2d | 1542 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
1ae1c1d0 GS |
1543 | } |
1544 | ||
1545 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1546 | static inline void pmdp_invalidate(struct vm_area_struct *vma, | |
1547 | unsigned long address, pmd_t *pmdp) | |
1548 | { | |
1b948d6c | 1549 | pmdp_flush_direct(vma->vm_mm, address, pmdp); |
1ae1c1d0 GS |
1550 | } |
1551 | ||
be328650 GS |
1552 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1553 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
1554 | unsigned long address, pmd_t *pmdp) | |
1555 | { | |
1556 | pmd_t pmd = *pmdp; | |
1557 | ||
1558 | if (pmd_write(pmd)) { | |
1b948d6c | 1559 | pmdp_flush_direct(mm, address, pmdp); |
be328650 GS |
1560 | set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); |
1561 | } | |
1562 | } | |
1563 | ||
f28b6ff8 AK |
1564 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1565 | unsigned long address, | |
1566 | pmd_t *pmdp) | |
1567 | { | |
8809aa2d | 1568 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
f28b6ff8 AK |
1569 | } |
1570 | #define pmdp_collapse_flush pmdp_collapse_flush | |
1571 | ||
1ae1c1d0 GS |
1572 | #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) |
1573 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) | |
1574 | ||
1575 | static inline int pmd_trans_huge(pmd_t pmd) | |
1576 | { | |
1577 | return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; | |
1578 | } | |
1579 | ||
1580 | static inline int has_transparent_hugepage(void) | |
1581 | { | |
1582 | return MACHINE_HAS_HPAGE ? 1 : 0; | |
1583 | } | |
75077afb GS |
1584 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1585 | ||
1da177e4 | 1586 | /* |
1da177e4 LT |
1587 | * 64 bit swap entry format: |
1588 | * A page-table entry has some bits we have to treat in a special way. | |
4e0a6412 | 1589 | * Bits 52 and bit 55 have to be zero, otherwise a specification |
1da177e4 | 1590 | * exception will occur instead of a page translation exception. The |
4e0a6412 | 1591 | * specification exception has the bad habit not to store necessary |
1da177e4 | 1592 | * information in the lowcore. |
a1c843b8 MS |
1593 | * Bits 54 and 63 are used to indicate the page type. |
1594 | * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 | |
1595 | * This leaves the bits 0-51 and bits 56-62 to store type and offset. | |
1596 | * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 | |
1597 | * for the offset. | |
1598 | * | offset |01100|type |00| | |
1599 | * |0000000000111111111122222222223333333333444444444455|55555|55566|66| | |
1600 | * |0123456789012345678901234567890123456789012345678901|23456|78901|23| | |
1da177e4 | 1601 | */ |
5a79859a | 1602 | |
a1c843b8 MS |
1603 | #define __SWP_OFFSET_MASK ((1UL << 52) - 1) |
1604 | #define __SWP_OFFSET_SHIFT 12 | |
1605 | #define __SWP_TYPE_MASK ((1UL << 5) - 1) | |
1606 | #define __SWP_TYPE_SHIFT 2 | |
5a79859a | 1607 | |
4448aaf0 | 1608 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1609 | { |
1610 | pte_t pte; | |
a1c843b8 MS |
1611 | |
1612 | pte_val(pte) = _PAGE_INVALID | _PAGE_PROTECT; | |
1613 | pte_val(pte) |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; | |
1614 | pte_val(pte) |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; | |
1da177e4 LT |
1615 | return pte; |
1616 | } | |
1617 | ||
a1c843b8 MS |
1618 | static inline unsigned long __swp_type(swp_entry_t entry) |
1619 | { | |
1620 | return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; | |
1621 | } | |
1622 | ||
1623 | static inline unsigned long __swp_offset(swp_entry_t entry) | |
1624 | { | |
1625 | return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; | |
1626 | } | |
1627 | ||
1628 | static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) | |
1629 | { | |
1630 | return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; | |
1631 | } | |
1da177e4 LT |
1632 | |
1633 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1634 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1635 | ||
1da177e4 LT |
1636 | #endif /* !__ASSEMBLY__ */ |
1637 | ||
1638 | #define kern_addr_valid(addr) (1) | |
1639 | ||
17f34580 HC |
1640 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1641 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1642 | extern int s390_enable_sie(void); |
3ac8e380 | 1643 | extern int s390_enable_skey(void); |
a13cff31 | 1644 | extern void s390_reset_cmma(struct mm_struct *mm); |
f4eb07c1 | 1645 | |
1f6b83e5 MS |
1646 | /* s390 has a private copy of get unmapped area to deal with cache synonyms */ |
1647 | #define HAVE_ARCH_UNMAPPED_AREA | |
1648 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
1649 | ||
1da177e4 LT |
1650 | /* |
1651 | * No page table caches to initialise | |
1652 | */ | |
765a0cac HC |
1653 | static inline void pgtable_cache_init(void) { } |
1654 | static inline void check_pgt_cache(void) { } | |
1da177e4 | 1655 | |
1da177e4 LT |
1656 | #include <asm-generic/pgtable.h> |
1657 | ||
1658 | #endif /* _S390_PAGE_H */ |