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s390: update default configuration
[deliverable/linux.git] / arch / s390 / include / asm / pgtable.h
CommitLineData
1da177e4 1/*
1da177e4 2 * S390 version
a53c8fab 3 * Copyright IBM Corp. 1999, 2000
1da177e4
LT		 4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11#ifndef _ASM_S390_PGTABLE_H
12#define _ASM_S390_PGTABLE_H
13
1da177e4
LT		 14/*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29#ifndef __ASSEMBLY__
9789db08 30#include <linux/sched.h>
2dcea57a 31#include <linux/mm_types.h>
abf09bed 32#include <linux/page-flags.h>
527e30b4 33#include <linux/radix-tree.h>
1da177e4 34#include <asm/bug.h>
b2fa47e6 35#include <asm/page.h>
1da177e4 36
1da177e4
LT		 37extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
38extern void paging_init(void);
2b67fc46 39extern void vmem_map_init(void);
1da177e4
LT		 40
41/*
42 * The S390 doesn't have any external MMU info: the kernel page
43 * tables contain all the necessary information.
44 */
4b3073e1 45#define update_mmu_cache(vma, address, ptep) do { } while (0)
b113da65 46#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
1da177e4
LT		 47
48/*
238ec4ef 49 * ZERO_PAGE is a global shared page that is always zero; used
1da177e4
LT		 50 * for zero-mapped memory areas etc..
51 */
238ec4ef
MS		 52
53extern unsigned long empty_zero_page;
54extern unsigned long zero_page_mask;
55
56#define ZERO_PAGE(vaddr) \
57 (virt_to_page((void *)(empty_zero_page + \
58 (((unsigned long)(vaddr)) &zero_page_mask))))
816422ad 59#define __HAVE_COLOR_ZERO_PAGE
238ec4ef 60
4f2e2903 61/* TODO: s390 cannot support io_remap_pfn_range... */
1da177e4
LT		 62#endif /* !__ASSEMBLY__ */
63
64/*
65 * PMD_SHIFT determines the size of the area a second-level page
66 * table can map
67 * PGDIR_SHIFT determines what a third-level page table entry can map
68 */
f4815ac6 69#ifndef CONFIG_64BIT
146e4b3c
MS		 70# define PMD_SHIFT 20
71# define PUD_SHIFT 20
72# define PGDIR_SHIFT 20
f4815ac6 73#else /* CONFIG_64BIT */
146e4b3c 74# define PMD_SHIFT 20
190a1d72 75# define PUD_SHIFT 31
5a216a20 76# define PGDIR_SHIFT 42
f4815ac6 77#endif /* CONFIG_64BIT */
1da177e4
LT		 78
79#define PMD_SIZE (1UL << PMD_SHIFT)
80#define PMD_MASK (~(PMD_SIZE-1))
190a1d72
MS		 81#define PUD_SIZE (1UL << PUD_SHIFT)
82#define PUD_MASK (~(PUD_SIZE-1))
5a216a20
MS		 83#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
84#define PGDIR_MASK (~(PGDIR_SIZE-1))
1da177e4
LT		 85
86/*
87 * entries per page directory level: the S390 is two-level, so
88 * we don't really have any PMD directory physically.
89 * for S390 segment-table entries are combined to one PGD
90 * that leads to 1024 pte per pgd
91 */
146e4b3c 92#define PTRS_PER_PTE 256
f4815ac6 93#ifndef CONFIG_64BIT
146e4b3c 94#define PTRS_PER_PMD 1
5a216a20 95#define PTRS_PER_PUD 1
f4815ac6 96#else /* CONFIG_64BIT */
146e4b3c 97#define PTRS_PER_PMD 2048
5a216a20 98#define PTRS_PER_PUD 2048
f4815ac6 99#endif /* CONFIG_64BIT */
146e4b3c 100#define PTRS_PER_PGD 2048
1da177e4 101
d455a369
HD		 102#define FIRST_USER_ADDRESS 0
103
1da177e4
LT		 104#define pte_ERROR(e) \
105 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
106#define pmd_ERROR(e) \
107 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
190a1d72
MS		 108#define pud_ERROR(e) \
109 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
1da177e4
LT		 110#define pgd_ERROR(e) \
111 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
112
113#ifndef __ASSEMBLY__
114/*
c972cc60
HC		 115 * The vmalloc and module area will always be on the topmost area of the kernel
116 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
117 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
118 * modules will reside. That makes sure that inter module branches always
119 * happen without trampolines and in addition the placement within a 2GB frame
120 * is branch prediction unit friendly.
8b62bc96 121 */
239a6425 122extern unsigned long VMALLOC_START;
14045ebf
MS		 123extern unsigned long VMALLOC_END;
124extern struct page *vmemmap;
239a6425 125
14045ebf 126#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
5fd9c6e2 127
c972cc60
HC		 128#ifdef CONFIG_64BIT
129extern unsigned long MODULES_VADDR;
130extern unsigned long MODULES_END;
131#define MODULES_VADDR MODULES_VADDR
132#define MODULES_END MODULES_END
133#define MODULES_LEN (1UL << 31)
134#endif
135
1da177e4
LT		 136/*
137 * A 31 bit pagetable entry of S390 has following format:
138 * | PFRA | | OS |
139 * 0 0IP0
140 * 00000000001111111111222222222233
141 * 01234567890123456789012345678901
142 *
143 * I Page-Invalid Bit: Page is not available for address-translation
144 * P Page-Protection Bit: Store access not possible for page
145 *
146 * A 31 bit segmenttable entry of S390 has following format:
147 * | P-table origin | |PTL
148 * 0 IC
149 * 00000000001111111111222222222233
150 * 01234567890123456789012345678901
151 *
152 * I Segment-Invalid Bit: Segment is not available for address-translation
153 * C Common-Segment Bit: Segment is not private (PoP 3-30)
154 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
155 *
156 * The 31 bit segmenttable origin of S390 has following format:
157 *
158 * |S-table origin | | STL |
159 * X **GPS
160 * 00000000001111111111222222222233
161 * 01234567890123456789012345678901
162 *
163 * X Space-Switch event:
164 * G Segment-Invalid Bit: *
165 * P Private-Space Bit: Segment is not private (PoP 3-30)
166 * S Storage-Alteration:
167 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
168 *
169 * A 64 bit pagetable entry of S390 has following format:
6a985c61 170 * | PFRA |0IPC| OS |
1da177e4
LT		 171 * 0000000000111111111122222222223333333333444444444455555555556666
172 * 0123456789012345678901234567890123456789012345678901234567890123
173 *
174 * I Page-Invalid Bit: Page is not available for address-translation
175 * P Page-Protection Bit: Store access not possible for page
6a985c61 176 * C Change-bit override: HW is not required to set change bit
1da177e4
LT		 177 *
178 * A 64 bit segmenttable entry of S390 has following format:
179 * | P-table origin | TT
180 * 0000000000111111111122222222223333333333444444444455555555556666
181 * 0123456789012345678901234567890123456789012345678901234567890123
182 *
183 * I Segment-Invalid Bit: Segment is not available for address-translation
184 * C Common-Segment Bit: Segment is not private (PoP 3-30)
185 * P Page-Protection Bit: Store access not possible for page
186 * TT Type 00
187 *
188 * A 64 bit region table entry of S390 has following format:
189 * | S-table origin | TF TTTL
190 * 0000000000111111111122222222223333333333444444444455555555556666
191 * 0123456789012345678901234567890123456789012345678901234567890123
192 *
193 * I Segment-Invalid Bit: Segment is not available for address-translation
194 * TT Type 01
195 * TF
190a1d72 196 * TL Table length
1da177e4
LT		 197 *
198 * The 64 bit regiontable origin of S390 has following format:
199 * | region table origon | DTTL
200 * 0000000000111111111122222222223333333333444444444455555555556666
201 * 0123456789012345678901234567890123456789012345678901234567890123
202 *
203 * X Space-Switch event:
204 * G Segment-Invalid Bit:
205 * P Private-Space Bit:
206 * S Storage-Alteration:
207 * R Real space
208 * TL Table-Length:
209 *
210 * A storage key has the following format:
211 * | ACC |F|R|C|0|
212 * 0 3 4 5 6 7
213 * ACC: access key
214 * F : fetch protection bit
215 * R : referenced bit
216 * C : changed bit
217 */
218
219/* Hardware bits in the page table entry */
e5098611 220#define _PAGE_PROTECT 0x200 /* HW read-only bit */
83377484 221#define _PAGE_INVALID 0x400 /* HW invalid bit */
e5098611 222#define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
3610cce8
MS		 223
224/* Software bits in the page table entry */
e5098611
MS		 225#define _PAGE_PRESENT 0x001 /* SW pte present bit */
226#define _PAGE_TYPE 0x002 /* SW pte type bit */
227#define _PAGE_YOUNG 0x004 /* SW pte young bit */
228#define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
0944fe3f
MS		 229#define _PAGE_READ 0x010 /* SW pte read bit */
230#define _PAGE_WRITE 0x020 /* SW pte write bit */
231#define _PAGE_SPECIAL 0x040 /* SW associated with special page */
b31288fa 232#define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
a08cb629 233#define __HAVE_ARCH_PTE_SPECIAL
1da177e4 234
138c9021 235/* Set of bits not changed in pte_modify */
6a5c1482
HC		 236#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \
237 _PAGE_YOUNG)
53492b1d 238
83377484 239/*
e5098611
MS		 240 * handle_pte_fault uses pte_present, pte_none and pte_file to find out the
241 * pte type WITHOUT holding the page table lock. The _PAGE_PRESENT bit
242 * is used to distinguish present from not-present ptes. It is changed only
243 * with the page table lock held.
83377484 244 *
e5098611
MS		 245 * The following table gives the different possible bit combinations for
246 * the pte hardware and software bits in the last 12 bits of a pte:
83377484 247 *
0944fe3f
MS		 248 * 842100000000
249 * 000084210000
250 * 000000008421
251 * .IR...wrdytp
252 * empty .10...000000
253 * swap .10...xxxx10
254 * file .11...xxxxx0
255 * prot-none, clean, old .11...000001
256 * prot-none, clean, young .11...000101
257 * prot-none, dirty, old .10...001001
258 * prot-none, dirty, young .10...001101
259 * read-only, clean, old .11...010001
260 * read-only, clean, young .01...010101
261 * read-only, dirty, old .11...011001
262 * read-only, dirty, young .01...011101
263 * read-write, clean, old .11...110001
264 * read-write, clean, young .01...110101
265 * read-write, dirty, old .10...111001
266 * read-write, dirty, young .00...111101
e5098611
MS		 267 *
268 * pte_present is true for the bit pattern .xx...xxxxx1, (pte & 0x001) == 0x001
269 * pte_none is true for the bit pattern .10...xxxx00, (pte & 0x603) == 0x400
270 * pte_file is true for the bit pattern .11...xxxxx0, (pte & 0x601) == 0x600
271 * pte_swap is true for the bit pattern .10...xxxx10, (pte & 0x603) == 0x402
83377484
MS		 272 */
273
f4815ac6 274#ifndef CONFIG_64BIT
1da177e4 275
3610cce8
MS		 276/* Bits in the segment table address-space-control-element */
277#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
278#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
279#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
280#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
281#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
1da177e4 282
3610cce8 283/* Bits in the segment table entry */
0944fe3f 284#define _SEGMENT_ENTRY_BITS 0x7fffffffUL /* Valid segment table bits */
3610cce8 285#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
e5098611
MS		 286#define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
287#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
3610cce8
MS		 288#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
289#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
152125b7
MS		 290
291#define _SEGMENT_ENTRY_DIRTY 0 /* No sw dirty bit for 31-bit */
292#define _SEGMENT_ENTRY_YOUNG 0 /* No sw young bit for 31-bit */
293#define _SEGMENT_ENTRY_READ 0 /* No sw read bit for 31-bit */
294#define _SEGMENT_ENTRY_WRITE 0 /* No sw write bit for 31-bit */
295#define _SEGMENT_ENTRY_LARGE 0 /* No large pages for 31-bit */
296#define _SEGMENT_ENTRY_BITS_LARGE 0
297#define _SEGMENT_ENTRY_ORIGIN_LARGE 0
1da177e4 298
3610cce8 299#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
e5098611 300#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
1da177e4 301
0944fe3f
MS		 302/*
303 * Segment table entry encoding (I = invalid, R = read-only bit):
304 * ..R...I.....
305 * prot-none ..1...1.....
306 * read-only ..1...0.....
307 * read-write ..0...0.....
308 * empty ..0...1.....
309 */
310
6c61cfe9 311/* Page status table bits for virtualization */
0d0dafc1
MS		 312#define PGSTE_ACC_BITS 0xf0000000UL
313#define PGSTE_FP_BIT 0x08000000UL
314#define PGSTE_PCL_BIT 0x00800000UL
315#define PGSTE_HR_BIT 0x00400000UL
316#define PGSTE_HC_BIT 0x00200000UL
317#define PGSTE_GR_BIT 0x00040000UL
318#define PGSTE_GC_BIT 0x00020000UL
0a61b222
MS		 319#define PGSTE_UC_BIT 0x00008000UL /* user dirty (migration) */
320#define PGSTE_IN_BIT 0x00004000UL /* IPTE notify bit */
6c61cfe9 321
f4815ac6 322#else /* CONFIG_64BIT */
1da177e4 323
3610cce8
MS		 324/* Bits in the segment/region table address-space-control-element */
325#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
326#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
327#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
328#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
329#define _ASCE_REAL_SPACE 0x20 /* real space control */
330#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
331#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
332#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
333#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
334#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
335#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
336
337/* Bits in the region table entry */
338#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
e5098611
MS		 339#define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
340#define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
3610cce8
MS		 341#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
342#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
343#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
344#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
345#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
346
347#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
e5098611 348#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
3610cce8 349#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
e5098611 350#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
3610cce8 351#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
e5098611 352#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
3610cce8 353
18da2369 354#define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
1819ed1f 355#define _REGION3_ENTRY_RO 0x200 /* page protection bit */
18da2369 356
1da177e4 357/* Bits in the segment table entry */
0944fe3f 358#define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL
152125b7 359#define _SEGMENT_ENTRY_BITS_LARGE 0xfffffffffff0ff33UL
ea81531d 360#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
3610cce8 361#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
e5098611
MS		 362#define _SEGMENT_ENTRY_PROTECT 0x200 /* page protection bit */
363#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
1da177e4 364
3610cce8 365#define _SEGMENT_ENTRY (0)
e5098611 366#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
3610cce8 367
152125b7
MS		 368#define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */
369#define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */
370#define _SEGMENT_ENTRY_SPLIT 0x0800 /* THP splitting bit */
371#define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */
152125b7
MS		 372#define _SEGMENT_ENTRY_READ 0x0002 /* SW segment read bit */
373#define _SEGMENT_ENTRY_WRITE 0x0001 /* SW segment write bit */
0944fe3f
MS		 374
375/*
376 * Segment table entry encoding (R = read-only, I = invalid, y = young bit):
152125b7
MS		 377 * dy..R...I...wr
378 * prot-none, clean, old 00..1...1...00
379 * prot-none, clean, young 01..1...1...00
380 * prot-none, dirty, old 10..1...1...00
381 * prot-none, dirty, young 11..1...1...00
382 * read-only, clean, old 00..1...1...01
383 * read-only, clean, young 01..1...0...01
384 * read-only, dirty, old 10..1...1...01
385 * read-only, dirty, young 11..1...0...01
386 * read-write, clean, old 00..1...1...11
387 * read-write, clean, young 01..1...0...11
388 * read-write, dirty, old 10..0...1...11
389 * read-write, dirty, young 11..0...0...11
0944fe3f
MS		 390 * The segment table origin is used to distinguish empty (origin==0) from
391 * read-write, old segment table entries (origin!=0)
392 */
e5098611 393
152125b7 394#define _SEGMENT_ENTRY_SPLIT_BIT 11 /* THP splitting bit number */
1ae1c1d0 395
6c61cfe9 396/* Page status table bits for virtualization */
0d0dafc1
MS		 397#define PGSTE_ACC_BITS 0xf000000000000000UL
398#define PGSTE_FP_BIT 0x0800000000000000UL
399#define PGSTE_PCL_BIT 0x0080000000000000UL
400#define PGSTE_HR_BIT 0x0040000000000000UL
401#define PGSTE_HC_BIT 0x0020000000000000UL
402#define PGSTE_GR_BIT 0x0004000000000000UL
403#define PGSTE_GC_BIT 0x0002000000000000UL
0a61b222
MS		 404#define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */
405#define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */
6c61cfe9 406
f4815ac6 407#endif /* CONFIG_64BIT */
1da177e4 408
b31288fa
KW		 409/* Guest Page State used for virtualization */
410#define _PGSTE_GPS_ZERO 0x0000000080000000UL
411#define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL
412#define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL
413#define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL
414
1da177e4 415/*
3610cce8
MS		 416 * A user page table pointer has the space-switch-event bit, the
417 * private-space-control bit and the storage-alteration-event-control
418 * bit set. A kernel page table pointer doesn't need them.
1da177e4 419 */
3610cce8
MS		 420#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
421 _ASCE_ALT_EVENT)
1da177e4 422
1da177e4 423/*
9282ed92 424 * Page protection definitions.
1da177e4 425 */
e5098611 426#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID)
0944fe3f
MS		 427#define PAGE_READ __pgprot(_PAGE_PRESENT | _PAGE_READ | \
428 _PAGE_INVALID | _PAGE_PROTECT)
429#define PAGE_WRITE __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
430 _PAGE_INVALID | _PAGE_PROTECT)
431
432#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
433 _PAGE_YOUNG | _PAGE_DIRTY)
434#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
435 _PAGE_YOUNG | _PAGE_DIRTY)
436#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
437 _PAGE_PROTECT)
1da177e4
LT		 438
439/*
043d0708
MS		 440 * On s390 the page table entry has an invalid bit and a read-only bit.
441 * Read permission implies execute permission and write permission
442 * implies read permission.
1da177e4
LT		 443 */
444 /*xwr*/
9282ed92 445#define __P000 PAGE_NONE
e5098611
MS		 446#define __P001 PAGE_READ
447#define __P010 PAGE_READ
448#define __P011 PAGE_READ
449#define __P100 PAGE_READ
450#define __P101 PAGE_READ
451#define __P110 PAGE_READ
452#define __P111 PAGE_READ
9282ed92
GS		 453
454#define __S000 PAGE_NONE
e5098611
MS		 455#define __S001 PAGE_READ
456#define __S010 PAGE_WRITE
457#define __S011 PAGE_WRITE
458#define __S100 PAGE_READ
459#define __S101 PAGE_READ
460#define __S110 PAGE_WRITE
461#define __S111 PAGE_WRITE
1da177e4 462
106c992a
GS		 463/*
464 * Segment entry (large page) protection definitions.
465 */
e5098611
MS		 466#define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
467 _SEGMENT_ENTRY_PROTECT)
152125b7
MS		 468#define SEGMENT_READ __pgprot(_SEGMENT_ENTRY_PROTECT | \
469 _SEGMENT_ENTRY_READ)
470#define SEGMENT_WRITE __pgprot(_SEGMENT_ENTRY_READ | \
471 _SEGMENT_ENTRY_WRITE)
106c992a 472
b2fa47e6
MS		 473static inline int mm_has_pgste(struct mm_struct *mm)
474{
475#ifdef CONFIG_PGSTE
476 if (unlikely(mm->context.has_pgste))
477 return 1;
478#endif
479 return 0;
480}
65eef335
DD		 481
482static inline int mm_use_skey(struct mm_struct *mm)
483{
484#ifdef CONFIG_PGSTE
485 if (mm->context.use_skey)
486 return 1;
487#endif
488 return 0;
489}
490
1da177e4
LT		 491/*
492 * pgd/pmd/pte query functions
493 */
f4815ac6 494#ifndef CONFIG_64BIT
1da177e4 495
4448aaf0
AB		 496static inline int pgd_present(pgd_t pgd) { return 1; }
497static inline int pgd_none(pgd_t pgd) { return 0; }
498static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 499
190a1d72
MS		 500static inline int pud_present(pud_t pud) { return 1; }
501static inline int pud_none(pud_t pud) { return 0; }
18da2369 502static inline int pud_large(pud_t pud) { return 0; }
190a1d72
MS		 503static inline int pud_bad(pud_t pud) { return 0; }
504
f4815ac6 505#else /* CONFIG_64BIT */
1da177e4 506
5a216a20
MS		 507static inline int pgd_present(pgd_t pgd)
508{
6252d702
MS		 509 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
510 return 1;
5a216a20
MS		 511 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
512}
513
514static inline int pgd_none(pgd_t pgd)
515{
6252d702
MS		 516 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
517 return 0;
e5098611 518 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
5a216a20
MS		 519}
520
521static inline int pgd_bad(pgd_t pgd)
522{
6252d702
MS		 523 /*
524 * With dynamic page table levels the pgd can be a region table
525 * entry or a segment table entry. Check for the bit that are
526 * invalid for either table entry.
527 */
5a216a20 528 unsigned long mask =
e5098611 529 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
5a216a20
MS		 530 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
531 return (pgd_val(pgd) & mask) != 0;
532}
190a1d72
MS		 533
534static inline int pud_present(pud_t pud)
1da177e4 535{
6252d702
MS		 536 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
537 return 1;
0d017923 538 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 539}
540
190a1d72 541static inline int pud_none(pud_t pud)
1da177e4 542{
6252d702
MS		 543 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
544 return 0;
e5098611 545 return (pud_val(pud) & _REGION_ENTRY_INVALID) != 0UL;
1da177e4
LT		 546}
547
18da2369
HC		 548static inline int pud_large(pud_t pud)
549{
550 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
551 return 0;
552 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
553}
554
190a1d72 555static inline int pud_bad(pud_t pud)
1da177e4 556{
6252d702
MS		 557 /*
558 * With dynamic page table levels the pud can be a region table
559 * entry or a segment table entry. Check for the bit that are
560 * invalid for either table entry.
561 */
5a216a20 562 unsigned long mask =
e5098611 563 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INVALID &
5a216a20
MS		 564 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
565 return (pud_val(pud) & mask) != 0;
1da177e4
LT		 566}
567
f4815ac6 568#endif /* CONFIG_64BIT */
3610cce8 569
4448aaf0 570static inline int pmd_present(pmd_t pmd)
1da177e4 571{
e5098611 572 return pmd_val(pmd) != _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 573}
574
4448aaf0 575static inline int pmd_none(pmd_t pmd)
1da177e4 576{
e5098611 577 return pmd_val(pmd) == _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 578}
579
378b1e7a
HC		 580static inline int pmd_large(pmd_t pmd)
581{
e5098611 582 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
378b1e7a
HC		 583}
584
152125b7 585static inline int pmd_pfn(pmd_t pmd)
0944fe3f 586{
152125b7
MS		 587 unsigned long origin_mask;
588
589 origin_mask = _SEGMENT_ENTRY_ORIGIN;
590 if (pmd_large(pmd))
591 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
592 return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT;
0944fe3f
MS		 593}
594
4448aaf0 595static inline int pmd_bad(pmd_t pmd)
1da177e4 596{
0944fe3f
MS		 597 if (pmd_large(pmd))
598 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS_LARGE) != 0;
0944fe3f 599 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
1da177e4
LT		 600}
601
75077afb
GS		 602#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
603extern void pmdp_splitting_flush(struct vm_area_struct *vma,
604 unsigned long addr, pmd_t *pmdp);
605
1ae1c1d0
GS		 606#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
607extern int pmdp_set_access_flags(struct vm_area_struct *vma,
608 unsigned long address, pmd_t *pmdp,
609 pmd_t entry, int dirty);
610
611#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
612extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
613 unsigned long address, pmd_t *pmdp);
614
615#define __HAVE_ARCH_PMD_WRITE
616static inline int pmd_write(pmd_t pmd)
617{
152125b7
MS		 618 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0;
619}
620
621static inline int pmd_dirty(pmd_t pmd)
622{
623 int dirty = 1;
624 if (pmd_large(pmd))
625 dirty = (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0;
626 return dirty;
1ae1c1d0
GS		 627}
628
629static inline int pmd_young(pmd_t pmd)
630{
152125b7
MS		 631 int young = 1;
632 if (pmd_large(pmd))
0944fe3f 633 young = (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
0944fe3f 634 return young;
1ae1c1d0
GS		 635}
636
e5098611 637static inline int pte_present(pte_t pte)
1da177e4 638{
e5098611
MS		 639 /* Bit pattern: (pte & 0x001) == 0x001 */
640 return (pte_val(pte) & _PAGE_PRESENT) != 0;
1da177e4
LT		 641}
642
e5098611 643static inline int pte_none(pte_t pte)
1da177e4 644{
e5098611
MS		 645 /* Bit pattern: pte == 0x400 */
646 return pte_val(pte) == _PAGE_INVALID;
1da177e4
LT		 647}
648
b31288fa
KW		 649static inline int pte_swap(pte_t pte)
650{
651 /* Bit pattern: (pte & 0x603) == 0x402 */
652 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT |
653 _PAGE_TYPE | _PAGE_PRESENT))
654 == (_PAGE_INVALID | _PAGE_TYPE);
655}
656
4448aaf0 657static inline int pte_file(pte_t pte)
1da177e4 658{
e5098611
MS		 659 /* Bit pattern: (pte & 0x601) == 0x600 */
660 return (pte_val(pte) & (_PAGE_INVALID | _PAGE_PROTECT | _PAGE_PRESENT))
661 == (_PAGE_INVALID | _PAGE_PROTECT);
1da177e4
LT		 662}
663
7e675137
NP		 664static inline int pte_special(pte_t pte)
665{
a08cb629 666 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 667}
668
ba8a9229 669#define __HAVE_ARCH_PTE_SAME
b2fa47e6
MS		 670static inline int pte_same(pte_t a, pte_t b)
671{
672 return pte_val(a) == pte_val(b);
673}
1da177e4 674
b2fa47e6 675static inline pgste_t pgste_get_lock(pte_t *ptep)
5b7baf05 676{
b2fa47e6 677 unsigned long new = 0;
5b7baf05 678#ifdef CONFIG_PGSTE
b2fa47e6
MS		 679 unsigned long old;
680
5b7baf05 681 preempt_disable();
b2fa47e6
MS		 682 asm(
683 " lg %0,%2\n"
684 "0: lgr %1,%0\n"
0d0dafc1
MS		 685 " nihh %0,0xff7f\n" /* clear PCL bit in old */
686 " oihh %1,0x0080\n" /* set PCL bit in new */
b2fa47e6
MS		 687 " csg %0,%1,%2\n"
688 " jl 0b\n"
689 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
a8f6e7f7 690 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
5b7baf05 691#endif
b2fa47e6 692 return __pgste(new);
5b7baf05
CB		 693}
694
b2fa47e6 695static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 696{
697#ifdef CONFIG_PGSTE
b2fa47e6 698 asm(
0d0dafc1 699 " nihh %1,0xff7f\n" /* clear PCL bit */
b2fa47e6
MS		 700 " stg %1,%0\n"
701 : "=Q" (ptep[PTRS_PER_PTE])
a8f6e7f7
CB		 702 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
703 : "cc", "memory");
5b7baf05
CB		 704 preempt_enable();
705#endif
706}
707
d56c893d
MS		 708static inline pgste_t pgste_get(pte_t *ptep)
709{
710 unsigned long pgste = 0;
711#ifdef CONFIG_PGSTE
712 pgste = *(unsigned long *)(ptep + PTRS_PER_PTE);
713#endif
714 return __pgste(pgste);
715}
716
3a82603b
CB		 717static inline void pgste_set(pte_t *ptep, pgste_t pgste)
718{
719#ifdef CONFIG_PGSTE
720 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
721#endif
722}
723
65eef335
DD		 724static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste,
725 struct mm_struct *mm)
5b7baf05
CB		 726{
727#ifdef CONFIG_PGSTE
0944fe3f 728 unsigned long address, bits, skey;
b2fa47e6 729
65eef335 730 if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID)
09b53883 731 return pgste;
a43a9d93 732 address = pte_val(*ptep) & PAGE_MASK;
0944fe3f 733 skey = (unsigned long) page_get_storage_key(address);
b2fa47e6 734 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
b2fa47e6 735 /* Transfer page changed & referenced bit to guest bits in pgste */
0d0dafc1 736 pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */
b2fa47e6 737 /* Copy page access key and fetch protection bit to pgste */
0944fe3f
MS		 738 pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
739 pgste_val(pgste) |= (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
b2fa47e6
MS		 740#endif
741 return pgste;
742
743}
744
65eef335
DD		 745static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry,
746 struct mm_struct *mm)
b2fa47e6
MS		 747{
748#ifdef CONFIG_PGSTE
a43a9d93 749 unsigned long address;
338679f7 750 unsigned long nkey;
b2fa47e6 751
65eef335 752 if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID)
09b53883 753 return;
338679f7 754 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
09b53883 755 address = pte_val(entry) & PAGE_MASK;
338679f7
CB		 756 /*
757 * Set page access key and fetch protection bit from pgste.
758 * The guest C/R information is still in the PGSTE, set real
759 * key C/R to 0.
760 */
fe489bf4 761 nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
0a61b222 762 nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48;
338679f7 763 page_set_storage_key(address, nkey, 0);
5b7baf05
CB		 764#endif
765}
766
0a61b222 767static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry)
abf09bed 768{
0a61b222
MS		 769 if ((pte_val(entry) & _PAGE_PRESENT) &&
770 (pte_val(entry) & _PAGE_WRITE) &&
771 !(pte_val(entry) & _PAGE_INVALID)) {
772 if (!MACHINE_HAS_ESOP) {
773 /*
774 * Without enhanced suppression-on-protection force
775 * the dirty bit on for all writable ptes.
776 */
777 pte_val(entry) |= _PAGE_DIRTY;
778 pte_val(entry) &= ~_PAGE_PROTECT;
779 }
780 if (!(pte_val(entry) & _PAGE_PROTECT))
781 /* This pte allows write access, set user-dirty */
782 pgste_val(pgste) |= PGSTE_UC_BIT;
abf09bed
MS		 783 }
784 *ptep = entry;
0a61b222 785 return pgste;
abf09bed
MS		 786}
787
e5992f2e
MS		 788/**
789 * struct gmap_struct - guest address space
527e30b4 790 * @crst_list: list of all crst tables used in the guest address space
e5992f2e 791 * @mm: pointer to the parent mm_struct
527e30b4
MS		 792 * @guest_to_host: radix tree with guest to host address translation
793 * @host_to_guest: radix tree with pointer to segment table entries
794 * @guest_table_lock: spinlock to protect all entries in the guest page table
e5992f2e 795 * @table: pointer to the page directory
480e5926 796 * @asce: address space control element for gmap page table
24eb3a82 797 * @pfault_enabled: defines if pfaults are applicable for the guest
e5992f2e
MS		 798 */
799struct gmap {
800 struct list_head list;
527e30b4 801 struct list_head crst_list;
e5992f2e 802 struct mm_struct *mm;
527e30b4
MS		 803 struct radix_tree_root guest_to_host;
804 struct radix_tree_root host_to_guest;
805 spinlock_t guest_table_lock;
e5992f2e 806 unsigned long *table;
480e5926 807 unsigned long asce;
c6c956b8 808 unsigned long asce_end;
2c70fe44 809 void *private;
24eb3a82 810 bool pfault_enabled;
e5992f2e
MS		 811};
812
d3383632
MS		 813/**
814 * struct gmap_notifier - notify function block for page invalidation
815 * @notifier_call: address of callback function
816 */
817struct gmap_notifier {
818 struct list_head list;
6e0a0431 819 void (*notifier_call)(struct gmap *gmap, unsigned long gaddr);
d3383632
MS		 820};
821
c6c956b8 822struct gmap *gmap_alloc(struct mm_struct *mm, unsigned long limit);
e5992f2e
MS		 823void gmap_free(struct gmap *gmap);
824void gmap_enable(struct gmap *gmap);
825void gmap_disable(struct gmap *gmap);
826int gmap_map_segment(struct gmap *gmap, unsigned long from,
d3383632 827 unsigned long to, unsigned long len);
e5992f2e 828int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
6e0a0431
MS		 829unsigned long __gmap_translate(struct gmap *, unsigned long gaddr);
830unsigned long gmap_translate(struct gmap *, unsigned long gaddr);
527e30b4
MS		 831int __gmap_link(struct gmap *gmap, unsigned long gaddr, unsigned long vmaddr);
832int gmap_fault(struct gmap *, unsigned long gaddr, unsigned int fault_flags);
6e0a0431
MS		 833void gmap_discard(struct gmap *, unsigned long from, unsigned long to);
834void __gmap_zap(struct gmap *, unsigned long gaddr);
a0bf4f14
DD		 835bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *);
836
e5992f2e 837
d3383632
MS		 838void gmap_register_ipte_notifier(struct gmap_notifier *);
839void gmap_unregister_ipte_notifier(struct gmap_notifier *);
840int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
9da4e380 841void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);
d3383632
MS		 842
843static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
55dbbdd9 844 unsigned long addr,
d3383632
MS		 845 pte_t *ptep, pgste_t pgste)
846{
847#ifdef CONFIG_PGSTE
0d0dafc1
MS		 848 if (pgste_val(pgste) & PGSTE_IN_BIT) {
849 pgste_val(pgste) &= ~PGSTE_IN_BIT;
9da4e380 850 gmap_do_ipte_notify(mm, addr, ptep);
d3383632
MS		 851 }
852#endif
853 return pgste;
854}
855
b2fa47e6
MS		 856/*
857 * Certain architectures need to do special things when PTEs
858 * within a page table are directly modified. Thus, the following
859 * hook is made available.
860 */
861static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
862 pte_t *ptep, pte_t entry)
863{
864 pgste_t pgste;
865
866 if (mm_has_pgste(mm)) {
867 pgste = pgste_get_lock(ptep);
b31288fa 868 pgste_val(pgste) &= ~_PGSTE_GPS_ZERO;
65eef335 869 pgste_set_key(ptep, pgste, entry, mm);
0a61b222 870 pgste = pgste_set_pte(ptep, pgste, entry);
b2fa47e6 871 pgste_set_unlock(ptep, pgste);
abf09bed 872 } else {
b2fa47e6 873 *ptep = entry;
abf09bed 874 }
b2fa47e6
MS		 875}
876
1da177e4
LT		 877/*
878 * query functions pte_write/pte_dirty/pte_young only work if
879 * pte_present() is true. Undefined behaviour if not..
880 */
4448aaf0 881static inline int pte_write(pte_t pte)
1da177e4 882{
e5098611 883 return (pte_val(pte) & _PAGE_WRITE) != 0;
1da177e4
LT		 884}
885
4448aaf0 886static inline int pte_dirty(pte_t pte)
1da177e4 887{
e5098611 888 return (pte_val(pte) & _PAGE_DIRTY) != 0;
1da177e4
LT		 889}
890
4448aaf0 891static inline int pte_young(pte_t pte)
1da177e4 892{
0944fe3f 893 return (pte_val(pte) & _PAGE_YOUNG) != 0;
1da177e4
LT		 894}
895
b31288fa
KW		 896#define __HAVE_ARCH_PTE_UNUSED
897static inline int pte_unused(pte_t pte)
898{
899 return pte_val(pte) & _PAGE_UNUSED;
900}
901
1da177e4
LT		 902/*
903 * pgd/pmd/pte modification functions
904 */
905
b2fa47e6 906static inline void pgd_clear(pgd_t *pgd)
5a216a20 907{
f4815ac6 908#ifdef CONFIG_64BIT
6252d702
MS		 909 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
910 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
b2fa47e6 911#endif
5a216a20
MS		 912}
913
b2fa47e6 914static inline void pud_clear(pud_t *pud)
1da177e4 915{
f4815ac6 916#ifdef CONFIG_64BIT
6252d702
MS		 917 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
918 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
b2fa47e6 919#endif
1da177e4
LT		 920}
921
b2fa47e6 922static inline void pmd_clear(pmd_t *pmdp)
1da177e4 923{
e5098611 924 pmd_val(*pmdp) = _SEGMENT_ENTRY_INVALID;
1da177e4
LT		 925}
926
4448aaf0 927static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 928{
e5098611 929 pte_val(*ptep) = _PAGE_INVALID;
1da177e4
LT		 930}
931
932/*
933 * The following pte modification functions only work if
934 * pte_present() is true. Undefined behaviour if not..
935 */
4448aaf0 936static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 937{
138c9021 938 pte_val(pte) &= _PAGE_CHG_MASK;
1da177e4 939 pte_val(pte) |= pgprot_val(newprot);
0944fe3f
MS		 940 /*
941 * newprot for PAGE_NONE, PAGE_READ and PAGE_WRITE has the
942 * invalid bit set, clear it again for readable, young pages
943 */
944 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
945 pte_val(pte) &= ~_PAGE_INVALID;
946 /*
947 * newprot for PAGE_READ and PAGE_WRITE has the page protection
948 * bit set, clear it again for writable, dirty pages
949 */
e5098611
MS		 950 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
951 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 952 return pte;
953}
954
4448aaf0 955static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 956{
e5098611
MS		 957 pte_val(pte) &= ~_PAGE_WRITE;
958 pte_val(pte) |= _PAGE_PROTECT;
1da177e4
LT		 959 return pte;
960}
961
4448aaf0 962static inline pte_t pte_mkwrite(pte_t pte)
1da177e4 963{
e5098611
MS		 964 pte_val(pte) |= _PAGE_WRITE;
965 if (pte_val(pte) & _PAGE_DIRTY)
966 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 967 return pte;
968}
969
4448aaf0 970static inline pte_t pte_mkclean(pte_t pte)
1da177e4 971{
e5098611
MS		 972 pte_val(pte) &= ~_PAGE_DIRTY;
973 pte_val(pte) |= _PAGE_PROTECT;
1da177e4
LT		 974 return pte;
975}
976
4448aaf0 977static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 978{
e5098611
MS		 979 pte_val(pte) |= _PAGE_DIRTY;
980 if (pte_val(pte) & _PAGE_WRITE)
981 pte_val(pte) &= ~_PAGE_PROTECT;
1da177e4
LT		 982 return pte;
983}
984
4448aaf0 985static inline pte_t pte_mkold(pte_t pte)
1da177e4 986{
e5098611 987 pte_val(pte) &= ~_PAGE_YOUNG;
0944fe3f 988 pte_val(pte) |= _PAGE_INVALID;
1da177e4
LT		 989 return pte;
990}
991
4448aaf0 992static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 993{
0944fe3f
MS		 994 pte_val(pte) |= _PAGE_YOUNG;
995 if (pte_val(pte) & _PAGE_READ)
996 pte_val(pte) &= ~_PAGE_INVALID;
1da177e4
LT		 997 return pte;
998}
999
7e675137
NP		 1000static inline pte_t pte_mkspecial(pte_t pte)
1001{
a08cb629 1002 pte_val(pte) |= _PAGE_SPECIAL;
7e675137
NP		 1003 return pte;
1004}
1005
84afdcee
HC		 1006#ifdef CONFIG_HUGETLB_PAGE
1007static inline pte_t pte_mkhuge(pte_t pte)
1008{
e5098611 1009 pte_val(pte) |= _PAGE_LARGE;
84afdcee
HC		 1010 return pte;
1011}
1012#endif
1013
9282ed92 1014static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 1015{
53e857f3
MS		 1016 unsigned long pto = (unsigned long) ptep;
1017
f4815ac6 1018#ifndef CONFIG_64BIT
53e857f3
MS		 1019 /* pto in ESA mode must point to the start of the segment table */
1020 pto &= 0x7ffffc00;
9282ed92 1021#endif
53e857f3
MS		 1022 /* Invalidation + global TLB flush for the pte */
1023 asm volatile(
1024 " ipte %2,%3"
1025 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
1026}
1027
1b948d6c
MS		 1028static inline void __ptep_ipte_local(unsigned long address, pte_t *ptep)
1029{
1030 unsigned long pto = (unsigned long) ptep;
1031
1032#ifndef CONFIG_64BIT
1033 /* pto in ESA mode must point to the start of the segment table */
1034 pto &= 0x7ffffc00;
1035#endif
1036 /* Invalidation + local TLB flush for the pte */
1037 asm volatile(
1038 " .insn rrf,0xb2210000,%2,%3,0,1"
1039 : "=m" (*ptep) : "m" (*ptep), "a" (pto), "a" (address));
1040}
1041
cfb0b241
HC		 1042static inline void __ptep_ipte_range(unsigned long address, int nr, pte_t *ptep)
1043{
1044 unsigned long pto = (unsigned long) ptep;
1045
1046#ifndef CONFIG_64BIT
1047 /* pto in ESA mode must point to the start of the segment table */
1048 pto &= 0x7ffffc00;
1049#endif
1050 /* Invalidate a range of ptes + global TLB flush of the ptes */
1051 do {
1052 asm volatile(
1053 " .insn rrf,0xb2210000,%2,%0,%1,0"
1054 : "+a" (address), "+a" (nr) : "a" (pto) : "memory");
1055 } while (nr != 255);
1056}
1057
53e857f3
MS		 1058static inline void ptep_flush_direct(struct mm_struct *mm,
1059 unsigned long address, pte_t *ptep)
1060{
1b948d6c
MS		 1061 int active, count;
1062
53e857f3
MS		 1063 if (pte_val(*ptep) & _PAGE_INVALID)
1064 return;
1b948d6c
MS		 1065 active = (mm == current->active_mm) ? 1 : 0;
1066 count = atomic_add_return(0x10000, &mm->context.attach_count);
1067 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
1068 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1069 __ptep_ipte_local(address, ptep);
1070 else
1071 __ptep_ipte(address, ptep);
1072 atomic_sub(0x10000, &mm->context.attach_count);
9282ed92
GS		 1073}
1074
5c474a1e
MS		 1075static inline void ptep_flush_lazy(struct mm_struct *mm,
1076 unsigned long address, pte_t *ptep)
1077{
53e857f3 1078 int active, count;
5c474a1e 1079
53e857f3
MS		 1080 if (pte_val(*ptep) & _PAGE_INVALID)
1081 return;
1082 active = (mm == current->active_mm) ? 1 : 0;
1083 count = atomic_add_return(0x10000, &mm->context.attach_count);
1084 if ((count & 0xffff) <= active) {
1085 pte_val(*ptep) |= _PAGE_INVALID;
5c474a1e 1086 mm->context.flush_mm = 1;
53e857f3
MS		 1087 } else
1088 __ptep_ipte(address, ptep);
1089 atomic_sub(0x10000, &mm->context.attach_count);
5c474a1e
MS		 1090}
1091
0a61b222
MS		 1092/*
1093 * Get (and clear) the user dirty bit for a pte.
1094 */
1095static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
1096 unsigned long addr,
1097 pte_t *ptep)
1098{
1099 pgste_t pgste;
1100 pte_t pte;
1101 int dirty;
1102
1103 if (!mm_has_pgste(mm))
1104 return 0;
1105 pgste = pgste_get_lock(ptep);
1106 dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT);
1107 pgste_val(pgste) &= ~PGSTE_UC_BIT;
1108 pte = *ptep;
1109 if (dirty && (pte_val(pte) & _PAGE_PRESENT)) {
55dbbdd9 1110 pgste = pgste_ipte_notify(mm, addr, ptep, pgste);
0a61b222
MS		 1111 __ptep_ipte(addr, ptep);
1112 if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE))
1113 pte_val(pte) |= _PAGE_PROTECT;
1114 else
1115 pte_val(pte) |= _PAGE_INVALID;
1116 *ptep = pte;
1117 }
1118 pgste_set_unlock(ptep, pgste);
1119 return dirty;
1120}
1121
0944fe3f
MS		 1122#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1123static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1124 unsigned long addr, pte_t *ptep)
1125{
1126 pgste_t pgste;
3e03d4c4 1127 pte_t pte, oldpte;
0944fe3f
MS		 1128 int young;
1129
1130 if (mm_has_pgste(vma->vm_mm)) {
1131 pgste = pgste_get_lock(ptep);
55dbbdd9 1132 pgste = pgste_ipte_notify(vma->vm_mm, addr, ptep, pgste);
0944fe3f
MS		 1133 }
1134
3e03d4c4 1135 oldpte = pte = *ptep;
53e857f3 1136 ptep_flush_direct(vma->vm_mm, addr, ptep);
0944fe3f
MS		 1137 young = pte_young(pte);
1138 pte = pte_mkold(pte);
1139
1140 if (mm_has_pgste(vma->vm_mm)) {
3e03d4c4 1141 pgste = pgste_update_all(&oldpte, pgste, vma->vm_mm);
0a61b222 1142 pgste = pgste_set_pte(ptep, pgste, pte);
0944fe3f
MS		 1143 pgste_set_unlock(ptep, pgste);
1144 } else
1145 *ptep = pte;
1146
1147 return young;
1148}
1149
1150#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1151static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1152 unsigned long address, pte_t *ptep)
1153{
1154 return ptep_test_and_clear_young(vma, address, ptep);
1155}
1156
ba8a9229
MS		 1157/*
1158 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1159 * both clear the TLB for the unmapped pte. The reason is that
1160 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1161 * to modify an active pte. The sequence is
1162 * 1) ptep_get_and_clear
1163 * 2) set_pte_at
1164 * 3) flush_tlb_range
1165 * On s390 the tlb needs to get flushed with the modification of the pte
1166 * if the pte is active. The only way how this can be implemented is to
1167 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1168 * is a nop.
1169 */
1170#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
b2fa47e6
MS		 1171static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1172 unsigned long address, pte_t *ptep)
1173{
1174 pgste_t pgste;
1175 pte_t pte;
1176
d3383632 1177 if (mm_has_pgste(mm)) {
b2fa47e6 1178 pgste = pgste_get_lock(ptep);
55dbbdd9 1179 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
d3383632 1180 }
b2fa47e6
MS		 1181
1182 pte = *ptep;
5c474a1e 1183 ptep_flush_lazy(mm, address, ptep);
e5098611 1184 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6
MS		 1185
1186 if (mm_has_pgste(mm)) {
65eef335 1187 pgste = pgste_update_all(&pte, pgste, mm);
b2fa47e6
MS		 1188 pgste_set_unlock(ptep, pgste);
1189 }
1190 return pte;
1191}
1192
1193#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1194static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1195 unsigned long address,
1196 pte_t *ptep)
1197{
d3383632 1198 pgste_t pgste;
b2fa47e6
MS		 1199 pte_t pte;
1200
d3383632
MS		 1201 if (mm_has_pgste(mm)) {
1202 pgste = pgste_get_lock(ptep);
55dbbdd9 1203 pgste_ipte_notify(mm, address, ptep, pgste);
d3383632 1204 }
b2fa47e6
MS		 1205
1206 pte = *ptep;
5c474a1e 1207 ptep_flush_lazy(mm, address, ptep);
b56433cb 1208
3a82603b 1209 if (mm_has_pgste(mm)) {
65eef335 1210 pgste = pgste_update_all(&pte, pgste, mm);
3a82603b
CB		 1211 pgste_set(ptep, pgste);
1212 }
b2fa47e6
MS		 1213 return pte;
1214}
1215
1216static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1217 unsigned long address,
1218 pte_t *ptep, pte_t pte)
1219{
b56433cb
CB		 1220 pgste_t pgste;
1221
abf09bed 1222 if (mm_has_pgste(mm)) {
d56c893d 1223 pgste = pgste_get(ptep);
65eef335 1224 pgste_set_key(ptep, pgste, pte, mm);
0a61b222 1225 pgste = pgste_set_pte(ptep, pgste, pte);
b56433cb 1226 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1227 } else
1228 *ptep = pte;
b2fa47e6 1229}
ba8a9229
MS		 1230
1231#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22
MS		 1232static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1233 unsigned long address, pte_t *ptep)
1234{
b2fa47e6
MS		 1235 pgste_t pgste;
1236 pte_t pte;
1237
d3383632 1238 if (mm_has_pgste(vma->vm_mm)) {
b2fa47e6 1239 pgste = pgste_get_lock(ptep);
55dbbdd9 1240 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
d3383632 1241 }
b2fa47e6
MS		 1242
1243 pte = *ptep;
53e857f3 1244 ptep_flush_direct(vma->vm_mm, address, ptep);
e5098611 1245 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6
MS		 1246
1247 if (mm_has_pgste(vma->vm_mm)) {
b31288fa
KW		 1248 if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) ==
1249 _PGSTE_GPS_USAGE_UNUSED)
1250 pte_val(pte) |= _PAGE_UNUSED;
65eef335 1251 pgste = pgste_update_all(&pte, pgste, vma->vm_mm);
b2fa47e6
MS		 1252 pgste_set_unlock(ptep, pgste);
1253 }
1da177e4
LT		 1254 return pte;
1255}
1256
ba8a9229
MS		 1257/*
1258 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1259 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1260 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1261 * cannot be accessed while the batched unmap is running. In this case
1262 * full==1 and a simple pte_clear is enough. See tlb.h.
1263 */
1264#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1265static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
b2fa47e6 1266 unsigned long address,
ba8a9229 1267 pte_t *ptep, int full)
1da177e4 1268{
b2fa47e6
MS		 1269 pgste_t pgste;
1270 pte_t pte;
1271
a055f66a 1272 if (!full && mm_has_pgste(mm)) {
b2fa47e6 1273 pgste = pgste_get_lock(ptep);
55dbbdd9 1274 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
d3383632 1275 }
ba8a9229 1276
b2fa47e6
MS		 1277 pte = *ptep;
1278 if (!full)
5c474a1e 1279 ptep_flush_lazy(mm, address, ptep);
e5098611 1280 pte_val(*ptep) = _PAGE_INVALID;
b2fa47e6 1281
a055f66a 1282 if (!full && mm_has_pgste(mm)) {
65eef335 1283 pgste = pgste_update_all(&pte, pgste, mm);
b2fa47e6
MS		 1284 pgste_set_unlock(ptep, pgste);
1285 }
ba8a9229 1286 return pte;
1da177e4
LT		 1287}
1288
ba8a9229 1289#define __HAVE_ARCH_PTEP_SET_WRPROTECT
b2fa47e6
MS		 1290static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1291 unsigned long address, pte_t *ptep)
1292{
1293 pgste_t pgste;
1294 pte_t pte = *ptep;
1295
1296 if (pte_write(pte)) {
d3383632 1297 if (mm_has_pgste(mm)) {
b2fa47e6 1298 pgste = pgste_get_lock(ptep);
55dbbdd9 1299 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
d3383632 1300 }
b2fa47e6 1301
5c474a1e 1302 ptep_flush_lazy(mm, address, ptep);
abf09bed 1303 pte = pte_wrprotect(pte);
b2fa47e6 1304
abf09bed 1305 if (mm_has_pgste(mm)) {
0a61b222 1306 pgste = pgste_set_pte(ptep, pgste, pte);
b2fa47e6 1307 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1308 } else
1309 *ptep = pte;
b2fa47e6
MS		 1310 }
1311 return pte;
1312}
ba8a9229
MS		 1313
1314#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
b2fa47e6
MS		 1315static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1316 unsigned long address, pte_t *ptep,
1317 pte_t entry, int dirty)
1318{
1319 pgste_t pgste;
1320
1321 if (pte_same(*ptep, entry))
1322 return 0;
d3383632 1323 if (mm_has_pgste(vma->vm_mm)) {
b2fa47e6 1324 pgste = pgste_get_lock(ptep);
55dbbdd9 1325 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
d3383632 1326 }
b2fa47e6 1327
53e857f3 1328 ptep_flush_direct(vma->vm_mm, address, ptep);
b2fa47e6 1329
abf09bed 1330 if (mm_has_pgste(vma->vm_mm)) {
1951497d 1331 pgste_set_key(ptep, pgste, entry, vma->vm_mm);
0a61b222 1332 pgste = pgste_set_pte(ptep, pgste, entry);
b2fa47e6 1333 pgste_set_unlock(ptep, pgste);
abf09bed
MS		 1334 } else
1335 *ptep = entry;
b2fa47e6
MS		 1336 return 1;
1337}
1da177e4 1338
1da177e4
LT		 1339/*
1340 * Conversion functions: convert a page and protection to a page entry,
1341 * and a page entry and page directory to the page they refer to.
1342 */
1343static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1344{
1345 pte_t __pte;
1346 pte_val(__pte) = physpage + pgprot_val(pgprot);
0944fe3f 1347 return pte_mkyoung(__pte);
1da177e4
LT		 1348}
1349
2dcea57a
HC		 1350static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1351{
0b2b6e1d 1352 unsigned long physpage = page_to_phys(page);
abf09bed 1353 pte_t __pte = mk_pte_phys(physpage, pgprot);
1da177e4 1354
e5098611
MS		 1355 if (pte_write(__pte) && PageDirty(page))
1356 __pte = pte_mkdirty(__pte);
abf09bed 1357 return __pte;
2dcea57a
HC		 1358}
1359
190a1d72
MS		 1360#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1361#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1362#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1363#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1da177e4 1364
190a1d72
MS		 1365#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1366#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4 1367
f4815ac6 1368#ifndef CONFIG_64BIT
1da177e4 1369
190a1d72
MS		 1370#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1371#define pud_deref(pmd) ({ BUG(); 0UL; })
1372#define pgd_deref(pmd) ({ BUG(); 0UL; })
46a82b2d 1373
190a1d72
MS		 1374#define pud_offset(pgd, address) ((pud_t *) pgd)
1375#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1da177e4 1376
f4815ac6 1377#else /* CONFIG_64BIT */
1da177e4 1378
190a1d72
MS		 1379#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1380#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
5a216a20 1381#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1da177e4 1382
5a216a20
MS		 1383static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1384{
6252d702
MS		 1385 pud_t *pud = (pud_t *) pgd;
1386 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1387 pud = (pud_t *) pgd_deref(*pgd);
5a216a20
MS		 1388 return pud + pud_index(address);
1389}
1da177e4 1390
190a1d72 1391static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1da177e4 1392{
6252d702
MS		 1393 pmd_t *pmd = (pmd_t *) pud;
1394 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1395 pmd = (pmd_t *) pud_deref(*pud);
190a1d72 1396 return pmd + pmd_index(address);
1da177e4
LT		 1397}
1398
f4815ac6 1399#endif /* CONFIG_64BIT */
1da177e4 1400
190a1d72
MS		 1401#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1402#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1403#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 1404
152125b7 1405#define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
1da177e4 1406
190a1d72
MS		 1407/* Find an entry in the lowest level page table.. */
1408#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1409#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1da177e4 1410#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1da177e4 1411#define pte_unmap(pte) do { } while (0)
1da177e4 1412
106c992a 1413#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1ae1c1d0
GS		 1414static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1415{
d8e7a33d 1416 /*
e5098611 1417 * pgprot is PAGE_NONE, PAGE_READ, or PAGE_WRITE (see __Pxxx / __Sxxx)
d8e7a33d
GS		 1418 * Convert to segment table entry format.
1419 */
1420 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1421 return pgprot_val(SEGMENT_NONE);
e5098611
MS		 1422 if (pgprot_val(pgprot) == pgprot_val(PAGE_READ))
1423 return pgprot_val(SEGMENT_READ);
1424 return pgprot_val(SEGMENT_WRITE);
1ae1c1d0
GS		 1425}
1426
152125b7 1427static inline pmd_t pmd_wrprotect(pmd_t pmd)
0944fe3f 1428{
152125b7
MS		 1429 pmd_val(pmd) &= ~_SEGMENT_ENTRY_WRITE;
1430 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1431 return pmd;
1432}
1433
1434static inline pmd_t pmd_mkwrite(pmd_t pmd)
1435{
1436 pmd_val(pmd) |= _SEGMENT_ENTRY_WRITE;
1437 if (pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
1438 return pmd;
1439 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1440 return pmd;
1441}
1442
1443static inline pmd_t pmd_mkclean(pmd_t pmd)
1444{
1445 if (pmd_large(pmd)) {
1446 pmd_val(pmd) &= ~_SEGMENT_ENTRY_DIRTY;
0944fe3f 1447 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
152125b7
MS		 1448 }
1449 return pmd;
1450}
1451
1452static inline pmd_t pmd_mkdirty(pmd_t pmd)
1453{
1454 if (pmd_large(pmd)) {
1455 pmd_val(pmd) |= _SEGMENT_ENTRY_DIRTY;
1456 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE)
1457 pmd_val(pmd) &= ~_SEGMENT_ENTRY_PROTECT;
1458 }
1459 return pmd;
1460}
1461
1462static inline pmd_t pmd_mkyoung(pmd_t pmd)
1463{
1464 if (pmd_large(pmd)) {
0944fe3f 1465 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
152125b7
MS		 1466 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ)
1467 pmd_val(pmd) &= ~_SEGMENT_ENTRY_INVALID;
0944fe3f 1468 }
0944fe3f
MS		 1469 return pmd;
1470}
1471
1472static inline pmd_t pmd_mkold(pmd_t pmd)
1473{
152125b7 1474 if (pmd_large(pmd)) {
0944fe3f
MS		 1475 pmd_val(pmd) &= ~_SEGMENT_ENTRY_YOUNG;
1476 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1477 }
0944fe3f
MS		 1478 return pmd;
1479}
1480
1ae1c1d0
GS		 1481static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1482{
152125b7
MS		 1483 if (pmd_large(pmd)) {
1484 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN_LARGE |
1485 _SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_YOUNG |
1486 _SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_SPLIT;
1487 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1488 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
1489 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1490 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG))
1491 pmd_val(pmd) |= _SEGMENT_ENTRY_INVALID;
1492 return pmd;
1493 }
1494 pmd_val(pmd) &= _SEGMENT_ENTRY_ORIGIN;
1ae1c1d0
GS		 1495 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1496 return pmd;
1497}
1498
106c992a 1499static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1ae1c1d0 1500{
106c992a
GS		 1501 pmd_t __pmd;
1502 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
152125b7 1503 return __pmd;
1ae1c1d0
GS		 1504}
1505
106c992a
GS		 1506#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1507
1b948d6c
MS		 1508static inline void __pmdp_csp(pmd_t *pmdp)
1509{
1510 register unsigned long reg2 asm("2") = pmd_val(*pmdp);
1511 register unsigned long reg3 asm("3") = pmd_val(*pmdp) |
1512 _SEGMENT_ENTRY_INVALID;
1513 register unsigned long reg4 asm("4") = ((unsigned long) pmdp) + 5;
1514
1515 asm volatile(
1516 " csp %1,%3"
1517 : "=m" (*pmdp)
1518 : "d" (reg2), "d" (reg3), "d" (reg4), "m" (*pmdp) : "cc");
1519}
1520
1521static inline void __pmdp_idte(unsigned long address, pmd_t *pmdp)
1522{
1523 unsigned long sto;
1524
1525 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
1526 asm volatile(
1527 " .insn rrf,0xb98e0000,%2,%3,0,0"
1528 : "=m" (*pmdp)
1529 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
1530 : "cc" );
1531}
1532
1533static inline void __pmdp_idte_local(unsigned long address, pmd_t *pmdp)
1534{
1535 unsigned long sto;
1536
1537 sto = (unsigned long) pmdp - pmd_index(address) * sizeof(pmd_t);
1538 asm volatile(
1539 " .insn rrf,0xb98e0000,%2,%3,0,1"
1540 : "=m" (*pmdp)
1541 : "m" (*pmdp), "a" (sto), "a" ((address & HPAGE_MASK))
1542 : "cc" );
1543}
1544
1545static inline void pmdp_flush_direct(struct mm_struct *mm,
1546 unsigned long address, pmd_t *pmdp)
1547{
1548 int active, count;
1549
1550 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
1551 return;
1552 if (!MACHINE_HAS_IDTE) {
1553 __pmdp_csp(pmdp);
1554 return;
1555 }
1556 active = (mm == current->active_mm) ? 1 : 0;
1557 count = atomic_add_return(0x10000, &mm->context.attach_count);
1558 if (MACHINE_HAS_TLB_LC && (count & 0xffff) <= active &&
1559 cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1560 __pmdp_idte_local(address, pmdp);
1561 else
1562 __pmdp_idte(address, pmdp);
1563 atomic_sub(0x10000, &mm->context.attach_count);
1564}
1565
3eabaee9
MS		 1566static inline void pmdp_flush_lazy(struct mm_struct *mm,
1567 unsigned long address, pmd_t *pmdp)
1568{
53e857f3 1569 int active, count;
3eabaee9 1570
1b948d6c
MS		 1571 if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID)
1572 return;
53e857f3
MS		 1573 active = (mm == current->active_mm) ? 1 : 0;
1574 count = atomic_add_return(0x10000, &mm->context.attach_count);
1575 if ((count & 0xffff) <= active) {
1576 pmd_val(*pmdp) |= _SEGMENT_ENTRY_INVALID;
3eabaee9 1577 mm->context.flush_mm = 1;
1b948d6c
MS		 1578 } else if (MACHINE_HAS_IDTE)
1579 __pmdp_idte(address, pmdp);
1580 else
1581 __pmdp_csp(pmdp);
53e857f3 1582 atomic_sub(0x10000, &mm->context.attach_count);
3eabaee9
MS		 1583}
1584
106c992a
GS		 1585#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1586
1587#define __HAVE_ARCH_PGTABLE_DEPOSIT
6b0b50b0
AK		 1588extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1589 pgtable_t pgtable);
106c992a
GS		 1590
1591#define __HAVE_ARCH_PGTABLE_WITHDRAW
6b0b50b0 1592extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
106c992a
GS		 1593
1594static inline int pmd_trans_splitting(pmd_t pmd)
1595{
152125b7
MS		 1596 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) &&
1597 (pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT);
106c992a
GS		 1598}
1599
1600static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1601 pmd_t *pmdp, pmd_t entry)
1602{
106c992a
GS		 1603 *pmdp = entry;
1604}
1605
1606static inline pmd_t pmd_mkhuge(pmd_t pmd)
1607{
1608 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
152125b7
MS		 1609 pmd_val(pmd) |= _SEGMENT_ENTRY_YOUNG;
1610 pmd_val(pmd) |= _SEGMENT_ENTRY_PROTECT;
1ae1c1d0
GS		 1611 return pmd;
1612}
1613
1ae1c1d0
GS		 1614#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1615static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1616 unsigned long address, pmd_t *pmdp)
1617{
0944fe3f 1618 pmd_t pmd;
1ae1c1d0 1619
0944fe3f 1620 pmd = *pmdp;
1b948d6c 1621 pmdp_flush_direct(vma->vm_mm, address, pmdp);
0944fe3f
MS		 1622 *pmdp = pmd_mkold(pmd);
1623 return pmd_young(pmd);
1ae1c1d0
GS		 1624}
1625
1626#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1627static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1628 unsigned long address, pmd_t *pmdp)
1629{
1630 pmd_t pmd = *pmdp;
1631
1b948d6c 1632 pmdp_flush_direct(mm, address, pmdp);
1ae1c1d0
GS		 1633 pmd_clear(pmdp);
1634 return pmd;
1635}
1636
1637#define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1638static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1639 unsigned long address, pmd_t *pmdp)
1640{
1641 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1642}
1643
1644#define __HAVE_ARCH_PMDP_INVALIDATE
1645static inline void pmdp_invalidate(struct vm_area_struct *vma,
1646 unsigned long address, pmd_t *pmdp)
1647{
1b948d6c 1648 pmdp_flush_direct(vma->vm_mm, address, pmdp);
1ae1c1d0
GS		 1649}
1650
be328650
GS		 1651#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1652static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1653 unsigned long address, pmd_t *pmdp)
1654{
1655 pmd_t pmd = *pmdp;
1656
1657 if (pmd_write(pmd)) {
1b948d6c 1658 pmdp_flush_direct(mm, address, pmdp);
be328650
GS		 1659 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1660 }
1661}
1662
1ae1c1d0
GS		 1663#define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1664#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1665
1666static inline int pmd_trans_huge(pmd_t pmd)
1667{
1668 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1669}
1670
1671static inline int has_transparent_hugepage(void)
1672{
1673 return MACHINE_HAS_HPAGE ? 1 : 0;
1674}
75077afb
GS		 1675#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1676
1da177e4
LT		 1677/*
1678 * 31 bit swap entry format:
1679 * A page-table entry has some bits we have to treat in a special way.
1680 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1681 * exception will occur instead of a page translation exception. The
1682 * specifiation exception has the bad habit not to store necessary
1683 * information in the lowcore.
e5098611
MS		 1684 * Bits 21, 22, 30 and 31 are used to indicate the page type.
1685 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1da177e4
LT		 1686 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1687 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1688 * plus 24 for the offset.
1689 * 0| offset |0110|o|type |00|
1690 * 0 0000000001111111111 2222 2 22222 33
1691 * 0 1234567890123456789 0123 4 56789 01
1692 *
1693 * 64 bit swap entry format:
1694 * A page-table entry has some bits we have to treat in a special way.
1695 * Bits 52 and bit 55 have to be zero, otherwise an specification
1696 * exception will occur instead of a page translation exception. The
1697 * specifiation exception has the bad habit not to store necessary
1698 * information in the lowcore.
e5098611
MS		 1699 * Bits 53, 54, 62 and 63 are used to indicate the page type.
1700 * A swap pte is indicated by bit pattern (pte & 0x603) == 0x402
1da177e4
LT		 1701 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1702 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1703 * plus 56 for the offset.
1704 * | offset |0110|o|type |00|
1705 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1706 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1707 */
f4815ac6 1708#ifndef CONFIG_64BIT
1da177e4
LT		 1709#define __SWP_OFFSET_MASK (~0UL >> 12)
1710#else
1711#define __SWP_OFFSET_MASK (~0UL >> 11)
1712#endif
4448aaf0 1713static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT		 1714{
1715 pte_t pte;
1716 offset &= __SWP_OFFSET_MASK;
e5098611 1717 pte_val(pte) = _PAGE_INVALID | _PAGE_TYPE | ((type & 0x1f) << 2) |
1da177e4
LT		 1718 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1719 return pte;
1720}
1721
1722#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1723#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1724#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1725
1726#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1727#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1728
f4815ac6 1729#ifndef CONFIG_64BIT
1da177e4 1730# define PTE_FILE_MAX_BITS 26
f4815ac6 1731#else /* CONFIG_64BIT */
1da177e4 1732# define PTE_FILE_MAX_BITS 59
f4815ac6 1733#endif /* CONFIG_64BIT */
1da177e4
LT		 1734
1735#define pte_to_pgoff(__pte) \
1736 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1737
1738#define pgoff_to_pte(__off) \
1739 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
e5098611 1740 | _PAGE_INVALID | _PAGE_PROTECT })
1da177e4
LT		 1741
1742#endif /* !__ASSEMBLY__ */
1743
1744#define kern_addr_valid(addr) (1)
1745
17f34580
HC		 1746extern int vmem_add_mapping(unsigned long start, unsigned long size);
1747extern int vmem_remove_mapping(unsigned long start, unsigned long size);
402b0862 1748extern int s390_enable_sie(void);
934bc131 1749extern void s390_enable_skey(void);
f4eb07c1 1750
1da177e4
LT		 1751/*
1752 * No page table caches to initialise
1753 */
765a0cac
HC		 1754static inline void pgtable_cache_init(void) { }
1755static inline void check_pgt_cache(void) { }
1da177e4 1756
1da177e4
LT		 1757#include <asm-generic/pgtable.h>
1758
1759#endif /* _S390_PAGE_H */
Linux kernel - Deliverables
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