[deliverable/linux.git] / arch / s390 / include / asm / processor.h

/*
 *  S390 version
 *    Copyright IBM Corp. 1999
 *    Author(s): Hartmut Penner (hp@de.ibm.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *
 *  Derived from "include/asm-i386/processor.h"
 *    Copyright (C) 1994, Linus Torvalds
 */

#ifndef __ASM_S390_PROCESSOR_H
#define __ASM_S390_PROCESSOR_H

#include <linux/const.h>

#define CIF_MCCK_PENDING	0	/* machine check handling is pending */
#define CIF_ASCE		1	/* user asce needs fixup / uaccess */
#define CIF_NOHZ_DELAY		2	/* delay HZ disable for a tick */
#define CIF_FPU			3	/* restore FPU registers */
#define CIF_IGNORE_IRQ		4	/* ignore interrupt (for udelay) */
#define CIF_ENABLED_WAIT	5	/* in enabled wait state */

#define _CIF_MCCK_PENDING	_BITUL(CIF_MCCK_PENDING)
#define _CIF_ASCE		_BITUL(CIF_ASCE)
#define _CIF_NOHZ_DELAY		_BITUL(CIF_NOHZ_DELAY)
#define _CIF_FPU		_BITUL(CIF_FPU)
#define _CIF_IGNORE_IRQ		_BITUL(CIF_IGNORE_IRQ)
#define _CIF_ENABLED_WAIT	_BITUL(CIF_ENABLED_WAIT)

#ifndef __ASSEMBLY__

#include <linux/linkage.h>
#include <linux/irqflags.h>
#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/runtime_instr.h>
#include <asm/fpu/types.h>
#include <asm/fpu/internal.h>

static inline void set_cpu_flag(int flag)
{
	S390_lowcore.cpu_flags |= (1UL << flag);
}

static inline void clear_cpu_flag(int flag)
{
	S390_lowcore.cpu_flags &= ~(1UL << flag);
}

static inline int test_cpu_flag(int flag)
{
	return !!(S390_lowcore.cpu_flags & (1UL << flag));
}

/*
 * Test CIF flag of another CPU. The caller needs to ensure that
 * CPU hotplug can not happen, e.g. by disabling preemption.
 */
static inline int test_cpu_flag_of(int flag, int cpu)
{
	struct lowcore *lc = lowcore_ptr[cpu];
	return !!(lc->cpu_flags & (1UL << flag));
}

#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })

static inline void get_cpu_id(struct cpuid *ptr)
{
	asm volatile("stidp %0" : "=Q" (*ptr));
}

extern void s390_adjust_jiffies(void);
extern const struct seq_operations cpuinfo_op;
extern int sysctl_ieee_emulation_warnings;
extern void execve_tail(void);

/*
 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
 */

#define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
#define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
					(1UL << 30) : (1UL << 41))
#define TASK_SIZE		TASK_SIZE_OF(current)
#define TASK_MAX_SIZE		(1UL << 53)

#define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
#define STACK_TOP_MAX		(1UL << 42)

#define HAVE_ARCH_PICK_MMAP_LAYOUT

typedef struct {
        __u32 ar4;
} mm_segment_t;

/*
 * Thread structure
 */
struct thread_struct {
	struct fpu fpu;			/* FP and VX register save area */
	unsigned int  acrs[NUM_ACRS];
        unsigned long ksp;              /* kernel stack pointer             */
	mm_segment_t mm_segment;
	unsigned long gmap_addr;	/* address of last gmap fault. */
	unsigned int gmap_pfault;	/* signal of a pending guest pfault */
	struct per_regs per_user;	/* User specified PER registers */
	struct per_event per_event;	/* Cause of the last PER trap */
	unsigned long per_flags;	/* Flags to control debug behavior */
        /* pfault_wait is used to block the process on a pfault event */
	unsigned long pfault_wait;
	struct list_head list;
	/* cpu runtime instrumentation */
	struct runtime_instr_cb *ri_cb;
	unsigned char trap_tdb[256];	/* Transaction abort diagnose block */
};

/* Flag to disable transactions. */
#define PER_FLAG_NO_TE			1UL
/* Flag to enable random transaction aborts. */
#define PER_FLAG_TE_ABORT_RAND		2UL
/* Flag to specify random transaction abort mode:
 * - abort each transaction at a random instruction before TEND if set.
 * - abort random transactions at a random instruction if cleared.
 */
#define PER_FLAG_TE_ABORT_RAND_TEND	4UL

typedef struct thread_struct thread_struct;

/*
 * Stack layout of a C stack frame.
 */
#ifndef __PACK_STACK
struct stack_frame {
	unsigned long back_chain;
	unsigned long empty1[5];
	unsigned long gprs[10];
	unsigned int  empty2[8];
};
#else
struct stack_frame {
	unsigned long empty1[5];
	unsigned int  empty2[8];
	unsigned long gprs[10];
	unsigned long back_chain;
};
#endif

#define ARCH_MIN_TASKALIGN	8

extern __vector128 init_task_fpu_regs[__NUM_VXRS];
#define INIT_THREAD {							\
	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
	.fpu.regs = (void *)&init_task_fpu_regs,			\
}

/*
 * Do necessary setup to start up a new thread.
 */
#define start_thread(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
	regs->psw.addr	= new_psw;					\
	regs->gprs[15]	= new_stackp;					\
	execve_tail();							\
} while (0)

#define start_thread31(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
	regs->psw.addr	= new_psw;					\
	regs->gprs[15]	= new_stackp;					\
	crst_table_downgrade(current->mm, 1UL << 31);			\
	execve_tail();							\
} while (0)

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
struct seq_file;

void show_cacheinfo(struct seq_file *m);

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

/*
 * Return saved PC of a blocked thread.
 */
extern unsigned long thread_saved_pc(struct task_struct *t);

unsigned long get_wchan(struct task_struct *p);
#define task_pt_regs(tsk) ((struct pt_regs *) \
        (task_stack_page(tsk) + THREAD_SIZE) - 1)
#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])

/* Has task runtime instrumentation enabled ? */
#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)

static inline unsigned short stap(void)
{
	unsigned short cpu_address;

	asm volatile("stap %0" : "=m" (cpu_address));
	return cpu_address;
}

/*
 * Give up the time slice of the virtual PU.
 */
void cpu_relax(void);

#define cpu_relax_lowlatency()  barrier()

static inline void psw_set_key(unsigned int key)
{
	asm volatile("spka 0(%0)" : : "d" (key));
}

/*
 * Set PSW to specified value.
 */
static inline void __load_psw(psw_t psw)
{
	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
}

/*
 * Set PSW mask to specified value, while leaving the
 * PSW addr pointing to the next instruction.
 */
static inline void __load_psw_mask(unsigned long mask)
{
	unsigned long addr;
	psw_t psw;

	psw.mask = mask;

	asm volatile(
		"	larl	%0,1f\n"
		"	stg	%0,%O1+8(%R1)\n"
		"	lpswe	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
}

/*
 * Extract current PSW mask
 */
static inline unsigned long __extract_psw(void)
{
	unsigned int reg1, reg2;

	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
	return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
}

static inline void local_mcck_enable(void)
{
	__load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
}

static inline void local_mcck_disable(void)
{
	__load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
}

/*
 * Rewind PSW instruction address by specified number of bytes.
 */
static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
{
	unsigned long mask;

	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
					  (1UL << 24) - 1;
	return (psw.addr - ilc) & mask;
}

/*
 * Function to stop a processor until the next interrupt occurs
 */
void enabled_wait(void);

/*
 * Function to drop a processor into disabled wait state
 */
static inline void __noreturn disabled_wait(unsigned long code)
{
	psw_t psw;

	psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
	psw.addr = code;
	__load_psw(psw);
	while (1);
}

/*
 * Basic Machine Check/Program Check Handler.
 */

extern void s390_base_mcck_handler(void);
extern void s390_base_pgm_handler(void);
extern void s390_base_ext_handler(void);

extern void (*s390_base_mcck_handler_fn)(void);
extern void (*s390_base_pgm_handler_fn)(void);
extern void (*s390_base_ext_handler_fn)(void);

#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL

extern int memcpy_real(void *, void *, size_t);
extern void memcpy_absolute(void *, void *, size_t);

#define mem_assign_absolute(dest, val) {			\
	__typeof__(dest) __tmp = (val);				\
								\
	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
}

#endif /* __ASSEMBLY__ */

#endif /* __ASM_S390_PROCESSOR_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* S390 version
a53c8fab	3	* Copyright IBM Corp. 1999
1da177e4 LT	4	* Author(s): Hartmut Penner (hp@de.ibm.com),
	5	* Martin Schwidefsky (schwidefsky@de.ibm.com)
	6	*
	7	* Derived from "include/asm-i386/processor.h"
	8	* Copyright (C) 1994, Linus Torvalds
	9	*/
	10
	11	#ifndef __ASM_S390_PROCESSOR_H
	12	#define __ASM_S390_PROCESSOR_H
	13
92778b99 HC	14	#include <linux/const.h>
92778b99 HC	15
d3a73acb MS	16	#define CIF_MCCK_PENDING 0 /* machine check handling is pending */
d3a73acb MS	17	#define CIF_ASCE 1 /* user asce needs fixup / uaccess */
fe0f4976	18	#define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
b0753902	19	#define CIF_FPU 3 /* restore FPU registers */
db7e007f	20	#define CIF_IGNORE_IRQ 4 /* ignore interrupt (for udelay) */
419123f9	21	#define CIF_ENABLED_WAIT 5 /* in enabled wait state */
d3a73acb	22
92778b99 HC	23	#define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING)
	24	#define _CIF_ASCE _BITUL(CIF_ASCE)
	25	#define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY)
	26	#define _CIF_FPU _BITUL(CIF_FPU)
	27	#define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ)
419123f9	28	#define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT)
d3a73acb	29
eb608fb3 HC	30	#ifndef __ASSEMBLY__
eb608fb3 HC	31
edd53787	32	#include <linux/linkage.h>
a0616cde	33	#include <linux/irqflags.h>
e86a6ed6	34	#include <asm/cpu.h>
25097bf1	35	#include <asm/page.h>
1da177e4	36	#include <asm/ptrace.h>
25097bf1	37	#include <asm/setup.h>
e4b8b3f3	38	#include <asm/runtime_instr.h>
b0753902 HB	39	#include <asm/fpu/types.h>
b0753902 HB	40	#include <asm/fpu/internal.h>
1da177e4	41
d3a73acb MS	42	static inline void set_cpu_flag(int flag)
d3a73acb MS	43	{
ac25e790	44	S390_lowcore.cpu_flags \|= (1UL << flag);
d3a73acb MS	45	}
	46
	47	static inline void clear_cpu_flag(int flag)
	48	{
ac25e790	49	S390_lowcore.cpu_flags &= ~(1UL << flag);
d3a73acb MS	50	}
	51
	52	static inline int test_cpu_flag(int flag)
	53	{
ac25e790	54	return !!(S390_lowcore.cpu_flags & (1UL << flag));
d3a73acb MS	55	}
d3a73acb MS	56
419123f9 MS	57	/*
	58	* Test CIF flag of another CPU. The caller needs to ensure that
	59	* CPU hotplug can not happen, e.g. by disabling preemption.
	60	*/
	61	static inline int test_cpu_flag_of(int flag, int cpu)
	62	{
c667aeac	63	struct lowcore *lc = lowcore_ptr[cpu];
419123f9 MS	64	return !!(lc->cpu_flags & (1UL << flag));
	65	}
	66
fe0f4976 MS	67	#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
fe0f4976 MS	68
1da177e4 LT	69	/*
	70	* Default implementation of macro that returns current
	71	* instruction pointer ("program counter").
	72	*/
94c12cc7	73	#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
1da177e4	74
e86a6ed6	75	static inline void get_cpu_id(struct cpuid *ptr)
72960a02	76	{
987bcdac	77	asm volatile("stidp %0" : "=Q" (*ptr));
72960a02 MH	78	}
72960a02 MH	79
31ee4b2f	80	extern void s390_adjust_jiffies(void);
638ad34a MS	81	extern const struct seq_operations cpuinfo_op;
638ad34a MS	82	extern int sysctl_ieee_emulation_warnings;
65f22a90	83	extern void execve_tail(void);
1da177e4	84
1da177e4	85	/*
f481bfaf	86	* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
1da177e4	87	*/
1da177e4	88
f481bfaf	89	#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
5a216a20 MS	90	#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
	91	(1UL << 30) : (1UL << 41))
	92	#define TASK_SIZE TASK_SIZE_OF(current)
ee6ee55b	93	#define TASK_MAX_SIZE (1UL << 53)
1da177e4	94
6252d702 MS	95	#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
6252d702 MS	96	#define STACK_TOP_MAX (1UL << 42)
922a70d3	97
1da177e4 LT	98	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	99
	100	typedef struct {
	101	__u32 ar4;
	102	} mm_segment_t;
	103
	104	/*
	105	* Thread structure
	106	*/
	107	struct thread_struct {
904818e2	108	struct fpu fpu; /* FP and VX register save area */
1da177e4 LT	109	unsigned int acrs[NUM_ACRS];
1da177e4 LT	110	unsigned long ksp; /* kernel stack pointer */
1da177e4	111	mm_segment_t mm_segment;
e5992f2e	112	unsigned long gmap_addr; /* address of last gmap fault. */
24eb3a82	113	unsigned int gmap_pfault; /* signal of a pending guest pfault */
5e9a2692 MS	114	struct per_regs per_user; /* User specified PER registers */
5e9a2692 MS	115	struct per_event per_event; /* Cause of the last PER trap */
d35339a4	116	unsigned long per_flags; /* Flags to control debug behavior */
1da177e4 LT	117	/* pfault_wait is used to block the process on a pfault event */
1da177e4 LT	118	unsigned long pfault_wait;
f2db2e6c	119	struct list_head list;
e4b8b3f3 JG	120	/* cpu runtime instrumentation */
e4b8b3f3 JG	121	struct runtime_instr_cb *ri_cb;
d35339a4	122	unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
1da177e4 LT	123	};
1da177e4 LT	124
64597f9d MM	125	/* Flag to disable transactions. */
	126	#define PER_FLAG_NO_TE 1UL
	127	/* Flag to enable random transaction aborts. */
	128	#define PER_FLAG_TE_ABORT_RAND 2UL
	129	/* Flag to specify random transaction abort mode:
	130	* - abort each transaction at a random instruction before TEND if set.
	131	* - abort random transactions at a random instruction if cleared.
	132	*/
	133	#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
d35339a4	134
1da177e4 LT	135	typedef struct thread_struct thread_struct;
	136
	137	/*
	138	* Stack layout of a C stack frame.
	139	*/
	140	#ifndef __PACK_STACK
	141	struct stack_frame {
	142	unsigned long back_chain;
	143	unsigned long empty1[5];
	144	unsigned long gprs[10];
	145	unsigned int empty2[8];
	146	};
	147	#else
	148	struct stack_frame {
	149	unsigned long empty1[5];
	150	unsigned int empty2[8];
	151	unsigned long gprs[10];
	152	unsigned long back_chain;
	153	};
	154	#endif
	155
	156	#define ARCH_MIN_TASKALIGN 8
	157
0ac27779	158	extern __vector128 init_task_fpu_regs[__NUM_VXRS];
6f3fa3f0 MS	159	#define INIT_THREAD { \
6f3fa3f0 MS	160	.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
0ac27779	161	.fpu.regs = (void *)&init_task_fpu_regs, \
6f3fa3f0	162	}
1da177e4 LT	163
	164	/*
	165	* Do necessary setup to start up a new thread.
	166	*/
b50511e4	167	#define start_thread(regs, new_psw, new_stackp) do { \
e258d719	168	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_EA \| PSW_MASK_BA; \
fecc868a	169	regs->psw.addr = new_psw; \
b50511e4	170	regs->gprs[15] = new_stackp; \
65f22a90	171	execve_tail(); \
63506c41 MS	172	} while (0)
63506c41 MS	173
b50511e4	174	#define start_thread31(regs, new_psw, new_stackp) do { \
e258d719	175	regs->psw.mask = PSW_USER_BITS \| PSW_MASK_BA; \
fecc868a	176	regs->psw.addr = new_psw; \
b50511e4 MS	177	regs->gprs[15] = new_stackp; \
b50511e4 MS	178	crst_table_downgrade(current->mm, 1UL << 31); \
65f22a90	179	execve_tail(); \
1da177e4 LT	180	} while (0)
1da177e4 LT	181
1da177e4 LT	182	/* Forward declaration, a strange C thing */
	183	struct task_struct;
	184	struct mm_struct;
df5f8314	185	struct seq_file;
1da177e4	186
5a79859a	187	void show_cacheinfo(struct seq_file *m);
6668022c	188
1da177e4 LT	189	/* Free all resources held by a thread. */
1da177e4 LT	190	extern void release_thread(struct task_struct *);
1da177e4	191
1da177e4 LT	192	/*
	193	* Return saved PC of a blocked thread.
	194	*/
	195	extern unsigned long thread_saved_pc(struct task_struct *t);
	196
1da177e4	197	unsigned long get_wchan(struct task_struct *p);
c7584fb6	198	#define task_pt_regs(tsk) ((struct pt_regs *) \
30af7120	199	(task_stack_page(tsk) + THREAD_SIZE) - 1)
c7584fb6 AV	200	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
c7584fb6 AV	201	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
1da177e4	202
5ebf250d HC	203	/* Has task runtime instrumentation enabled ? */
	204	#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
	205
a0616cde DH	206	static inline unsigned short stap(void)
	207	{
	208	unsigned short cpu_address;
	209
	210	asm volatile("stap %0" : "=m" (cpu_address));
	211	return cpu_address;
	212	}
	213
1da177e4 LT	214	/*
	215	* Give up the time slice of the virtual PU.
	216	*/
4d92f502	217	void cpu_relax(void);
1da177e4	218
3a6bfbc9	219	#define cpu_relax_lowlatency() barrier()
083986e8	220
dc74d7f9 HC	221	static inline void psw_set_key(unsigned int key)
	222	{
	223	asm volatile("spka 0(%0)" : : "d" (key));
	224	}
	225
77fa2245 HC	226	/*
	227	* Set PSW to specified value.
	228	*/
	229	static inline void __load_psw(psw_t psw)
	230	{
987bcdac	231	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
77fa2245 HC	232	}
77fa2245 HC	233
1da177e4 LT	234	/*
	235	* Set PSW mask to specified value, while leaving the
	236	* PSW addr pointing to the next instruction.
	237	*/
ecbafda8	238	static inline void __load_psw_mask(unsigned long mask)
1da177e4 LT	239	{
1da177e4 LT	240	unsigned long addr;
1da177e4	241	psw_t psw;
77fa2245	242
1da177e4 LT	243	psw.mask = mask;
1da177e4 LT	244
94c12cc7 MS	245	asm volatile(
94c12cc7 MS	246	" larl %0,1f\n"
987bcdac MS	247	" stg %0,%O1+8(%R1)\n"
987bcdac MS	248	" lpswe %1\n"
1da177e4	249	"1:"
987bcdac	250	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
1da177e4	251	}
ccf45caf	252
22362a0e MS	253	/*
	254	* Extract current PSW mask
	255	*/
	256	static inline unsigned long __extract_psw(void)
	257	{
	258	unsigned int reg1, reg2;
	259
	260	asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
	261	return (((unsigned long) reg1) << 32) \| ((unsigned long) reg2);
	262	}
	263
ecbafda8 HC	264	static inline void local_mcck_enable(void)
	265	{
	266	__load_psw_mask(__extract_psw() \| PSW_MASK_MCHECK);
	267	}
	268
	269	static inline void local_mcck_disable(void)
	270	{
	271	__load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
	272	}
	273
ccf45caf MS	274	/*
	275	* Rewind PSW instruction address by specified number of bytes.
	276	*/
	277	static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
	278	{
ccf45caf MS	279	unsigned long mask;
	280
	281	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	282	(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
	283	(1UL << 24) - 1;
	284	return (psw.addr - ilc) & mask;
ccf45caf	285	}
b5f87f15 MS	286
	287	/*
	288	* Function to stop a processor until the next interrupt occurs
	289	*/
	290	void enabled_wait(void);
	291
1da177e4 LT	292	/*
	293	* Function to drop a processor into disabled wait state
	294	*/
ff2d8b19	295	static inline void __noreturn disabled_wait(unsigned long code)
1da177e4	296	{
f9e6edfb HC	297	psw_t psw;
	298
	299	psw.mask = PSW_MASK_BASE \| PSW_MASK_WAIT \| PSW_MASK_BA \| PSW_MASK_EA;
	300	psw.addr = code;
	301	__load_psw(psw);
edd53787	302	while (1);
1da177e4 LT	303	}
1da177e4 LT	304
ab14de6c HC	305	/*
	306	* Basic Machine Check/Program Check Handler.
	307	*/
	308
	309	extern void s390_base_mcck_handler(void);
	310	extern void s390_base_pgm_handler(void);
	311	extern void s390_base_ext_handler(void);
	312
	313	extern void (*s390_base_mcck_handler_fn)(void);
	314	extern void (*s390_base_pgm_handler_fn)(void);
	315	extern void (*s390_base_ext_handler_fn)(void);
	316
dfd54cbc HC	317	#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
dfd54cbc HC	318
fbe76568 HC	319	extern int memcpy_real(void , void , size_t);
	320	extern void memcpy_absolute(void , void , size_t);
	321
	322	#define mem_assign_absolute(dest, val) { \
	323	__typeof__(dest) __tmp = (val); \
	324	\
	325	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
	326	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
	327	}
	328
eb608fb3 HC	329	#endif /* __ASSEMBLY__ */
	330
	331	#endif /* __ASM_S390_PROCESSOR_H */