Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
5 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
6 | * | |
7 | * Derived from "include/asm-i386/processor.h" | |
8 | * Copyright (C) 1994, Linus Torvalds | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_S390_PROCESSOR_H | |
12 | #define __ASM_S390_PROCESSOR_H | |
13 | ||
eb608fb3 HC |
14 | #ifndef __ASSEMBLY__ |
15 | ||
edd53787 | 16 | #include <linux/linkage.h> |
a0616cde | 17 | #include <linux/irqflags.h> |
e86a6ed6 | 18 | #include <asm/cpu.h> |
25097bf1 | 19 | #include <asm/page.h> |
1da177e4 | 20 | #include <asm/ptrace.h> |
25097bf1 | 21 | #include <asm/setup.h> |
e4b8b3f3 | 22 | #include <asm/runtime_instr.h> |
1da177e4 | 23 | |
1da177e4 LT |
24 | /* |
25 | * Default implementation of macro that returns current | |
26 | * instruction pointer ("program counter"). | |
27 | */ | |
94c12cc7 | 28 | #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) |
1da177e4 | 29 | |
e86a6ed6 | 30 | static inline void get_cpu_id(struct cpuid *ptr) |
72960a02 | 31 | { |
987bcdac | 32 | asm volatile("stidp %0" : "=Q" (*ptr)); |
72960a02 MH |
33 | } |
34 | ||
31ee4b2f | 35 | extern void s390_adjust_jiffies(void); |
638ad34a MS |
36 | extern const struct seq_operations cpuinfo_op; |
37 | extern int sysctl_ieee_emulation_warnings; | |
65f22a90 | 38 | extern void execve_tail(void); |
1da177e4 | 39 | |
1da177e4 | 40 | /* |
f481bfaf | 41 | * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. |
1da177e4 | 42 | */ |
f4815ac6 | 43 | #ifndef CONFIG_64BIT |
1da177e4 | 44 | |
5a216a20 MS |
45 | #define TASK_SIZE (1UL << 31) |
46 | #define TASK_UNMAPPED_BASE (1UL << 30) | |
1da177e4 | 47 | |
f4815ac6 | 48 | #else /* CONFIG_64BIT */ |
1da177e4 | 49 | |
f481bfaf | 50 | #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) |
5a216a20 MS |
51 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ |
52 | (1UL << 30) : (1UL << 41)) | |
53 | #define TASK_SIZE TASK_SIZE_OF(current) | |
1da177e4 | 54 | |
f4815ac6 | 55 | #endif /* CONFIG_64BIT */ |
1da177e4 | 56 | |
f4815ac6 | 57 | #ifndef CONFIG_64BIT |
5a216a20 | 58 | #define STACK_TOP (1UL << 31) |
6252d702 | 59 | #define STACK_TOP_MAX (1UL << 31) |
f4815ac6 | 60 | #else /* CONFIG_64BIT */ |
6252d702 MS |
61 | #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) |
62 | #define STACK_TOP_MAX (1UL << 42) | |
f4815ac6 | 63 | #endif /* CONFIG_64BIT */ |
922a70d3 | 64 | |
1da177e4 LT |
65 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
66 | ||
67 | typedef struct { | |
68 | __u32 ar4; | |
69 | } mm_segment_t; | |
70 | ||
71 | /* | |
72 | * Thread structure | |
73 | */ | |
74 | struct thread_struct { | |
75 | s390_fp_regs fp_regs; | |
76 | unsigned int acrs[NUM_ACRS]; | |
77 | unsigned long ksp; /* kernel stack pointer */ | |
1da177e4 | 78 | mm_segment_t mm_segment; |
e5992f2e | 79 | unsigned long gmap_addr; /* address of last gmap fault. */ |
5e9a2692 MS |
80 | struct per_regs per_user; /* User specified PER registers */ |
81 | struct per_event per_event; /* Cause of the last PER trap */ | |
d35339a4 | 82 | unsigned long per_flags; /* Flags to control debug behavior */ |
1da177e4 LT |
83 | /* pfault_wait is used to block the process on a pfault event */ |
84 | unsigned long pfault_wait; | |
f2db2e6c | 85 | struct list_head list; |
e4b8b3f3 JG |
86 | /* cpu runtime instrumentation */ |
87 | struct runtime_instr_cb *ri_cb; | |
88 | int ri_signum; | |
d35339a4 MS |
89 | #ifdef CONFIG_64BIT |
90 | unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ | |
91 | #endif | |
1da177e4 LT |
92 | }; |
93 | ||
d35339a4 MS |
94 | #define PER_FLAG_NO_TE 1UL /* Flag to disable transactions. */ |
95 | ||
1da177e4 LT |
96 | typedef struct thread_struct thread_struct; |
97 | ||
98 | /* | |
99 | * Stack layout of a C stack frame. | |
100 | */ | |
101 | #ifndef __PACK_STACK | |
102 | struct stack_frame { | |
103 | unsigned long back_chain; | |
104 | unsigned long empty1[5]; | |
105 | unsigned long gprs[10]; | |
106 | unsigned int empty2[8]; | |
107 | }; | |
108 | #else | |
109 | struct stack_frame { | |
110 | unsigned long empty1[5]; | |
111 | unsigned int empty2[8]; | |
112 | unsigned long gprs[10]; | |
113 | unsigned long back_chain; | |
114 | }; | |
115 | #endif | |
116 | ||
117 | #define ARCH_MIN_TASKALIGN 8 | |
118 | ||
6f3fa3f0 MS |
119 | #define INIT_THREAD { \ |
120 | .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ | |
121 | } | |
1da177e4 LT |
122 | |
123 | /* | |
124 | * Do necessary setup to start up a new thread. | |
125 | */ | |
b50511e4 MS |
126 | #define start_thread(regs, new_psw, new_stackp) do { \ |
127 | regs->psw.mask = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA; \ | |
128 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ | |
129 | regs->gprs[15] = new_stackp; \ | |
65f22a90 | 130 | execve_tail(); \ |
63506c41 MS |
131 | } while (0) |
132 | ||
b50511e4 MS |
133 | #define start_thread31(regs, new_psw, new_stackp) do { \ |
134 | regs->psw.mask = psw_user_bits | PSW_MASK_BA; \ | |
135 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ | |
136 | regs->gprs[15] = new_stackp; \ | |
0f6f281b | 137 | __tlb_flush_mm(current->mm); \ |
b50511e4 | 138 | crst_table_downgrade(current->mm, 1UL << 31); \ |
0f6f281b | 139 | update_mm(current->mm, current); \ |
65f22a90 | 140 | execve_tail(); \ |
1da177e4 LT |
141 | } while (0) |
142 | ||
1da177e4 LT |
143 | /* Forward declaration, a strange C thing */ |
144 | struct task_struct; | |
145 | struct mm_struct; | |
df5f8314 | 146 | struct seq_file; |
1da177e4 | 147 | |
6668022c HC |
148 | #ifdef CONFIG_64BIT |
149 | extern void show_cacheinfo(struct seq_file *m); | |
150 | #else | |
151 | static inline void show_cacheinfo(struct seq_file *m) { } | |
152 | #endif | |
153 | ||
1da177e4 LT |
154 | /* Free all resources held by a thread. */ |
155 | extern void release_thread(struct task_struct *); | |
1da177e4 | 156 | |
1da177e4 LT |
157 | /* |
158 | * Return saved PC of a blocked thread. | |
159 | */ | |
160 | extern unsigned long thread_saved_pc(struct task_struct *t); | |
161 | ||
bb11e3bd | 162 | extern void show_code(struct pt_regs *regs); |
c10302ef | 163 | extern void print_fn_code(unsigned char *code, unsigned long len); |
9b7fb990 | 164 | extern int insn_to_mnemonic(unsigned char *instruction, char buf[8]); |
1da177e4 LT |
165 | |
166 | unsigned long get_wchan(struct task_struct *p); | |
c7584fb6 | 167 | #define task_pt_regs(tsk) ((struct pt_regs *) \ |
30af7120 | 168 | (task_stack_page(tsk) + THREAD_SIZE) - 1) |
c7584fb6 AV |
169 | #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) |
170 | #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) | |
1da177e4 | 171 | |
a0616cde DH |
172 | static inline unsigned short stap(void) |
173 | { | |
174 | unsigned short cpu_address; | |
175 | ||
176 | asm volatile("stap %0" : "=m" (cpu_address)); | |
177 | return cpu_address; | |
178 | } | |
179 | ||
1da177e4 LT |
180 | /* |
181 | * Give up the time slice of the virtual PU. | |
182 | */ | |
abdba61a HC |
183 | static inline void cpu_relax(void) |
184 | { | |
185 | if (MACHINE_HAS_DIAG44) | |
c48e0913 HC |
186 | asm volatile("diag 0,0,68"); |
187 | barrier(); | |
abdba61a | 188 | } |
1da177e4 | 189 | |
dc74d7f9 HC |
190 | static inline void psw_set_key(unsigned int key) |
191 | { | |
192 | asm volatile("spka 0(%0)" : : "d" (key)); | |
193 | } | |
194 | ||
77fa2245 HC |
195 | /* |
196 | * Set PSW to specified value. | |
197 | */ | |
198 | static inline void __load_psw(psw_t psw) | |
199 | { | |
f4815ac6 | 200 | #ifndef CONFIG_64BIT |
987bcdac | 201 | asm volatile("lpsw %0" : : "Q" (psw) : "cc"); |
77fa2245 | 202 | #else |
987bcdac | 203 | asm volatile("lpswe %0" : : "Q" (psw) : "cc"); |
77fa2245 HC |
204 | #endif |
205 | } | |
206 | ||
1da177e4 LT |
207 | /* |
208 | * Set PSW mask to specified value, while leaving the | |
209 | * PSW addr pointing to the next instruction. | |
210 | */ | |
1da177e4 LT |
211 | static inline void __load_psw_mask (unsigned long mask) |
212 | { | |
213 | unsigned long addr; | |
1da177e4 | 214 | psw_t psw; |
77fa2245 | 215 | |
1da177e4 LT |
216 | psw.mask = mask; |
217 | ||
f4815ac6 | 218 | #ifndef CONFIG_64BIT |
94c12cc7 MS |
219 | asm volatile( |
220 | " basr %0,0\n" | |
221 | "0: ahi %0,1f-0b\n" | |
987bcdac MS |
222 | " st %0,%O1+4(%R1)\n" |
223 | " lpsw %1\n" | |
1da177e4 | 224 | "1:" |
987bcdac | 225 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
f4815ac6 | 226 | #else /* CONFIG_64BIT */ |
94c12cc7 MS |
227 | asm volatile( |
228 | " larl %0,1f\n" | |
987bcdac MS |
229 | " stg %0,%O1+8(%R1)\n" |
230 | " lpswe %1\n" | |
1da177e4 | 231 | "1:" |
987bcdac | 232 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
f4815ac6 | 233 | #endif /* CONFIG_64BIT */ |
1da177e4 | 234 | } |
ccf45caf MS |
235 | |
236 | /* | |
237 | * Rewind PSW instruction address by specified number of bytes. | |
238 | */ | |
239 | static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) | |
240 | { | |
f4815ac6 | 241 | #ifndef CONFIG_64BIT |
ccf45caf MS |
242 | if (psw.addr & PSW_ADDR_AMODE) |
243 | /* 31 bit mode */ | |
244 | return (psw.addr - ilc) | PSW_ADDR_AMODE; | |
245 | /* 24 bit mode */ | |
246 | return (psw.addr - ilc) & ((1UL << 24) - 1); | |
247 | #else | |
248 | unsigned long mask; | |
249 | ||
250 | mask = (psw.mask & PSW_MASK_EA) ? -1UL : | |
251 | (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : | |
252 | (1UL << 24) - 1; | |
253 | return (psw.addr - ilc) & mask; | |
254 | #endif | |
255 | } | |
1da177e4 | 256 | |
1da177e4 LT |
257 | /* |
258 | * Function to drop a processor into disabled wait state | |
259 | */ | |
ff2d8b19 | 260 | static inline void __noreturn disabled_wait(unsigned long code) |
1da177e4 | 261 | { |
1da177e4 | 262 | unsigned long ctl_buf; |
77fa2245 | 263 | psw_t dw_psw; |
1da177e4 | 264 | |
b50511e4 | 265 | dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; |
77fa2245 | 266 | dw_psw.addr = code; |
1da177e4 LT |
267 | /* |
268 | * Store status and then load disabled wait psw, | |
269 | * the processor is dead afterwards | |
270 | */ | |
f4815ac6 | 271 | #ifndef CONFIG_64BIT |
94c12cc7 MS |
272 | asm volatile( |
273 | " stctl 0,0,0(%2)\n" | |
274 | " ni 0(%2),0xef\n" /* switch off protection */ | |
275 | " lctl 0,0,0(%2)\n" | |
276 | " stpt 0xd8\n" /* store timer */ | |
277 | " stckc 0xe0\n" /* store clock comparator */ | |
278 | " stpx 0x108\n" /* store prefix register */ | |
279 | " stam 0,15,0x120\n" /* store access registers */ | |
280 | " std 0,0x160\n" /* store f0 */ | |
281 | " std 2,0x168\n" /* store f2 */ | |
282 | " std 4,0x170\n" /* store f4 */ | |
283 | " std 6,0x178\n" /* store f6 */ | |
284 | " stm 0,15,0x180\n" /* store general registers */ | |
285 | " stctl 0,15,0x1c0\n" /* store control registers */ | |
286 | " oi 0x1c0,0x10\n" /* fake protection bit */ | |
287 | " lpsw 0(%1)" | |
288 | : "=m" (ctl_buf) | |
289 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc"); | |
f4815ac6 | 290 | #else /* CONFIG_64BIT */ |
94c12cc7 MS |
291 | asm volatile( |
292 | " stctg 0,0,0(%2)\n" | |
293 | " ni 4(%2),0xef\n" /* switch off protection */ | |
294 | " lctlg 0,0,0(%2)\n" | |
295 | " lghi 1,0x1000\n" | |
296 | " stpt 0x328(1)\n" /* store timer */ | |
297 | " stckc 0x330(1)\n" /* store clock comparator */ | |
298 | " stpx 0x318(1)\n" /* store prefix register */ | |
299 | " stam 0,15,0x340(1)\n"/* store access registers */ | |
300 | " stfpc 0x31c(1)\n" /* store fpu control */ | |
301 | " std 0,0x200(1)\n" /* store f0 */ | |
302 | " std 1,0x208(1)\n" /* store f1 */ | |
303 | " std 2,0x210(1)\n" /* store f2 */ | |
304 | " std 3,0x218(1)\n" /* store f3 */ | |
305 | " std 4,0x220(1)\n" /* store f4 */ | |
306 | " std 5,0x228(1)\n" /* store f5 */ | |
307 | " std 6,0x230(1)\n" /* store f6 */ | |
308 | " std 7,0x238(1)\n" /* store f7 */ | |
309 | " std 8,0x240(1)\n" /* store f8 */ | |
310 | " std 9,0x248(1)\n" /* store f9 */ | |
311 | " std 10,0x250(1)\n" /* store f10 */ | |
312 | " std 11,0x258(1)\n" /* store f11 */ | |
313 | " std 12,0x260(1)\n" /* store f12 */ | |
314 | " std 13,0x268(1)\n" /* store f13 */ | |
315 | " std 14,0x270(1)\n" /* store f14 */ | |
316 | " std 15,0x278(1)\n" /* store f15 */ | |
317 | " stmg 0,15,0x280(1)\n"/* store general registers */ | |
318 | " stctg 0,15,0x380(1)\n"/* store control registers */ | |
319 | " oi 0x384(1),0x10\n"/* fake protection bit */ | |
320 | " lpswe 0(%1)" | |
321 | : "=m" (ctl_buf) | |
bdd42b28 | 322 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1"); |
f4815ac6 | 323 | #endif /* CONFIG_64BIT */ |
edd53787 | 324 | while (1); |
1da177e4 LT |
325 | } |
326 | ||
a0616cde DH |
327 | /* |
328 | * Use to set psw mask except for the first byte which | |
329 | * won't be changed by this function. | |
330 | */ | |
331 | static inline void | |
332 | __set_psw_mask(unsigned long mask) | |
333 | { | |
334 | __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); | |
335 | } | |
336 | ||
337 | #define local_mcck_enable() \ | |
338 | __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK) | |
339 | #define local_mcck_disable() \ | |
340 | __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT) | |
341 | ||
ab14de6c HC |
342 | /* |
343 | * Basic Machine Check/Program Check Handler. | |
344 | */ | |
345 | ||
346 | extern void s390_base_mcck_handler(void); | |
347 | extern void s390_base_pgm_handler(void); | |
348 | extern void s390_base_ext_handler(void); | |
349 | ||
350 | extern void (*s390_base_mcck_handler_fn)(void); | |
351 | extern void (*s390_base_pgm_handler_fn)(void); | |
352 | extern void (*s390_base_ext_handler_fn)(void); | |
353 | ||
dfd54cbc HC |
354 | #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL |
355 | ||
fbe76568 HC |
356 | extern int memcpy_real(void *, void *, size_t); |
357 | extern void memcpy_absolute(void *, void *, size_t); | |
358 | ||
359 | #define mem_assign_absolute(dest, val) { \ | |
360 | __typeof__(dest) __tmp = (val); \ | |
361 | \ | |
362 | BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ | |
363 | memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ | |
364 | } | |
365 | ||
eb608fb3 HC |
366 | /* |
367 | * Helper macro for exception table entries | |
368 | */ | |
369 | #define EX_TABLE(_fault, _target) \ | |
370 | ".section __ex_table,\"a\"\n" \ | |
371 | ".align 4\n" \ | |
372 | ".long (" #_fault ") - .\n" \ | |
373 | ".long (" #_target ") - .\n" \ | |
374 | ".previous\n" | |
375 | ||
376 | #else /* __ASSEMBLY__ */ | |
377 | ||
378 | #define EX_TABLE(_fault, _target) \ | |
379 | .section __ex_table,"a" ; \ | |
380 | .align 4 ; \ | |
381 | .long (_fault) - . ; \ | |
382 | .long (_target) - . ; \ | |
383 | .previous | |
384 | ||
385 | #endif /* __ASSEMBLY__ */ | |
386 | ||
387 | #endif /* __ASM_S390_PROCESSOR_H */ |