Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
5 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
6 | * | |
7 | * Derived from "include/asm-i386/processor.h" | |
8 | * Copyright (C) 1994, Linus Torvalds | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_S390_PROCESSOR_H | |
12 | #define __ASM_S390_PROCESSOR_H | |
13 | ||
92778b99 HC |
14 | #include <linux/const.h> |
15 | ||
d3a73acb MS |
16 | #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ |
17 | #define CIF_ASCE 1 /* user asce needs fixup / uaccess */ | |
fe0f4976 | 18 | #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ |
b0753902 | 19 | #define CIF_FPU 3 /* restore FPU registers */ |
db7e007f | 20 | #define CIF_IGNORE_IRQ 4 /* ignore interrupt (for udelay) */ |
d3a73acb | 21 | |
92778b99 HC |
22 | #define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING) |
23 | #define _CIF_ASCE _BITUL(CIF_ASCE) | |
24 | #define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY) | |
25 | #define _CIF_FPU _BITUL(CIF_FPU) | |
26 | #define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ) | |
d3a73acb | 27 | |
eb608fb3 HC |
28 | #ifndef __ASSEMBLY__ |
29 | ||
edd53787 | 30 | #include <linux/linkage.h> |
a0616cde | 31 | #include <linux/irqflags.h> |
e86a6ed6 | 32 | #include <asm/cpu.h> |
25097bf1 | 33 | #include <asm/page.h> |
1da177e4 | 34 | #include <asm/ptrace.h> |
25097bf1 | 35 | #include <asm/setup.h> |
e4b8b3f3 | 36 | #include <asm/runtime_instr.h> |
b0753902 HB |
37 | #include <asm/fpu/types.h> |
38 | #include <asm/fpu/internal.h> | |
1da177e4 | 39 | |
d3a73acb MS |
40 | static inline void set_cpu_flag(int flag) |
41 | { | |
ac25e790 | 42 | S390_lowcore.cpu_flags |= (1UL << flag); |
d3a73acb MS |
43 | } |
44 | ||
45 | static inline void clear_cpu_flag(int flag) | |
46 | { | |
ac25e790 | 47 | S390_lowcore.cpu_flags &= ~(1UL << flag); |
d3a73acb MS |
48 | } |
49 | ||
50 | static inline int test_cpu_flag(int flag) | |
51 | { | |
ac25e790 | 52 | return !!(S390_lowcore.cpu_flags & (1UL << flag)); |
d3a73acb MS |
53 | } |
54 | ||
fe0f4976 MS |
55 | #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) |
56 | ||
1da177e4 LT |
57 | /* |
58 | * Default implementation of macro that returns current | |
59 | * instruction pointer ("program counter"). | |
60 | */ | |
94c12cc7 | 61 | #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) |
1da177e4 | 62 | |
e86a6ed6 | 63 | static inline void get_cpu_id(struct cpuid *ptr) |
72960a02 | 64 | { |
987bcdac | 65 | asm volatile("stidp %0" : "=Q" (*ptr)); |
72960a02 MH |
66 | } |
67 | ||
31ee4b2f | 68 | extern void s390_adjust_jiffies(void); |
638ad34a MS |
69 | extern const struct seq_operations cpuinfo_op; |
70 | extern int sysctl_ieee_emulation_warnings; | |
65f22a90 | 71 | extern void execve_tail(void); |
1da177e4 | 72 | |
1da177e4 | 73 | /* |
f481bfaf | 74 | * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. |
1da177e4 | 75 | */ |
1da177e4 | 76 | |
f481bfaf | 77 | #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) |
5a216a20 MS |
78 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ |
79 | (1UL << 30) : (1UL << 41)) | |
80 | #define TASK_SIZE TASK_SIZE_OF(current) | |
ee6ee55b | 81 | #define TASK_MAX_SIZE (1UL << 53) |
1da177e4 | 82 | |
6252d702 MS |
83 | #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) |
84 | #define STACK_TOP_MAX (1UL << 42) | |
922a70d3 | 85 | |
1da177e4 LT |
86 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
87 | ||
88 | typedef struct { | |
89 | __u32 ar4; | |
90 | } mm_segment_t; | |
91 | ||
92 | /* | |
93 | * Thread structure | |
94 | */ | |
95 | struct thread_struct { | |
904818e2 | 96 | struct fpu fpu; /* FP and VX register save area */ |
1da177e4 LT |
97 | unsigned int acrs[NUM_ACRS]; |
98 | unsigned long ksp; /* kernel stack pointer */ | |
1da177e4 | 99 | mm_segment_t mm_segment; |
e5992f2e | 100 | unsigned long gmap_addr; /* address of last gmap fault. */ |
24eb3a82 | 101 | unsigned int gmap_pfault; /* signal of a pending guest pfault */ |
5e9a2692 MS |
102 | struct per_regs per_user; /* User specified PER registers */ |
103 | struct per_event per_event; /* Cause of the last PER trap */ | |
d35339a4 | 104 | unsigned long per_flags; /* Flags to control debug behavior */ |
1da177e4 LT |
105 | /* pfault_wait is used to block the process on a pfault event */ |
106 | unsigned long pfault_wait; | |
f2db2e6c | 107 | struct list_head list; |
e4b8b3f3 JG |
108 | /* cpu runtime instrumentation */ |
109 | struct runtime_instr_cb *ri_cb; | |
110 | int ri_signum; | |
d35339a4 | 111 | unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ |
1da177e4 LT |
112 | }; |
113 | ||
64597f9d MM |
114 | /* Flag to disable transactions. */ |
115 | #define PER_FLAG_NO_TE 1UL | |
116 | /* Flag to enable random transaction aborts. */ | |
117 | #define PER_FLAG_TE_ABORT_RAND 2UL | |
118 | /* Flag to specify random transaction abort mode: | |
119 | * - abort each transaction at a random instruction before TEND if set. | |
120 | * - abort random transactions at a random instruction if cleared. | |
121 | */ | |
122 | #define PER_FLAG_TE_ABORT_RAND_TEND 4UL | |
d35339a4 | 123 | |
1da177e4 LT |
124 | typedef struct thread_struct thread_struct; |
125 | ||
126 | /* | |
127 | * Stack layout of a C stack frame. | |
128 | */ | |
129 | #ifndef __PACK_STACK | |
130 | struct stack_frame { | |
131 | unsigned long back_chain; | |
132 | unsigned long empty1[5]; | |
133 | unsigned long gprs[10]; | |
134 | unsigned int empty2[8]; | |
135 | }; | |
136 | #else | |
137 | struct stack_frame { | |
138 | unsigned long empty1[5]; | |
139 | unsigned int empty2[8]; | |
140 | unsigned long gprs[10]; | |
141 | unsigned long back_chain; | |
142 | }; | |
143 | #endif | |
144 | ||
145 | #define ARCH_MIN_TASKALIGN 8 | |
146 | ||
0ac27779 | 147 | extern __vector128 init_task_fpu_regs[__NUM_VXRS]; |
6f3fa3f0 MS |
148 | #define INIT_THREAD { \ |
149 | .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ | |
0ac27779 | 150 | .fpu.regs = (void *)&init_task_fpu_regs, \ |
6f3fa3f0 | 151 | } |
1da177e4 LT |
152 | |
153 | /* | |
154 | * Do necessary setup to start up a new thread. | |
155 | */ | |
b50511e4 | 156 | #define start_thread(regs, new_psw, new_stackp) do { \ |
e258d719 | 157 | regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ |
b50511e4 MS |
158 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ |
159 | regs->gprs[15] = new_stackp; \ | |
65f22a90 | 160 | execve_tail(); \ |
63506c41 MS |
161 | } while (0) |
162 | ||
b50511e4 | 163 | #define start_thread31(regs, new_psw, new_stackp) do { \ |
e258d719 | 164 | regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ |
b50511e4 MS |
165 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ |
166 | regs->gprs[15] = new_stackp; \ | |
167 | crst_table_downgrade(current->mm, 1UL << 31); \ | |
65f22a90 | 168 | execve_tail(); \ |
1da177e4 LT |
169 | } while (0) |
170 | ||
1da177e4 LT |
171 | /* Forward declaration, a strange C thing */ |
172 | struct task_struct; | |
173 | struct mm_struct; | |
df5f8314 | 174 | struct seq_file; |
1da177e4 | 175 | |
5a79859a | 176 | void show_cacheinfo(struct seq_file *m); |
6668022c | 177 | |
1da177e4 LT |
178 | /* Free all resources held by a thread. */ |
179 | extern void release_thread(struct task_struct *); | |
1da177e4 | 180 | |
1da177e4 LT |
181 | /* |
182 | * Return saved PC of a blocked thread. | |
183 | */ | |
184 | extern unsigned long thread_saved_pc(struct task_struct *t); | |
185 | ||
1da177e4 | 186 | unsigned long get_wchan(struct task_struct *p); |
c7584fb6 | 187 | #define task_pt_regs(tsk) ((struct pt_regs *) \ |
30af7120 | 188 | (task_stack_page(tsk) + THREAD_SIZE) - 1) |
c7584fb6 AV |
189 | #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) |
190 | #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) | |
1da177e4 | 191 | |
5ebf250d HC |
192 | /* Has task runtime instrumentation enabled ? */ |
193 | #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) | |
194 | ||
a0616cde DH |
195 | static inline unsigned short stap(void) |
196 | { | |
197 | unsigned short cpu_address; | |
198 | ||
199 | asm volatile("stap %0" : "=m" (cpu_address)); | |
200 | return cpu_address; | |
201 | } | |
202 | ||
1da177e4 LT |
203 | /* |
204 | * Give up the time slice of the virtual PU. | |
205 | */ | |
4d92f502 | 206 | void cpu_relax(void); |
1da177e4 | 207 | |
3a6bfbc9 | 208 | #define cpu_relax_lowlatency() barrier() |
083986e8 | 209 | |
dc74d7f9 HC |
210 | static inline void psw_set_key(unsigned int key) |
211 | { | |
212 | asm volatile("spka 0(%0)" : : "d" (key)); | |
213 | } | |
214 | ||
77fa2245 HC |
215 | /* |
216 | * Set PSW to specified value. | |
217 | */ | |
218 | static inline void __load_psw(psw_t psw) | |
219 | { | |
987bcdac | 220 | asm volatile("lpswe %0" : : "Q" (psw) : "cc"); |
77fa2245 HC |
221 | } |
222 | ||
1da177e4 LT |
223 | /* |
224 | * Set PSW mask to specified value, while leaving the | |
225 | * PSW addr pointing to the next instruction. | |
226 | */ | |
1da177e4 LT |
227 | static inline void __load_psw_mask (unsigned long mask) |
228 | { | |
229 | unsigned long addr; | |
1da177e4 | 230 | psw_t psw; |
77fa2245 | 231 | |
1da177e4 LT |
232 | psw.mask = mask; |
233 | ||
94c12cc7 MS |
234 | asm volatile( |
235 | " larl %0,1f\n" | |
987bcdac MS |
236 | " stg %0,%O1+8(%R1)\n" |
237 | " lpswe %1\n" | |
1da177e4 | 238 | "1:" |
987bcdac | 239 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
1da177e4 | 240 | } |
ccf45caf | 241 | |
22362a0e MS |
242 | /* |
243 | * Extract current PSW mask | |
244 | */ | |
245 | static inline unsigned long __extract_psw(void) | |
246 | { | |
247 | unsigned int reg1, reg2; | |
248 | ||
249 | asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); | |
250 | return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); | |
251 | } | |
252 | ||
ccf45caf MS |
253 | /* |
254 | * Rewind PSW instruction address by specified number of bytes. | |
255 | */ | |
256 | static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) | |
257 | { | |
ccf45caf MS |
258 | unsigned long mask; |
259 | ||
260 | mask = (psw.mask & PSW_MASK_EA) ? -1UL : | |
261 | (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : | |
262 | (1UL << 24) - 1; | |
263 | return (psw.addr - ilc) & mask; | |
ccf45caf | 264 | } |
b5f87f15 MS |
265 | |
266 | /* | |
267 | * Function to stop a processor until the next interrupt occurs | |
268 | */ | |
269 | void enabled_wait(void); | |
270 | ||
1da177e4 LT |
271 | /* |
272 | * Function to drop a processor into disabled wait state | |
273 | */ | |
ff2d8b19 | 274 | static inline void __noreturn disabled_wait(unsigned long code) |
1da177e4 | 275 | { |
1da177e4 | 276 | unsigned long ctl_buf; |
77fa2245 | 277 | psw_t dw_psw; |
1da177e4 | 278 | |
b50511e4 | 279 | dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; |
77fa2245 | 280 | dw_psw.addr = code; |
1da177e4 LT |
281 | /* |
282 | * Store status and then load disabled wait psw, | |
283 | * the processor is dead afterwards | |
284 | */ | |
94c12cc7 MS |
285 | asm volatile( |
286 | " stctg 0,0,0(%2)\n" | |
287 | " ni 4(%2),0xef\n" /* switch off protection */ | |
288 | " lctlg 0,0,0(%2)\n" | |
289 | " lghi 1,0x1000\n" | |
290 | " stpt 0x328(1)\n" /* store timer */ | |
291 | " stckc 0x330(1)\n" /* store clock comparator */ | |
292 | " stpx 0x318(1)\n" /* store prefix register */ | |
293 | " stam 0,15,0x340(1)\n"/* store access registers */ | |
294 | " stfpc 0x31c(1)\n" /* store fpu control */ | |
295 | " std 0,0x200(1)\n" /* store f0 */ | |
296 | " std 1,0x208(1)\n" /* store f1 */ | |
297 | " std 2,0x210(1)\n" /* store f2 */ | |
298 | " std 3,0x218(1)\n" /* store f3 */ | |
299 | " std 4,0x220(1)\n" /* store f4 */ | |
300 | " std 5,0x228(1)\n" /* store f5 */ | |
301 | " std 6,0x230(1)\n" /* store f6 */ | |
302 | " std 7,0x238(1)\n" /* store f7 */ | |
303 | " std 8,0x240(1)\n" /* store f8 */ | |
304 | " std 9,0x248(1)\n" /* store f9 */ | |
305 | " std 10,0x250(1)\n" /* store f10 */ | |
306 | " std 11,0x258(1)\n" /* store f11 */ | |
307 | " std 12,0x260(1)\n" /* store f12 */ | |
308 | " std 13,0x268(1)\n" /* store f13 */ | |
309 | " std 14,0x270(1)\n" /* store f14 */ | |
310 | " std 15,0x278(1)\n" /* store f15 */ | |
311 | " stmg 0,15,0x280(1)\n"/* store general registers */ | |
312 | " stctg 0,15,0x380(1)\n"/* store control registers */ | |
313 | " oi 0x384(1),0x10\n"/* fake protection bit */ | |
314 | " lpswe 0(%1)" | |
315 | : "=m" (ctl_buf) | |
bdd42b28 | 316 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1"); |
edd53787 | 317 | while (1); |
1da177e4 LT |
318 | } |
319 | ||
a0616cde DH |
320 | /* |
321 | * Use to set psw mask except for the first byte which | |
322 | * won't be changed by this function. | |
323 | */ | |
324 | static inline void | |
325 | __set_psw_mask(unsigned long mask) | |
326 | { | |
327 | __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); | |
328 | } | |
329 | ||
330 | #define local_mcck_enable() \ | |
e258d719 | 331 | __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK) |
a0616cde | 332 | #define local_mcck_disable() \ |
e258d719 | 333 | __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT) |
a0616cde | 334 | |
ab14de6c HC |
335 | /* |
336 | * Basic Machine Check/Program Check Handler. | |
337 | */ | |
338 | ||
339 | extern void s390_base_mcck_handler(void); | |
340 | extern void s390_base_pgm_handler(void); | |
341 | extern void s390_base_ext_handler(void); | |
342 | ||
343 | extern void (*s390_base_mcck_handler_fn)(void); | |
344 | extern void (*s390_base_pgm_handler_fn)(void); | |
345 | extern void (*s390_base_ext_handler_fn)(void); | |
346 | ||
dfd54cbc HC |
347 | #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL |
348 | ||
fbe76568 HC |
349 | extern int memcpy_real(void *, void *, size_t); |
350 | extern void memcpy_absolute(void *, void *, size_t); | |
351 | ||
352 | #define mem_assign_absolute(dest, val) { \ | |
353 | __typeof__(dest) __tmp = (val); \ | |
354 | \ | |
355 | BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ | |
356 | memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ | |
357 | } | |
358 | ||
eb608fb3 HC |
359 | #endif /* __ASSEMBLY__ */ |
360 | ||
361 | #endif /* __ASM_S390_PROCESSOR_H */ |