[deliverable/linux.git] / arch / s390 / include / asm / processor.h

/*
 *  S390 version
 *    Copyright IBM Corp. 1999
 *    Author(s): Hartmut Penner (hp@de.ibm.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *
 *  Derived from "include/asm-i386/processor.h"
 *    Copyright (C) 1994, Linus Torvalds
 */

#ifndef __ASM_S390_PROCESSOR_H
#define __ASM_S390_PROCESSOR_H

#ifndef __ASSEMBLY__

#include <linux/linkage.h>
#include <linux/irqflags.h>
#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/runtime_instr.h>

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })

static inline void get_cpu_id(struct cpuid *ptr)
{
	asm volatile("stidp %0" : "=Q" (*ptr));
}

extern void s390_adjust_jiffies(void);
extern const struct seq_operations cpuinfo_op;
extern int sysctl_ieee_emulation_warnings;
extern void execve_tail(void);

/*
 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
 */
#ifndef CONFIG_64BIT

#define TASK_SIZE		(1UL << 31)
#define TASK_UNMAPPED_BASE	(1UL << 30)

#else /* CONFIG_64BIT */

#define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
#define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
					(1UL << 30) : (1UL << 41))
#define TASK_SIZE		TASK_SIZE_OF(current)

#endif /* CONFIG_64BIT */

#ifndef CONFIG_64BIT
#define STACK_TOP		(1UL << 31)
#define STACK_TOP_MAX		(1UL << 31)
#else /* CONFIG_64BIT */
#define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
#define STACK_TOP_MAX		(1UL << 42)
#endif /* CONFIG_64BIT */

#define HAVE_ARCH_PICK_MMAP_LAYOUT

typedef struct {
        __u32 ar4;
} mm_segment_t;

/*
 * Thread structure
 */
struct thread_struct {
	s390_fp_regs fp_regs;
	unsigned int  acrs[NUM_ACRS];
        unsigned long ksp;              /* kernel stack pointer             */
	mm_segment_t mm_segment;
	unsigned long gmap_addr;	/* address of last gmap fault. */
	struct per_regs per_user;	/* User specified PER registers */
	struct per_event per_event;	/* Cause of the last PER trap */
	unsigned long per_flags;	/* Flags to control debug behavior */
        /* pfault_wait is used to block the process on a pfault event */
	unsigned long pfault_wait;
	struct list_head list;
	/* cpu runtime instrumentation */
	struct runtime_instr_cb *ri_cb;
	int ri_signum;
#ifdef CONFIG_64BIT
	unsigned char trap_tdb[256];	/* Transaction abort diagnose block */
#endif
};

/* Flag to disable transactions. */
#define PER_FLAG_NO_TE			1UL
/* Flag to enable random transaction aborts. */
#define PER_FLAG_TE_ABORT_RAND		2UL
/* Flag to specify random transaction abort mode:
 * - abort each transaction at a random instruction before TEND if set.
 * - abort random transactions at a random instruction if cleared.
 */
#define PER_FLAG_TE_ABORT_RAND_TEND	4UL

typedef struct thread_struct thread_struct;

/*
 * Stack layout of a C stack frame.
 */
#ifndef __PACK_STACK
struct stack_frame {
	unsigned long back_chain;
	unsigned long empty1[5];
	unsigned long gprs[10];
	unsigned int  empty2[8];
};
#else
struct stack_frame {
	unsigned long empty1[5];
	unsigned int  empty2[8];
	unsigned long gprs[10];
	unsigned long back_chain;
};
#endif

#define ARCH_MIN_TASKALIGN	8

#define INIT_THREAD {							\
	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
}

/*
 * Do necessary setup to start up a new thread.
 */
#define start_thread(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= psw_user_bits | PSW_MASK_EA | PSW_MASK_BA;	\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	execve_tail();							\
} while (0)

#define start_thread31(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= psw_user_bits | PSW_MASK_BA;			\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	__tlb_flush_mm(current->mm);					\
	crst_table_downgrade(current->mm, 1UL << 31);			\
	update_mm(current->mm, current);				\
	execve_tail();							\
} while (0)

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
struct seq_file;

#ifdef CONFIG_64BIT
extern void show_cacheinfo(struct seq_file *m);
#else
static inline void show_cacheinfo(struct seq_file *m) { }
#endif

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);

/*
 * Return saved PC of a blocked thread.
 */
extern unsigned long thread_saved_pc(struct task_struct *t);

extern void show_code(struct pt_regs *regs);
extern void print_fn_code(unsigned char *code, unsigned long len);
extern int insn_to_mnemonic(unsigned char *instruction, char *buf,
			    unsigned int len);

unsigned long get_wchan(struct task_struct *p);
#define task_pt_regs(tsk) ((struct pt_regs *) \
        (task_stack_page(tsk) + THREAD_SIZE) - 1)
#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])

static inline unsigned short stap(void)
{
	unsigned short cpu_address;

	asm volatile("stap %0" : "=m" (cpu_address));
	return cpu_address;
}

/*
 * Give up the time slice of the virtual PU.
 */
static inline void cpu_relax(void)
{
	if (MACHINE_HAS_DIAG44)
		asm volatile("diag 0,0,68");
	barrier();
}

static inline void psw_set_key(unsigned int key)
{
	asm volatile("spka 0(%0)" : : "d" (key));
}

/*
 * Set PSW to specified value.
 */
static inline void __load_psw(psw_t psw)
{
#ifndef CONFIG_64BIT
	asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
#else
	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
#endif
}

/*
 * Set PSW mask to specified value, while leaving the
 * PSW addr pointing to the next instruction.
 */
static inline void __load_psw_mask (unsigned long mask)
{
	unsigned long addr;
	psw_t psw;

	psw.mask = mask;

#ifndef CONFIG_64BIT
	asm volatile(
		"	basr	%0,0\n"
		"0:	ahi	%0,1f-0b\n"
		"	st	%0,%O1+4(%R1)\n"
		"	lpsw	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
#else /* CONFIG_64BIT */
	asm volatile(
		"	larl	%0,1f\n"
		"	stg	%0,%O1+8(%R1)\n"
		"	lpswe	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
#endif /* CONFIG_64BIT */
}

/*
 * Rewind PSW instruction address by specified number of bytes.
 */
static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
{
#ifndef CONFIG_64BIT
	if (psw.addr & PSW_ADDR_AMODE)
		/* 31 bit mode */
		return (psw.addr - ilc) | PSW_ADDR_AMODE;
	/* 24 bit mode */
	return (psw.addr - ilc) & ((1UL << 24) - 1);
#else
	unsigned long mask;

	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
					  (1UL << 24) - 1;
	return (psw.addr - ilc) & mask;
#endif
}
 
/*
 * Function to drop a processor into disabled wait state
 */
static inline void __noreturn disabled_wait(unsigned long code)
{
        unsigned long ctl_buf;
        psw_t dw_psw;

	dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
        dw_psw.addr = code;
        /* 
         * Store status and then load disabled wait psw,
         * the processor is dead afterwards
         */
#ifndef CONFIG_64BIT
	asm volatile(
		"	stctl	0,0,0(%2)\n"
		"	ni	0(%2),0xef\n"	/* switch off protection */
		"	lctl	0,0,0(%2)\n"
		"	stpt	0xd8\n"		/* store timer */
		"	stckc	0xe0\n"		/* store clock comparator */
		"	stpx	0x108\n"	/* store prefix register */
		"	stam	0,15,0x120\n"	/* store access registers */
		"	std	0,0x160\n"	/* store f0 */
		"	std	2,0x168\n"	/* store f2 */
		"	std	4,0x170\n"	/* store f4 */
		"	std	6,0x178\n"	/* store f6 */
		"	stm	0,15,0x180\n"	/* store general registers */
		"	stctl	0,15,0x1c0\n"	/* store control registers */
		"	oi	0x1c0,0x10\n"	/* fake protection bit */
		"	lpsw	0(%1)"
		: "=m" (ctl_buf)
		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
#else /* CONFIG_64BIT */
	asm volatile(
		"	stctg	0,0,0(%2)\n"
		"	ni	4(%2),0xef\n"	/* switch off protection */
		"	lctlg	0,0,0(%2)\n"
		"	lghi	1,0x1000\n"
		"	stpt	0x328(1)\n"	/* store timer */
		"	stckc	0x330(1)\n"	/* store clock comparator */
		"	stpx	0x318(1)\n"	/* store prefix register */
		"	stam	0,15,0x340(1)\n"/* store access registers */
		"	stfpc	0x31c(1)\n"	/* store fpu control */
		"	std	0,0x200(1)\n"	/* store f0 */
		"	std	1,0x208(1)\n"	/* store f1 */
		"	std	2,0x210(1)\n"	/* store f2 */
		"	std	3,0x218(1)\n"	/* store f3 */
		"	std	4,0x220(1)\n"	/* store f4 */
		"	std	5,0x228(1)\n"	/* store f5 */
		"	std	6,0x230(1)\n"	/* store f6 */
		"	std	7,0x238(1)\n"	/* store f7 */
		"	std	8,0x240(1)\n"	/* store f8 */
		"	std	9,0x248(1)\n"	/* store f9 */
		"	std	10,0x250(1)\n"	/* store f10 */
		"	std	11,0x258(1)\n"	/* store f11 */
		"	std	12,0x260(1)\n"	/* store f12 */
		"	std	13,0x268(1)\n"	/* store f13 */
		"	std	14,0x270(1)\n"	/* store f14 */
		"	std	15,0x278(1)\n"	/* store f15 */
		"	stmg	0,15,0x280(1)\n"/* store general registers */
		"	stctg	0,15,0x380(1)\n"/* store control registers */
		"	oi	0x384(1),0x10\n"/* fake protection bit */
		"	lpswe	0(%1)"
		: "=m" (ctl_buf)
		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
#endif /* CONFIG_64BIT */
	while (1);
}

/*
 * Use to set psw mask except for the first byte which
 * won't be changed by this function.
 */
static inline void
__set_psw_mask(unsigned long mask)
{
	__load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
}

#define local_mcck_enable() \
	__set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK)
#define local_mcck_disable() \
	__set_psw_mask(psw_kernel_bits | PSW_MASK_DAT)

/*
 * Basic Machine Check/Program Check Handler.
 */

extern void s390_base_mcck_handler(void);
extern void s390_base_pgm_handler(void);
extern void s390_base_ext_handler(void);

extern void (*s390_base_mcck_handler_fn)(void);
extern void (*s390_base_pgm_handler_fn)(void);
extern void (*s390_base_ext_handler_fn)(void);

#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL

extern int memcpy_real(void *, void *, size_t);
extern void memcpy_absolute(void *, void *, size_t);

#define mem_assign_absolute(dest, val) {			\
	__typeof__(dest) __tmp = (val);				\
								\
	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));		\
	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));	\
}

/*
 * Helper macro for exception table entries
 */
#define EX_TABLE(_fault, _target)	\
	".section __ex_table,\"a\"\n"	\
	".align	4\n"			\
	".long	(" #_fault ") - .\n"	\
	".long	(" #_target ") - .\n"	\
	".previous\n"

#else /* __ASSEMBLY__ */

#define EX_TABLE(_fault, _target)	\
	.section __ex_table,"a"	;	\
	.align	4 ;			\
	.long	(_fault) - . ;		\
	.long	(_target) - . ;		\
	.previous

#endif /* __ASSEMBLY__ */

#endif /* __ASM_S390_PROCESSOR_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* S390 version
a53c8fab	3	* Copyright IBM Corp. 1999
1da177e4 LT	4	* Author(s): Hartmut Penner (hp@de.ibm.com),
	5	* Martin Schwidefsky (schwidefsky@de.ibm.com)
	6	*
	7	* Derived from "include/asm-i386/processor.h"
	8	* Copyright (C) 1994, Linus Torvalds
	9	*/
	10
	11	#ifndef __ASM_S390_PROCESSOR_H
	12	#define __ASM_S390_PROCESSOR_H
	13
eb608fb3 HC	14	#ifndef __ASSEMBLY__
eb608fb3 HC	15
edd53787	16	#include <linux/linkage.h>
a0616cde	17	#include <linux/irqflags.h>
e86a6ed6	18	#include <asm/cpu.h>
25097bf1	19	#include <asm/page.h>
1da177e4	20	#include <asm/ptrace.h>
25097bf1	21	#include <asm/setup.h>
e4b8b3f3	22	#include <asm/runtime_instr.h>
1da177e4	23
1da177e4 LT	24	/*
	25	* Default implementation of macro that returns current
	26	* instruction pointer ("program counter").
	27	*/
94c12cc7	28	#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
1da177e4	29
e86a6ed6	30	static inline void get_cpu_id(struct cpuid *ptr)
72960a02	31	{
987bcdac	32	asm volatile("stidp %0" : "=Q" (*ptr));
72960a02 MH	33	}
72960a02 MH	34
31ee4b2f	35	extern void s390_adjust_jiffies(void);
638ad34a MS	36	extern const struct seq_operations cpuinfo_op;
638ad34a MS	37	extern int sysctl_ieee_emulation_warnings;
65f22a90	38	extern void execve_tail(void);
1da177e4	39
1da177e4	40	/*
f481bfaf	41	* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
1da177e4	42	*/
f4815ac6	43	#ifndef CONFIG_64BIT
1da177e4	44
5a216a20 MS	45	#define TASK_SIZE (1UL << 31)
5a216a20 MS	46	#define TASK_UNMAPPED_BASE (1UL << 30)
1da177e4	47
f4815ac6	48	#else /* CONFIG_64BIT */
1da177e4	49
f481bfaf	50	#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
5a216a20 MS	51	#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
	52	(1UL << 30) : (1UL << 41))
	53	#define TASK_SIZE TASK_SIZE_OF(current)
1da177e4	54
f4815ac6	55	#endif /* CONFIG_64BIT */
1da177e4	56
f4815ac6	57	#ifndef CONFIG_64BIT
5a216a20	58	#define STACK_TOP (1UL << 31)
6252d702	59	#define STACK_TOP_MAX (1UL << 31)
f4815ac6	60	#else /* CONFIG_64BIT */
6252d702 MS	61	#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
6252d702 MS	62	#define STACK_TOP_MAX (1UL << 42)
f4815ac6	63	#endif /* CONFIG_64BIT */
922a70d3	64
1da177e4 LT	65	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	66
	67	typedef struct {
	68	__u32 ar4;
	69	} mm_segment_t;
	70
	71	/*
	72	* Thread structure
	73	*/
	74	struct thread_struct {
	75	s390_fp_regs fp_regs;
	76	unsigned int acrs[NUM_ACRS];
	77	unsigned long ksp; /* kernel stack pointer */
1da177e4	78	mm_segment_t mm_segment;
e5992f2e	79	unsigned long gmap_addr; /* address of last gmap fault. */
5e9a2692 MS	80	struct per_regs per_user; /* User specified PER registers */
5e9a2692 MS	81	struct per_event per_event; /* Cause of the last PER trap */
d35339a4	82	unsigned long per_flags; /* Flags to control debug behavior */
1da177e4 LT	83	/* pfault_wait is used to block the process on a pfault event */
1da177e4 LT	84	unsigned long pfault_wait;
f2db2e6c	85	struct list_head list;
e4b8b3f3 JG	86	/* cpu runtime instrumentation */
	87	struct runtime_instr_cb *ri_cb;
	88	int ri_signum;
d35339a4 MS	89	#ifdef CONFIG_64BIT
	90	unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
	91	#endif
1da177e4 LT	92	};
1da177e4 LT	93
64597f9d MM	94	/* Flag to disable transactions. */
	95	#define PER_FLAG_NO_TE 1UL
	96	/* Flag to enable random transaction aborts. */
	97	#define PER_FLAG_TE_ABORT_RAND 2UL
	98	/* Flag to specify random transaction abort mode:
	99	* - abort each transaction at a random instruction before TEND if set.
	100	* - abort random transactions at a random instruction if cleared.
	101	*/
	102	#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
d35339a4	103
1da177e4 LT	104	typedef struct thread_struct thread_struct;
	105
	106	/*
	107	* Stack layout of a C stack frame.
	108	*/
	109	#ifndef __PACK_STACK
	110	struct stack_frame {
	111	unsigned long back_chain;
	112	unsigned long empty1[5];
	113	unsigned long gprs[10];
	114	unsigned int empty2[8];
	115	};
	116	#else
	117	struct stack_frame {
	118	unsigned long empty1[5];
	119	unsigned int empty2[8];
	120	unsigned long gprs[10];
	121	unsigned long back_chain;
	122	};
	123	#endif
	124
	125	#define ARCH_MIN_TASKALIGN 8
	126
6f3fa3f0 MS	127	#define INIT_THREAD { \
	128	.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
	129	}
1da177e4 LT	130
	131	/*
	132	* Do necessary setup to start up a new thread.
	133	*/
b50511e4 MS	134	#define start_thread(regs, new_psw, new_stackp) do { \
	135	regs->psw.mask = psw_user_bits \| PSW_MASK_EA \| PSW_MASK_BA; \
	136	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
	137	regs->gprs[15] = new_stackp; \
65f22a90	138	execve_tail(); \
63506c41 MS	139	} while (0)
63506c41 MS	140
b50511e4 MS	141	#define start_thread31(regs, new_psw, new_stackp) do { \
	142	regs->psw.mask = psw_user_bits \| PSW_MASK_BA; \
	143	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
	144	regs->gprs[15] = new_stackp; \
0f6f281b	145	__tlb_flush_mm(current->mm); \
b50511e4	146	crst_table_downgrade(current->mm, 1UL << 31); \
0f6f281b	147	update_mm(current->mm, current); \
65f22a90	148	execve_tail(); \
1da177e4 LT	149	} while (0)
1da177e4 LT	150
1da177e4 LT	151	/* Forward declaration, a strange C thing */
	152	struct task_struct;
	153	struct mm_struct;
df5f8314	154	struct seq_file;
1da177e4	155
6668022c HC	156	#ifdef CONFIG_64BIT
	157	extern void show_cacheinfo(struct seq_file *m);
	158	#else
	159	static inline void show_cacheinfo(struct seq_file *m) { }
	160	#endif
	161
1da177e4 LT	162	/* Free all resources held by a thread. */
1da177e4 LT	163	extern void release_thread(struct task_struct *);
1da177e4	164
1da177e4 LT	165	/*
	166	* Return saved PC of a blocked thread.
	167	*/
	168	extern unsigned long thread_saved_pc(struct task_struct *t);
	169
bb11e3bd	170	extern void show_code(struct pt_regs *regs);
c10302ef	171	extern void print_fn_code(unsigned char *code, unsigned long len);
0bcc94ba SR	172	extern int insn_to_mnemonic(unsigned char instruction, char buf,
0bcc94ba SR	173	unsigned int len);
1da177e4 LT	174
1da177e4 LT	175	unsigned long get_wchan(struct task_struct *p);
c7584fb6	176	#define task_pt_regs(tsk) ((struct pt_regs *) \
30af7120	177	(task_stack_page(tsk) + THREAD_SIZE) - 1)
c7584fb6 AV	178	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
c7584fb6 AV	179	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
1da177e4	180
a0616cde DH	181	static inline unsigned short stap(void)
	182	{
	183	unsigned short cpu_address;
	184
	185	asm volatile("stap %0" : "=m" (cpu_address));
	186	return cpu_address;
	187	}
	188
1da177e4 LT	189	/*
	190	* Give up the time slice of the virtual PU.
	191	*/
abdba61a HC	192	static inline void cpu_relax(void)
	193	{
	194	if (MACHINE_HAS_DIAG44)
c48e0913 HC	195	asm volatile("diag 0,0,68");
c48e0913 HC	196	barrier();
abdba61a	197	}
1da177e4	198
dc74d7f9 HC	199	static inline void psw_set_key(unsigned int key)
	200	{
	201	asm volatile("spka 0(%0)" : : "d" (key));
	202	}
	203
77fa2245 HC	204	/*
	205	* Set PSW to specified value.
	206	*/
	207	static inline void __load_psw(psw_t psw)
	208	{
f4815ac6	209	#ifndef CONFIG_64BIT
987bcdac	210	asm volatile("lpsw %0" : : "Q" (psw) : "cc");
77fa2245	211	#else
987bcdac	212	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
77fa2245 HC	213	#endif
	214	}
	215
1da177e4 LT	216	/*
	217	* Set PSW mask to specified value, while leaving the
	218	* PSW addr pointing to the next instruction.
	219	*/
1da177e4 LT	220	static inline void __load_psw_mask (unsigned long mask)
	221	{
	222	unsigned long addr;
1da177e4	223	psw_t psw;
77fa2245	224
1da177e4 LT	225	psw.mask = mask;
1da177e4 LT	226
f4815ac6	227	#ifndef CONFIG_64BIT
94c12cc7 MS	228	asm volatile(
	229	" basr %0,0\n"
	230	"0: ahi %0,1f-0b\n"
987bcdac MS	231	" st %0,%O1+4(%R1)\n"
987bcdac MS	232	" lpsw %1\n"
1da177e4	233	"1:"
987bcdac	234	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
f4815ac6	235	#else /* CONFIG_64BIT */
94c12cc7 MS	236	asm volatile(
94c12cc7 MS	237	" larl %0,1f\n"
987bcdac MS	238	" stg %0,%O1+8(%R1)\n"
987bcdac MS	239	" lpswe %1\n"
1da177e4	240	"1:"
987bcdac	241	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
f4815ac6	242	#endif /* CONFIG_64BIT */
1da177e4	243	}
ccf45caf MS	244
	245	/*
	246	* Rewind PSW instruction address by specified number of bytes.
	247	*/
	248	static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
	249	{
f4815ac6	250	#ifndef CONFIG_64BIT
ccf45caf MS	251	if (psw.addr & PSW_ADDR_AMODE)
	252	/* 31 bit mode */
	253	return (psw.addr - ilc) \| PSW_ADDR_AMODE;
	254	/* 24 bit mode */
	255	return (psw.addr - ilc) & ((1UL << 24) - 1);
	256	#else
	257	unsigned long mask;
	258
	259	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	260	(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
	261	(1UL << 24) - 1;
	262	return (psw.addr - ilc) & mask;
	263	#endif
	264	}
1da177e4	265
1da177e4 LT	266	/*
	267	* Function to drop a processor into disabled wait state
	268	*/
ff2d8b19	269	static inline void __noreturn disabled_wait(unsigned long code)
1da177e4	270	{
1da177e4	271	unsigned long ctl_buf;
77fa2245	272	psw_t dw_psw;
1da177e4	273
b50511e4	274	dw_psw.mask = PSW_MASK_BASE \| PSW_MASK_WAIT \| PSW_MASK_BA \| PSW_MASK_EA;
77fa2245	275	dw_psw.addr = code;
1da177e4 LT	276	/*
	277	* Store status and then load disabled wait psw,
	278	* the processor is dead afterwards
	279	*/
f4815ac6	280	#ifndef CONFIG_64BIT
94c12cc7 MS	281	asm volatile(
	282	" stctl 0,0,0(%2)\n"
	283	" ni 0(%2),0xef\n" /* switch off protection */
	284	" lctl 0,0,0(%2)\n"
	285	" stpt 0xd8\n" /* store timer */
	286	" stckc 0xe0\n" /* store clock comparator */
	287	" stpx 0x108\n" /* store prefix register */
	288	" stam 0,15,0x120\n" /* store access registers */
	289	" std 0,0x160\n" /* store f0 */
	290	" std 2,0x168\n" /* store f2 */
	291	" std 4,0x170\n" /* store f4 */
	292	" std 6,0x178\n" /* store f6 */
	293	" stm 0,15,0x180\n" /* store general registers */
	294	" stctl 0,15,0x1c0\n" /* store control registers */
	295	" oi 0x1c0,0x10\n" /* fake protection bit */
	296	" lpsw 0(%1)"
	297	: "=m" (ctl_buf)
	298	: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
f4815ac6	299	#else /* CONFIG_64BIT */
94c12cc7 MS	300	asm volatile(
	301	" stctg 0,0,0(%2)\n"
	302	" ni 4(%2),0xef\n" /* switch off protection */
	303	" lctlg 0,0,0(%2)\n"
	304	" lghi 1,0x1000\n"
	305	" stpt 0x328(1)\n" /* store timer */
	306	" stckc 0x330(1)\n" /* store clock comparator */
	307	" stpx 0x318(1)\n" /* store prefix register */
	308	" stam 0,15,0x340(1)\n"/* store access registers */
	309	" stfpc 0x31c(1)\n" /* store fpu control */
	310	" std 0,0x200(1)\n" /* store f0 */
	311	" std 1,0x208(1)\n" /* store f1 */
	312	" std 2,0x210(1)\n" /* store f2 */
	313	" std 3,0x218(1)\n" /* store f3 */
	314	" std 4,0x220(1)\n" /* store f4 */
	315	" std 5,0x228(1)\n" /* store f5 */
	316	" std 6,0x230(1)\n" /* store f6 */
	317	" std 7,0x238(1)\n" /* store f7 */
	318	" std 8,0x240(1)\n" /* store f8 */
	319	" std 9,0x248(1)\n" /* store f9 */
	320	" std 10,0x250(1)\n" /* store f10 */
	321	" std 11,0x258(1)\n" /* store f11 */
	322	" std 12,0x260(1)\n" /* store f12 */
	323	" std 13,0x268(1)\n" /* store f13 */
	324	" std 14,0x270(1)\n" /* store f14 */
	325	" std 15,0x278(1)\n" /* store f15 */
	326	" stmg 0,15,0x280(1)\n"/* store general registers */
	327	" stctg 0,15,0x380(1)\n"/* store control registers */
	328	" oi 0x384(1),0x10\n"/* fake protection bit */
	329	" lpswe 0(%1)"
	330	: "=m" (ctl_buf)
bdd42b28	331	: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
f4815ac6	332	#endif /* CONFIG_64BIT */
edd53787	333	while (1);
1da177e4 LT	334	}
1da177e4 LT	335
a0616cde DH	336	/*
	337	* Use to set psw mask except for the first byte which
	338	* won't be changed by this function.
	339	*/
	340	static inline void
	341	__set_psw_mask(unsigned long mask)
	342	{
	343	__load_psw_mask(mask \| (arch_local_save_flags() & ~(-1UL >> 8)));
	344	}
	345
	346	#define local_mcck_enable() \
	347	__set_psw_mask(psw_kernel_bits \| PSW_MASK_DAT \| PSW_MASK_MCHECK)
	348	#define local_mcck_disable() \
	349	__set_psw_mask(psw_kernel_bits \| PSW_MASK_DAT)
	350
ab14de6c HC	351	/*
	352	* Basic Machine Check/Program Check Handler.
	353	*/
	354
	355	extern void s390_base_mcck_handler(void);
	356	extern void s390_base_pgm_handler(void);
	357	extern void s390_base_ext_handler(void);
	358
	359	extern void (*s390_base_mcck_handler_fn)(void);
	360	extern void (*s390_base_pgm_handler_fn)(void);
	361	extern void (*s390_base_ext_handler_fn)(void);
	362
dfd54cbc HC	363	#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
dfd54cbc HC	364
fbe76568 HC	365	extern int memcpy_real(void , void , size_t);
	366	extern void memcpy_absolute(void , void , size_t);
	367
	368	#define mem_assign_absolute(dest, val) { \
	369	__typeof__(dest) __tmp = (val); \
	370	\
	371	BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
	372	memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
	373	}
	374
eb608fb3 HC	375	/*
	376	* Helper macro for exception table entries
	377	*/
	378	#define EX_TABLE(_fault, _target) \
	379	".section __ex_table,\"a\"\n" \
	380	".align 4\n" \
	381	".long (" #_fault ") - .\n" \
	382	".long (" #_target ") - .\n" \
	383	".previous\n"
	384
	385	#else /* __ASSEMBLY__ */
	386
	387	#define EX_TABLE(_fault, _target) \
	388	.section __ex_table,"a" ; \
	389	.align 4 ; \
	390	.long (_fault) - . ; \
	391	.long (_target) - . ; \
	392	.previous
	393
	394	#endif /* __ASSEMBLY__ */
	395
	396	#endif /* __ASM_S390_PROCESSOR_H */