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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/processor.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Hartmut Penner (hp@de.ibm.com), | |
7 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
8 | * | |
9 | * Derived from "include/asm-i386/processor.h" | |
10 | * Copyright (C) 1994, Linus Torvalds | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_S390_PROCESSOR_H | |
14 | #define __ASM_S390_PROCESSOR_H | |
15 | ||
edd53787 | 16 | #include <linux/linkage.h> |
a0616cde | 17 | #include <linux/irqflags.h> |
e86a6ed6 | 18 | #include <asm/cpu.h> |
25097bf1 | 19 | #include <asm/page.h> |
1da177e4 | 20 | #include <asm/ptrace.h> |
25097bf1 | 21 | #include <asm/setup.h> |
1da177e4 | 22 | |
1da177e4 LT |
23 | /* |
24 | * Default implementation of macro that returns current | |
25 | * instruction pointer ("program counter"). | |
26 | */ | |
94c12cc7 | 27 | #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) |
1da177e4 | 28 | |
e86a6ed6 | 29 | static inline void get_cpu_id(struct cpuid *ptr) |
72960a02 | 30 | { |
987bcdac | 31 | asm volatile("stidp %0" : "=Q" (*ptr)); |
72960a02 MH |
32 | } |
33 | ||
31ee4b2f | 34 | extern void s390_adjust_jiffies(void); |
638ad34a MS |
35 | extern const struct seq_operations cpuinfo_op; |
36 | extern int sysctl_ieee_emulation_warnings; | |
1da177e4 | 37 | |
1da177e4 | 38 | /* |
f481bfaf | 39 | * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. |
1da177e4 | 40 | */ |
f4815ac6 | 41 | #ifndef CONFIG_64BIT |
1da177e4 | 42 | |
5a216a20 MS |
43 | #define TASK_SIZE (1UL << 31) |
44 | #define TASK_UNMAPPED_BASE (1UL << 30) | |
1da177e4 | 45 | |
f4815ac6 | 46 | #else /* CONFIG_64BIT */ |
1da177e4 | 47 | |
f481bfaf | 48 | #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) |
5a216a20 MS |
49 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ |
50 | (1UL << 30) : (1UL << 41)) | |
51 | #define TASK_SIZE TASK_SIZE_OF(current) | |
1da177e4 | 52 | |
f4815ac6 | 53 | #endif /* CONFIG_64BIT */ |
1da177e4 | 54 | |
f4815ac6 | 55 | #ifndef CONFIG_64BIT |
5a216a20 | 56 | #define STACK_TOP (1UL << 31) |
6252d702 | 57 | #define STACK_TOP_MAX (1UL << 31) |
f4815ac6 | 58 | #else /* CONFIG_64BIT */ |
6252d702 MS |
59 | #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) |
60 | #define STACK_TOP_MAX (1UL << 42) | |
f4815ac6 | 61 | #endif /* CONFIG_64BIT */ |
922a70d3 | 62 | |
1da177e4 LT |
63 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
64 | ||
65 | typedef struct { | |
66 | __u32 ar4; | |
67 | } mm_segment_t; | |
68 | ||
69 | /* | |
70 | * Thread structure | |
71 | */ | |
72 | struct thread_struct { | |
73 | s390_fp_regs fp_regs; | |
74 | unsigned int acrs[NUM_ACRS]; | |
75 | unsigned long ksp; /* kernel stack pointer */ | |
1da177e4 | 76 | mm_segment_t mm_segment; |
e5992f2e | 77 | unsigned long gmap_addr; /* address of last gmap fault. */ |
5e9a2692 MS |
78 | struct per_regs per_user; /* User specified PER registers */ |
79 | struct per_event per_event; /* Cause of the last PER trap */ | |
1da177e4 LT |
80 | /* pfault_wait is used to block the process on a pfault event */ |
81 | unsigned long pfault_wait; | |
f2db2e6c | 82 | struct list_head list; |
1da177e4 LT |
83 | }; |
84 | ||
85 | typedef struct thread_struct thread_struct; | |
86 | ||
87 | /* | |
88 | * Stack layout of a C stack frame. | |
89 | */ | |
90 | #ifndef __PACK_STACK | |
91 | struct stack_frame { | |
92 | unsigned long back_chain; | |
93 | unsigned long empty1[5]; | |
94 | unsigned long gprs[10]; | |
95 | unsigned int empty2[8]; | |
96 | }; | |
97 | #else | |
98 | struct stack_frame { | |
99 | unsigned long empty1[5]; | |
100 | unsigned int empty2[8]; | |
101 | unsigned long gprs[10]; | |
102 | unsigned long back_chain; | |
103 | }; | |
104 | #endif | |
105 | ||
106 | #define ARCH_MIN_TASKALIGN 8 | |
107 | ||
6f3fa3f0 MS |
108 | #define INIT_THREAD { \ |
109 | .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ | |
110 | } | |
1da177e4 LT |
111 | |
112 | /* | |
113 | * Do necessary setup to start up a new thread. | |
114 | */ | |
b50511e4 MS |
115 | #define start_thread(regs, new_psw, new_stackp) do { \ |
116 | regs->psw.mask = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA; \ | |
117 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ | |
118 | regs->gprs[15] = new_stackp; \ | |
63506c41 MS |
119 | } while (0) |
120 | ||
b50511e4 MS |
121 | #define start_thread31(regs, new_psw, new_stackp) do { \ |
122 | regs->psw.mask = psw_user_bits | PSW_MASK_BA; \ | |
123 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ | |
124 | regs->gprs[15] = new_stackp; \ | |
125 | crst_table_downgrade(current->mm, 1UL << 31); \ | |
1da177e4 LT |
126 | } while (0) |
127 | ||
1da177e4 LT |
128 | /* Forward declaration, a strange C thing */ |
129 | struct task_struct; | |
130 | struct mm_struct; | |
df5f8314 | 131 | struct seq_file; |
1da177e4 LT |
132 | |
133 | /* Free all resources held by a thread. */ | |
134 | extern void release_thread(struct task_struct *); | |
135 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); | |
136 | ||
1da177e4 LT |
137 | /* |
138 | * Return saved PC of a blocked thread. | |
139 | */ | |
140 | extern unsigned long thread_saved_pc(struct task_struct *t); | |
141 | ||
bb11e3bd | 142 | extern void show_code(struct pt_regs *regs); |
1da177e4 LT |
143 | |
144 | unsigned long get_wchan(struct task_struct *p); | |
c7584fb6 | 145 | #define task_pt_regs(tsk) ((struct pt_regs *) \ |
30af7120 | 146 | (task_stack_page(tsk) + THREAD_SIZE) - 1) |
c7584fb6 AV |
147 | #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) |
148 | #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) | |
1da177e4 | 149 | |
a0616cde DH |
150 | static inline unsigned short stap(void) |
151 | { | |
152 | unsigned short cpu_address; | |
153 | ||
154 | asm volatile("stap %0" : "=m" (cpu_address)); | |
155 | return cpu_address; | |
156 | } | |
157 | ||
1da177e4 LT |
158 | /* |
159 | * Give up the time slice of the virtual PU. | |
160 | */ | |
abdba61a HC |
161 | static inline void cpu_relax(void) |
162 | { | |
163 | if (MACHINE_HAS_DIAG44) | |
c48e0913 HC |
164 | asm volatile("diag 0,0,68"); |
165 | barrier(); | |
abdba61a | 166 | } |
1da177e4 | 167 | |
dc74d7f9 HC |
168 | static inline void psw_set_key(unsigned int key) |
169 | { | |
170 | asm volatile("spka 0(%0)" : : "d" (key)); | |
171 | } | |
172 | ||
77fa2245 HC |
173 | /* |
174 | * Set PSW to specified value. | |
175 | */ | |
176 | static inline void __load_psw(psw_t psw) | |
177 | { | |
f4815ac6 | 178 | #ifndef CONFIG_64BIT |
987bcdac | 179 | asm volatile("lpsw %0" : : "Q" (psw) : "cc"); |
77fa2245 | 180 | #else |
987bcdac | 181 | asm volatile("lpswe %0" : : "Q" (psw) : "cc"); |
77fa2245 HC |
182 | #endif |
183 | } | |
184 | ||
1da177e4 LT |
185 | /* |
186 | * Set PSW mask to specified value, while leaving the | |
187 | * PSW addr pointing to the next instruction. | |
188 | */ | |
1da177e4 LT |
189 | static inline void __load_psw_mask (unsigned long mask) |
190 | { | |
191 | unsigned long addr; | |
1da177e4 | 192 | psw_t psw; |
77fa2245 | 193 | |
1da177e4 LT |
194 | psw.mask = mask; |
195 | ||
f4815ac6 | 196 | #ifndef CONFIG_64BIT |
94c12cc7 MS |
197 | asm volatile( |
198 | " basr %0,0\n" | |
199 | "0: ahi %0,1f-0b\n" | |
987bcdac MS |
200 | " st %0,%O1+4(%R1)\n" |
201 | " lpsw %1\n" | |
1da177e4 | 202 | "1:" |
987bcdac | 203 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
f4815ac6 | 204 | #else /* CONFIG_64BIT */ |
94c12cc7 MS |
205 | asm volatile( |
206 | " larl %0,1f\n" | |
987bcdac MS |
207 | " stg %0,%O1+8(%R1)\n" |
208 | " lpswe %1\n" | |
1da177e4 | 209 | "1:" |
987bcdac | 210 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
f4815ac6 | 211 | #endif /* CONFIG_64BIT */ |
1da177e4 | 212 | } |
ccf45caf MS |
213 | |
214 | /* | |
215 | * Rewind PSW instruction address by specified number of bytes. | |
216 | */ | |
217 | static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) | |
218 | { | |
f4815ac6 | 219 | #ifndef CONFIG_64BIT |
ccf45caf MS |
220 | if (psw.addr & PSW_ADDR_AMODE) |
221 | /* 31 bit mode */ | |
222 | return (psw.addr - ilc) | PSW_ADDR_AMODE; | |
223 | /* 24 bit mode */ | |
224 | return (psw.addr - ilc) & ((1UL << 24) - 1); | |
225 | #else | |
226 | unsigned long mask; | |
227 | ||
228 | mask = (psw.mask & PSW_MASK_EA) ? -1UL : | |
229 | (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : | |
230 | (1UL << 24) - 1; | |
231 | return (psw.addr - ilc) & mask; | |
232 | #endif | |
233 | } | |
1da177e4 | 234 | |
1da177e4 LT |
235 | /* |
236 | * Function to drop a processor into disabled wait state | |
237 | */ | |
ff2d8b19 | 238 | static inline void __noreturn disabled_wait(unsigned long code) |
1da177e4 | 239 | { |
1da177e4 | 240 | unsigned long ctl_buf; |
77fa2245 | 241 | psw_t dw_psw; |
1da177e4 | 242 | |
b50511e4 | 243 | dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; |
77fa2245 | 244 | dw_psw.addr = code; |
1da177e4 LT |
245 | /* |
246 | * Store status and then load disabled wait psw, | |
247 | * the processor is dead afterwards | |
248 | */ | |
f4815ac6 | 249 | #ifndef CONFIG_64BIT |
94c12cc7 MS |
250 | asm volatile( |
251 | " stctl 0,0,0(%2)\n" | |
252 | " ni 0(%2),0xef\n" /* switch off protection */ | |
253 | " lctl 0,0,0(%2)\n" | |
254 | " stpt 0xd8\n" /* store timer */ | |
255 | " stckc 0xe0\n" /* store clock comparator */ | |
256 | " stpx 0x108\n" /* store prefix register */ | |
257 | " stam 0,15,0x120\n" /* store access registers */ | |
258 | " std 0,0x160\n" /* store f0 */ | |
259 | " std 2,0x168\n" /* store f2 */ | |
260 | " std 4,0x170\n" /* store f4 */ | |
261 | " std 6,0x178\n" /* store f6 */ | |
262 | " stm 0,15,0x180\n" /* store general registers */ | |
263 | " stctl 0,15,0x1c0\n" /* store control registers */ | |
264 | " oi 0x1c0,0x10\n" /* fake protection bit */ | |
265 | " lpsw 0(%1)" | |
266 | : "=m" (ctl_buf) | |
267 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc"); | |
f4815ac6 | 268 | #else /* CONFIG_64BIT */ |
94c12cc7 MS |
269 | asm volatile( |
270 | " stctg 0,0,0(%2)\n" | |
271 | " ni 4(%2),0xef\n" /* switch off protection */ | |
272 | " lctlg 0,0,0(%2)\n" | |
273 | " lghi 1,0x1000\n" | |
274 | " stpt 0x328(1)\n" /* store timer */ | |
275 | " stckc 0x330(1)\n" /* store clock comparator */ | |
276 | " stpx 0x318(1)\n" /* store prefix register */ | |
277 | " stam 0,15,0x340(1)\n"/* store access registers */ | |
278 | " stfpc 0x31c(1)\n" /* store fpu control */ | |
279 | " std 0,0x200(1)\n" /* store f0 */ | |
280 | " std 1,0x208(1)\n" /* store f1 */ | |
281 | " std 2,0x210(1)\n" /* store f2 */ | |
282 | " std 3,0x218(1)\n" /* store f3 */ | |
283 | " std 4,0x220(1)\n" /* store f4 */ | |
284 | " std 5,0x228(1)\n" /* store f5 */ | |
285 | " std 6,0x230(1)\n" /* store f6 */ | |
286 | " std 7,0x238(1)\n" /* store f7 */ | |
287 | " std 8,0x240(1)\n" /* store f8 */ | |
288 | " std 9,0x248(1)\n" /* store f9 */ | |
289 | " std 10,0x250(1)\n" /* store f10 */ | |
290 | " std 11,0x258(1)\n" /* store f11 */ | |
291 | " std 12,0x260(1)\n" /* store f12 */ | |
292 | " std 13,0x268(1)\n" /* store f13 */ | |
293 | " std 14,0x270(1)\n" /* store f14 */ | |
294 | " std 15,0x278(1)\n" /* store f15 */ | |
295 | " stmg 0,15,0x280(1)\n"/* store general registers */ | |
296 | " stctg 0,15,0x380(1)\n"/* store control registers */ | |
297 | " oi 0x384(1),0x10\n"/* fake protection bit */ | |
298 | " lpswe 0(%1)" | |
299 | : "=m" (ctl_buf) | |
bdd42b28 | 300 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1"); |
f4815ac6 | 301 | #endif /* CONFIG_64BIT */ |
edd53787 | 302 | while (1); |
1da177e4 LT |
303 | } |
304 | ||
a0616cde DH |
305 | /* |
306 | * Use to set psw mask except for the first byte which | |
307 | * won't be changed by this function. | |
308 | */ | |
309 | static inline void | |
310 | __set_psw_mask(unsigned long mask) | |
311 | { | |
312 | __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); | |
313 | } | |
314 | ||
315 | #define local_mcck_enable() \ | |
316 | __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK) | |
317 | #define local_mcck_disable() \ | |
318 | __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT) | |
319 | ||
ab14de6c HC |
320 | /* |
321 | * Basic Machine Check/Program Check Handler. | |
322 | */ | |
323 | ||
324 | extern void s390_base_mcck_handler(void); | |
325 | extern void s390_base_pgm_handler(void); | |
326 | extern void s390_base_ext_handler(void); | |
327 | ||
328 | extern void (*s390_base_mcck_handler_fn)(void); | |
329 | extern void (*s390_base_pgm_handler_fn)(void); | |
330 | extern void (*s390_base_ext_handler_fn)(void); | |
331 | ||
dfd54cbc HC |
332 | #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL |
333 | ||
de1a3f1c MS |
334 | /* |
335 | * Helper macro for exception table entries | |
336 | */ | |
f4815ac6 | 337 | #ifndef CONFIG_64BIT |
de1a3f1c MS |
338 | #define EX_TABLE(_fault,_target) \ |
339 | ".section __ex_table,\"a\"\n" \ | |
340 | " .align 4\n" \ | |
341 | " .long " #_fault "," #_target "\n" \ | |
342 | ".previous\n" | |
343 | #else | |
344 | #define EX_TABLE(_fault,_target) \ | |
345 | ".section __ex_table,\"a\"\n" \ | |
346 | " .align 8\n" \ | |
347 | " .quad " #_fault "," #_target "\n" \ | |
348 | ".previous\n" | |
349 | #endif | |
350 | ||
fbe76568 HC |
351 | extern int memcpy_real(void *, void *, size_t); |
352 | extern void memcpy_absolute(void *, void *, size_t); | |
353 | ||
354 | #define mem_assign_absolute(dest, val) { \ | |
355 | __typeof__(dest) __tmp = (val); \ | |
356 | \ | |
357 | BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ | |
358 | memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ | |
359 | } | |
360 | ||
1da177e4 | 361 | #endif /* __ASM_S390_PROCESSOR_H */ |