Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/smp.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), | |
7 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
8 | * Heiko Carstens (heiko.carstens@de.ibm.com) | |
9 | */ | |
10 | #ifndef __ASM_SMP_H | |
11 | #define __ASM_SMP_H | |
12 | ||
1da177e4 LT |
13 | #include <linux/threads.h> |
14 | #include <linux/cpumask.h> | |
15 | #include <linux/bitops.h> | |
16 | ||
17 | #if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__) | |
18 | ||
19 | #include <asm/lowcore.h> | |
20 | #include <asm/sigp.h> | |
c6b5b847 | 21 | #include <asm/ptrace.h> |
2e5061e4 | 22 | #include <asm/system.h> |
1da177e4 LT |
23 | |
24 | /* | |
25 | s390 specific smp.c headers | |
26 | */ | |
27 | typedef struct | |
28 | { | |
29 | int intresting; | |
30 | sigp_ccode ccode; | |
31 | __u32 status; | |
32 | __u16 cpu; | |
33 | } sigp_info; | |
34 | ||
2b67fc46 HC |
35 | extern void machine_restart_smp(char *); |
36 | extern void machine_halt_smp(void); | |
37 | extern void machine_power_off_smp(void); | |
38 | ||
1da177e4 LT |
39 | #define NO_PROC_ID 0xFF /* No processor magic marker */ |
40 | ||
41 | /* | |
42 | * This magic constant controls our willingness to transfer | |
43 | * a process across CPUs. Such a transfer incurs misses on the L1 | |
44 | * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My | |
45 | * gut feeling is this will vary by board in value. For a board | |
46 | * with separate L2 cache it probably depends also on the RSS, and | |
47 | * for a board with shared L2 cache it ought to decay fast as other | |
48 | * processes are run. | |
49 | */ | |
50 | ||
51 | #define PROC_CHANGE_PENALTY 20 /* Schedule penalty */ | |
52 | ||
39c715b7 | 53 | #define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr) |
1da177e4 | 54 | |
4448aaf0 | 55 | static inline __u16 hard_smp_processor_id(void) |
1da177e4 | 56 | { |
2e5061e4 | 57 | return stap(); |
1da177e4 LT |
58 | } |
59 | ||
60 | /* | |
61 | * returns 1 if cpu is in stopped/check stopped state or not operational | |
62 | * returns 0 otherwise | |
63 | */ | |
64 | static inline int | |
65 | smp_cpu_not_running(int cpu) | |
66 | { | |
67 | __u32 status; | |
68 | ||
69 | switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) { | |
70 | case sigp_order_code_accepted: | |
71 | case sigp_status_stored: | |
72 | /* Check for stopped and check stop state */ | |
73 | if (status & 0x50) | |
74 | return 1; | |
75 | break; | |
76 | case sigp_not_operational: | |
77 | return 1; | |
78 | default: | |
79 | break; | |
80 | } | |
81 | return 0; | |
82 | } | |
83 | ||
84 | #define cpu_logical_map(cpu) (cpu) | |
85 | ||
86 | extern int __cpu_disable (void); | |
87 | extern void __cpu_die (unsigned int cpu); | |
88 | extern void cpu_die (void) __attribute__ ((noreturn)); | |
89 | extern int __cpu_up (unsigned int cpu); | |
90 | ||
dbd70fb4 | 91 | extern struct mutex smp_cpu_state_mutex; |
c10fde0d | 92 | extern int smp_cpu_polarization[]; |
dbd70fb4 | 93 | |
ca9fc75a HC |
94 | extern void arch_send_call_function_single_ipi(int cpu); |
95 | extern void arch_send_call_function_ipi(cpumask_t mask); | |
96 | ||
1da177e4 LT |
97 | #endif |
98 | ||
99 | #ifndef CONFIG_SMP | |
c6b5b847 HC |
100 | static inline void smp_send_stop(void) |
101 | { | |
102 | /* Disable all interrupts/machine checks */ | |
c1821c2e | 103 | __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK); |
c6b5b847 HC |
104 | } |
105 | ||
2f4dfe20 | 106 | #define hard_smp_processor_id() 0 |
a386fba2 | 107 | #define smp_cpu_not_running(cpu) 1 |
1da177e4 LT |
108 | #endif |
109 | ||
1e489518 HC |
110 | #ifdef CONFIG_HOTPLUG_CPU |
111 | extern int smp_rescan_cpus(void); | |
112 | #else | |
113 | static inline int smp_rescan_cpus(void) { return 0; } | |
114 | #endif | |
115 | ||
411ed322 | 116 | extern union save_area *zfcpdump_save_areas[NR_CPUS + 1]; |
1da177e4 | 117 | #endif |