s390/mm: no local TLB flush for clearing-by-ASCE IDTE
[deliverable/linux.git] / arch / s390 / include / asm / tlbflush.h
CommitLineData
1da177e4
LT
1#ifndef _S390_TLBFLUSH_H
2#define _S390_TLBFLUSH_H
3
1da177e4 4#include <linux/mm.h>
53492b1d 5#include <linux/sched.h>
1da177e4 6#include <asm/processor.h>
c1821c2e 7#include <asm/pgalloc.h>
4ccccc52 8#include <asm/pgtable.h>
1da177e4
LT
9
10/*
1b948d6c 11 * Flush all TLB entries on the local CPU.
1da177e4 12 */
ba8a9229 13static inline void __tlb_flush_local(void)
1da177e4 14{
ba8a9229 15 asm volatile("ptlb" : : : "memory");
1da177e4 16}
1da177e4 17
ba8a9229 18/*
1b948d6c 19 * Flush TLB entries for a specific ASCE on all CPUs
ba8a9229 20 */
1b948d6c
MS
21static inline void __tlb_flush_idte(unsigned long asce)
22{
23 /* Global TLB flush for the mm */
24 asm volatile(
25 " .insn rrf,0xb98e0000,0,%0,%1,0"
26 : : "a" (2048), "a" (asce) : "cc");
27}
28
1b948d6c 29#ifdef CONFIG_SMP
a806170e
HC
30void smp_ptlb_all(void);
31
1b948d6c
MS
32/*
33 * Flush all TLB entries on all CPUs.
34 */
ba8a9229 35static inline void __tlb_flush_global(void)
1da177e4 36{
4ccccc52 37 unsigned int dummy = 0;
94c12cc7 38
4ccccc52 39 csp(&dummy, 0, 0);
1da177e4
LT
40}
41
1b948d6c
MS
42/*
43 * Flush TLB entries for a specific mm on all CPUs (in case gmap is used
44 * this implicates multiple ASCEs!).
45 */
374b8f45
MS
46static inline void __tlb_flush_full(struct mm_struct *mm)
47{
374b8f45 48 preempt_disable();
64f31d58 49 atomic_inc(&mm->context.flush_count);
1b948d6c
MS
50 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
51 /* Local TLB flush */
374b8f45 52 __tlb_flush_local();
1b948d6c
MS
53 } else {
54 /* Global TLB flush */
374b8f45 55 __tlb_flush_global();
1b948d6c 56 /* Reset TLB flush mask */
d5dcafee 57 cpumask_copy(mm_cpumask(mm), &mm->context.cpu_attach_mask);
1b948d6c 58 }
64f31d58 59 atomic_dec(&mm->context.flush_count);
374b8f45
MS
60 preempt_enable();
61}
1b948d6c
MS
62
63/*
f0454029
DH
64 * Flush TLB entries for a specific ASCE on all CPUs. Should never be used
65 * when more than one asce (e.g. gmap) ran on this mm.
1b948d6c
MS
66 */
67static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
68{
1b948d6c 69 preempt_disable();
64f31d58 70 atomic_inc(&mm->context.flush_count);
d5dcafee
MS
71 if (MACHINE_HAS_IDTE)
72 __tlb_flush_idte(asce);
73 else
74 __tlb_flush_global();
75 /* Reset TLB flush mask */
76 cpumask_copy(mm_cpumask(mm), &mm->context.cpu_attach_mask);
64f31d58 77 atomic_dec(&mm->context.flush_count);
1b948d6c
MS
78 preempt_enable();
79}
80
81static inline void __tlb_flush_kernel(void)
82{
83 if (MACHINE_HAS_IDTE)
723cacbd 84 __tlb_flush_idte(init_mm.context.asce);
1b948d6c
MS
85 else
86 __tlb_flush_global();
87}
374b8f45 88#else
e1c4d014 89#define __tlb_flush_global() __tlb_flush_local()
1b948d6c 90#define __tlb_flush_full(mm) __tlb_flush_local()
374b8f45 91
1da177e4 92/*
1b948d6c 93 * Flush TLB entries for a specific ASCE on all CPUs.
1da177e4 94 */
1b948d6c 95static inline void __tlb_flush_asce(struct mm_struct *mm, unsigned long asce)
ba8a9229 96{
d5dcafee 97 __tlb_flush_local();
ba8a9229 98}
1da177e4 99
1b948d6c
MS
100static inline void __tlb_flush_kernel(void)
101{
d5dcafee 102 __tlb_flush_local();
1b948d6c
MS
103}
104#endif
105
ba8a9229 106static inline void __tlb_flush_mm(struct mm_struct * mm)
1da177e4 107{
ba8a9229
MS
108 /*
109 * If the machine has IDTE we prefer to do a per mm flush
110 * on all cpus instead of doing a local flush if the mm
111 * only ran on the local cpu.
112 */
e5992f2e 113 if (MACHINE_HAS_IDTE && list_empty(&mm->context.gmap_list))
723cacbd 114 __tlb_flush_asce(mm, mm->context.asce);
043d0708
MS
115 else
116 __tlb_flush_full(mm);
1da177e4
LT
117}
118
5c474a1e 119static inline void __tlb_flush_mm_lazy(struct mm_struct * mm)
1da177e4 120{
050eef36 121 if (mm->context.flush_mm) {
ba8a9229 122 __tlb_flush_mm(mm);
050eef36
MS
123 mm->context.flush_mm = 0;
124 }
1da177e4
LT
125}
126
ba8a9229
MS
127/*
128 * TLB flushing:
129 * flush_tlb() - flushes the current mm struct TLBs
130 * flush_tlb_all() - flushes all processes TLBs
131 * flush_tlb_mm(mm) - flushes the specified mm context TLB's
132 * flush_tlb_page(vma, vmaddr) - flushes one page
133 * flush_tlb_range(vma, start, end) - flushes a range of pages
134 * flush_tlb_kernel_range(start, end) - flushes a range of kernel pages
135 */
1da177e4 136
ba8a9229
MS
137/*
138 * flush_tlb_mm goes together with ptep_set_wrprotect for the
139 * copy_page_range operation and flush_tlb_range is related to
140 * ptep_get_and_clear for change_protection. ptep_set_wrprotect and
141 * ptep_get_and_clear do not flush the TLBs directly if the mm has
142 * only one user. At the end of the update the flush_tlb_mm and
143 * flush_tlb_range functions need to do the flush.
144 */
145#define flush_tlb() do { } while (0)
146#define flush_tlb_all() do { } while (0)
ba8a9229 147#define flush_tlb_page(vma, addr) do { } while (0)
8ffd74a0
MS
148
149static inline void flush_tlb_mm(struct mm_struct *mm)
150{
5c474a1e 151 __tlb_flush_mm_lazy(mm);
8ffd74a0
MS
152}
153
154static inline void flush_tlb_range(struct vm_area_struct *vma,
155 unsigned long start, unsigned long end)
156{
5c474a1e 157 __tlb_flush_mm_lazy(vma->vm_mm);
8ffd74a0
MS
158}
159
160static inline void flush_tlb_kernel_range(unsigned long start,
161 unsigned long end)
162{
1b948d6c 163 __tlb_flush_kernel();
8ffd74a0 164}
1da177e4 165
1da177e4 166#endif /* _S390_TLBFLUSH_H */
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