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bd550337 HB |
1 | /* |
2 | * Support for Vector Instructions | |
3 | * | |
4 | * Assembler macros to generate .byte/.word code for particular | |
5 | * vector instructions that are supported by recent binutils (>= 2.26) only. | |
6 | * | |
7 | * Copyright IBM Corp. 2015 | |
8 | * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_S390_VX_INSN_H | |
12 | #define __ASM_S390_VX_INSN_H | |
13 | ||
14 | #ifdef __ASSEMBLY__ | |
15 | ||
16 | ||
17 | /* Macros to generate vector instruction byte code */ | |
18 | ||
bd550337 HB |
19 | /* GR_NUM - Retrieve general-purpose register number |
20 | * | |
21 | * @opd: Operand to store register number | |
22 | * @r64: String designation register in the format "%rN" | |
23 | */ | |
24 | .macro GR_NUM opd gr | |
0eab11c7 | 25 | \opd = 255 |
bd550337 HB |
26 | .ifc \gr,%r0 |
27 | \opd = 0 | |
28 | .endif | |
29 | .ifc \gr,%r1 | |
30 | \opd = 1 | |
31 | .endif | |
32 | .ifc \gr,%r2 | |
33 | \opd = 2 | |
34 | .endif | |
35 | .ifc \gr,%r3 | |
36 | \opd = 3 | |
37 | .endif | |
38 | .ifc \gr,%r4 | |
39 | \opd = 4 | |
40 | .endif | |
41 | .ifc \gr,%r5 | |
42 | \opd = 5 | |
43 | .endif | |
44 | .ifc \gr,%r6 | |
45 | \opd = 6 | |
46 | .endif | |
47 | .ifc \gr,%r7 | |
48 | \opd = 7 | |
49 | .endif | |
50 | .ifc \gr,%r8 | |
51 | \opd = 8 | |
52 | .endif | |
53 | .ifc \gr,%r9 | |
54 | \opd = 9 | |
55 | .endif | |
56 | .ifc \gr,%r10 | |
57 | \opd = 10 | |
58 | .endif | |
59 | .ifc \gr,%r11 | |
60 | \opd = 11 | |
61 | .endif | |
62 | .ifc \gr,%r12 | |
63 | \opd = 12 | |
64 | .endif | |
65 | .ifc \gr,%r13 | |
66 | \opd = 13 | |
67 | .endif | |
68 | .ifc \gr,%r14 | |
69 | \opd = 14 | |
70 | .endif | |
71 | .ifc \gr,%r15 | |
72 | \opd = 15 | |
73 | .endif | |
0eab11c7 MS |
74 | .if \opd == 255 |
75 | \opd = \gr | |
bd550337 HB |
76 | .endif |
77 | .endm | |
78 | ||
bd550337 HB |
79 | /* VX_NUM - Retrieve vector register number |
80 | * | |
81 | * @opd: Operand to store register number | |
82 | * @vxr: String designation register in the format "%vN" | |
83 | * | |
84 | * The vector register number is used for as input number to the | |
85 | * instruction and, as well as, to compute the RXB field of the | |
0eab11c7 | 86 | * instruction. |
bd550337 HB |
87 | */ |
88 | .macro VX_NUM opd vxr | |
0eab11c7 | 89 | \opd = 255 |
bd550337 HB |
90 | .ifc \vxr,%v0 |
91 | \opd = 0 | |
92 | .endif | |
93 | .ifc \vxr,%v1 | |
94 | \opd = 1 | |
95 | .endif | |
96 | .ifc \vxr,%v2 | |
97 | \opd = 2 | |
98 | .endif | |
99 | .ifc \vxr,%v3 | |
100 | \opd = 3 | |
101 | .endif | |
102 | .ifc \vxr,%v4 | |
103 | \opd = 4 | |
104 | .endif | |
105 | .ifc \vxr,%v5 | |
106 | \opd = 5 | |
107 | .endif | |
108 | .ifc \vxr,%v6 | |
109 | \opd = 6 | |
110 | .endif | |
111 | .ifc \vxr,%v7 | |
112 | \opd = 7 | |
113 | .endif | |
114 | .ifc \vxr,%v8 | |
115 | \opd = 8 | |
116 | .endif | |
117 | .ifc \vxr,%v9 | |
118 | \opd = 9 | |
119 | .endif | |
120 | .ifc \vxr,%v10 | |
121 | \opd = 10 | |
122 | .endif | |
123 | .ifc \vxr,%v11 | |
124 | \opd = 11 | |
125 | .endif | |
126 | .ifc \vxr,%v12 | |
127 | \opd = 12 | |
128 | .endif | |
129 | .ifc \vxr,%v13 | |
130 | \opd = 13 | |
131 | .endif | |
132 | .ifc \vxr,%v14 | |
133 | \opd = 14 | |
134 | .endif | |
135 | .ifc \vxr,%v15 | |
136 | \opd = 15 | |
137 | .endif | |
138 | .ifc \vxr,%v16 | |
139 | \opd = 16 | |
140 | .endif | |
141 | .ifc \vxr,%v17 | |
142 | \opd = 17 | |
143 | .endif | |
144 | .ifc \vxr,%v18 | |
145 | \opd = 18 | |
146 | .endif | |
147 | .ifc \vxr,%v19 | |
148 | \opd = 19 | |
149 | .endif | |
150 | .ifc \vxr,%v20 | |
151 | \opd = 20 | |
152 | .endif | |
153 | .ifc \vxr,%v21 | |
154 | \opd = 21 | |
155 | .endif | |
156 | .ifc \vxr,%v22 | |
157 | \opd = 22 | |
158 | .endif | |
159 | .ifc \vxr,%v23 | |
160 | \opd = 23 | |
161 | .endif | |
162 | .ifc \vxr,%v24 | |
163 | \opd = 24 | |
164 | .endif | |
165 | .ifc \vxr,%v25 | |
166 | \opd = 25 | |
167 | .endif | |
168 | .ifc \vxr,%v26 | |
169 | \opd = 26 | |
170 | .endif | |
171 | .ifc \vxr,%v27 | |
172 | \opd = 27 | |
173 | .endif | |
174 | .ifc \vxr,%v28 | |
175 | \opd = 28 | |
176 | .endif | |
177 | .ifc \vxr,%v29 | |
178 | \opd = 29 | |
179 | .endif | |
180 | .ifc \vxr,%v30 | |
181 | \opd = 30 | |
182 | .endif | |
183 | .ifc \vxr,%v31 | |
184 | \opd = 31 | |
185 | .endif | |
0eab11c7 MS |
186 | .if \opd == 255 |
187 | \opd = \vxr | |
bd550337 HB |
188 | .endif |
189 | .endm | |
190 | ||
191 | /* RXB - Compute most significant bit used vector registers | |
192 | * | |
193 | * @rxb: Operand to store computed RXB value | |
194 | * @v1: First vector register designated operand | |
195 | * @v2: Second vector register designated operand | |
196 | * @v3: Third vector register designated operand | |
197 | * @v4: Fourth vector register designated operand | |
198 | */ | |
199 | .macro RXB rxb v1 v2=0 v3=0 v4=0 | |
200 | \rxb = 0 | |
201 | .if \v1 & 0x10 | |
202 | \rxb = \rxb | 0x08 | |
203 | .endif | |
204 | .if \v2 & 0x10 | |
205 | \rxb = \rxb | 0x04 | |
206 | .endif | |
207 | .if \v3 & 0x10 | |
208 | \rxb = \rxb | 0x02 | |
209 | .endif | |
210 | .if \v4 & 0x10 | |
211 | \rxb = \rxb | 0x01 | |
212 | .endif | |
213 | .endm | |
214 | ||
215 | /* MRXB - Generate Element Size Control and RXB value | |
216 | * | |
217 | * @m: Element size control | |
218 | * @v1: First vector register designated operand (for RXB) | |
219 | * @v2: Second vector register designated operand (for RXB) | |
220 | * @v3: Third vector register designated operand (for RXB) | |
221 | * @v4: Fourth vector register designated operand (for RXB) | |
222 | */ | |
223 | .macro MRXB m v1 v2=0 v3=0 v4=0 | |
224 | rxb = 0 | |
225 | RXB rxb, \v1, \v2, \v3, \v4 | |
226 | .byte (\m << 4) | rxb | |
227 | .endm | |
228 | ||
229 | /* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields | |
230 | * | |
231 | * @m: Element size control | |
232 | * @opc: Opcode | |
233 | * @v1: First vector register designated operand (for RXB) | |
234 | * @v2: Second vector register designated operand (for RXB) | |
235 | * @v3: Third vector register designated operand (for RXB) | |
236 | * @v4: Fourth vector register designated operand (for RXB) | |
237 | */ | |
238 | .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0 | |
239 | MRXB \m, \v1, \v2, \v3, \v4 | |
240 | .byte \opc | |
241 | .endm | |
242 | ||
243 | /* Vector support instructions */ | |
244 | ||
245 | /* VECTOR GENERATE BYTE MASK */ | |
246 | .macro VGBM vr imm2 | |
247 | VX_NUM v1, \vr | |
0eab11c7 | 248 | .word (0xE700 | ((v1&15) << 4)) |
bd550337 HB |
249 | .word \imm2 |
250 | MRXBOPC 0, 0x44, v1 | |
251 | .endm | |
252 | .macro VZERO vxr | |
253 | VGBM \vxr, 0 | |
254 | .endm | |
255 | .macro VONE vxr | |
256 | VGBM \vxr, 0xFFFF | |
257 | .endm | |
258 | ||
259 | /* VECTOR LOAD VR ELEMENT FROM GR */ | |
260 | .macro VLVG v, gr, disp, m | |
261 | VX_NUM v1, \v | |
262 | GR_NUM b2, "%r0" | |
263 | GR_NUM r3, \gr | |
0eab11c7 | 264 | .word 0xE700 | ((v1&15) << 4) | r3 |
bd550337 HB |
265 | .word (b2 << 12) | (\disp) |
266 | MRXBOPC \m, 0x22, v1 | |
267 | .endm | |
268 | .macro VLVGB v, gr, index, base | |
269 | VLVG \v, \gr, \index, \base, 0 | |
270 | .endm | |
271 | .macro VLVGH v, gr, index | |
272 | VLVG \v, \gr, \index, 1 | |
273 | .endm | |
274 | .macro VLVGF v, gr, index | |
275 | VLVG \v, \gr, \index, 2 | |
276 | .endm | |
277 | .macro VLVGG v, gr, index | |
278 | VLVG \v, \gr, \index, 3 | |
279 | .endm | |
280 | ||
474fd6e8 MS |
281 | /* VECTOR LOAD REGISTER */ |
282 | .macro VLR v1, v2 | |
283 | VX_NUM v1, \v1 | |
284 | VX_NUM v2, \v2 | |
285 | .word 0xE700 | ((v1&15) << 4) | (v2&15) | |
286 | .word 0 | |
287 | MRXBOPC 0, 0x56, v1, v2 | |
288 | .endm | |
289 | ||
bd550337 HB |
290 | /* VECTOR LOAD */ |
291 | .macro VL v, disp, index="%r0", base | |
292 | VX_NUM v1, \v | |
293 | GR_NUM x2, \index | |
294 | GR_NUM b2, \base | |
0eab11c7 | 295 | .word 0xE700 | ((v1&15) << 4) | x2 |
bd550337 HB |
296 | .word (b2 << 12) | (\disp) |
297 | MRXBOPC 0, 0x06, v1 | |
298 | .endm | |
299 | ||
300 | /* VECTOR LOAD ELEMENT */ | |
301 | .macro VLEx vr1, disp, index="%r0", base, m3, opc | |
302 | VX_NUM v1, \vr1 | |
303 | GR_NUM x2, \index | |
304 | GR_NUM b2, \base | |
0eab11c7 | 305 | .word 0xE700 | ((v1&15) << 4) | x2 |
bd550337 HB |
306 | .word (b2 << 12) | (\disp) |
307 | MRXBOPC \m3, \opc, v1 | |
308 | .endm | |
309 | .macro VLEB vr1, disp, index="%r0", base, m3 | |
310 | VLEx \vr1, \disp, \index, \base, \m3, 0x00 | |
311 | .endm | |
312 | .macro VLEH vr1, disp, index="%r0", base, m3 | |
313 | VLEx \vr1, \disp, \index, \base, \m3, 0x01 | |
314 | .endm | |
315 | .macro VLEF vr1, disp, index="%r0", base, m3 | |
316 | VLEx \vr1, \disp, \index, \base, \m3, 0x03 | |
317 | .endm | |
318 | .macro VLEG vr1, disp, index="%r0", base, m3 | |
319 | VLEx \vr1, \disp, \index, \base, \m3, 0x02 | |
320 | .endm | |
321 | ||
322 | /* VECTOR LOAD ELEMENT IMMEDIATE */ | |
323 | .macro VLEIx vr1, imm2, m3, opc | |
324 | VX_NUM v1, \vr1 | |
0eab11c7 | 325 | .word 0xE700 | ((v1&15) << 4) |
bd550337 HB |
326 | .word \imm2 |
327 | MRXBOPC \m3, \opc, v1 | |
328 | .endm | |
329 | .macro VLEIB vr1, imm2, index | |
330 | VLEIx \vr1, \imm2, \index, 0x40 | |
331 | .endm | |
332 | .macro VLEIH vr1, imm2, index | |
333 | VLEIx \vr1, \imm2, \index, 0x41 | |
334 | .endm | |
335 | .macro VLEIF vr1, imm2, index | |
336 | VLEIx \vr1, \imm2, \index, 0x43 | |
337 | .endm | |
338 | .macro VLEIG vr1, imm2, index | |
339 | VLEIx \vr1, \imm2, \index, 0x42 | |
340 | .endm | |
341 | ||
342 | /* VECTOR LOAD GR FROM VR ELEMENT */ | |
343 | .macro VLGV gr, vr, disp, base="%r0", m | |
344 | GR_NUM r1, \gr | |
345 | GR_NUM b2, \base | |
346 | VX_NUM v3, \vr | |
0eab11c7 | 347 | .word 0xE700 | (r1 << 4) | (v3&15) |
bd550337 HB |
348 | .word (b2 << 12) | (\disp) |
349 | MRXBOPC \m, 0x21, v3 | |
350 | .endm | |
351 | .macro VLGVB gr, vr, disp, base="%r0" | |
352 | VLGV \gr, \vr, \disp, \base, 0 | |
353 | .endm | |
354 | .macro VLGVH gr, vr, disp, base="%r0" | |
355 | VLGV \gr, \vr, \disp, \base, 1 | |
356 | .endm | |
357 | .macro VLGVF gr, vr, disp, base="%r0" | |
358 | VLGV \gr, \vr, \disp, \base, 2 | |
359 | .endm | |
360 | .macro VLGVG gr, vr, disp, base="%r0" | |
361 | VLGV \gr, \vr, \disp, \base, 3 | |
362 | .endm | |
363 | ||
364 | /* VECTOR LOAD MULTIPLE */ | |
365 | .macro VLM vfrom, vto, disp, base | |
366 | VX_NUM v1, \vfrom | |
367 | VX_NUM v3, \vto | |
368 | GR_NUM b2, \base /* Base register */ | |
0eab11c7 | 369 | .word 0xE700 | ((v1&15) << 4) | (v3&15) |
bd550337 HB |
370 | .word (b2 << 12) | (\disp) |
371 | MRXBOPC 0, 0x36, v1, v3 | |
372 | .endm | |
373 | ||
374 | /* VECTOR STORE MULTIPLE */ | |
375 | .macro VSTM vfrom, vto, disp, base | |
376 | VX_NUM v1, \vfrom | |
377 | VX_NUM v3, \vto | |
378 | GR_NUM b2, \base /* Base register */ | |
0eab11c7 | 379 | .word 0xE700 | ((v1&15) << 4) | (v3&15) |
bd550337 HB |
380 | .word (b2 << 12) | (\disp) |
381 | MRXBOPC 0, 0x3E, v1, v3 | |
382 | .endm | |
383 | ||
384 | /* VECTOR PERMUTE */ | |
385 | .macro VPERM vr1, vr2, vr3, vr4 | |
386 | VX_NUM v1, \vr1 | |
387 | VX_NUM v2, \vr2 | |
388 | VX_NUM v3, \vr3 | |
389 | VX_NUM v4, \vr4 | |
0eab11c7 MS |
390 | .word 0xE700 | ((v1&15) << 4) | (v2&15) |
391 | .word ((v3&15) << 12) | |
392 | MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4 | |
bd550337 HB |
393 | .endm |
394 | ||
395 | /* VECTOR UNPACK LOGICAL LOW */ | |
396 | .macro VUPLL vr1, vr2, m3 | |
397 | VX_NUM v1, \vr1 | |
398 | VX_NUM v2, \vr2 | |
0eab11c7 | 399 | .word 0xE700 | ((v1&15) << 4) | (v2&15) |
bd550337 HB |
400 | .word 0x0000 |
401 | MRXBOPC \m3, 0xD4, v1, v2 | |
402 | .endm | |
403 | .macro VUPLLB vr1, vr2 | |
404 | VUPLL \vr1, \vr2, 0 | |
405 | .endm | |
406 | .macro VUPLLH vr1, vr2 | |
407 | VUPLL \vr1, \vr2, 1 | |
408 | .endm | |
409 | .macro VUPLLF vr1, vr2 | |
410 | VUPLL \vr1, \vr2, 2 | |
411 | .endm | |
412 | ||
413 | ||
414 | /* Vector integer instructions */ | |
415 | ||
474fd6e8 MS |
416 | /* VECTOR AND */ |
417 | .macro VN vr1, vr2, vr3 | |
418 | VX_NUM v1, \vr1 | |
419 | VX_NUM v2, \vr2 | |
420 | VX_NUM v3, \vr3 | |
421 | .word 0xE700 | ((v1&15) << 4) | (v2&15) | |
422 | .word ((v3&15) << 12) | |
423 | MRXBOPC 0, 0x68, v1, v2, v3 | |
424 | .endm | |
425 | ||
bd550337 HB |
426 | /* VECTOR EXCLUSIVE OR */ |
427 | .macro VX vr1, vr2, vr3 | |
428 | VX_NUM v1, \vr1 | |
429 | VX_NUM v2, \vr2 | |
430 | VX_NUM v3, \vr3 | |
0eab11c7 MS |
431 | .word 0xE700 | ((v1&15) << 4) | (v2&15) |
432 | .word ((v3&15) << 12) | |
bd550337 HB |
433 | MRXBOPC 0, 0x6D, v1, v2, v3 |
434 | .endm | |
435 | ||
436 | /* VECTOR GALOIS FIELD MULTIPLY SUM */ | |
437 | .macro VGFM vr1, vr2, vr3, m4 | |
438 | VX_NUM v1, \vr1 | |
439 | VX_NUM v2, \vr2 | |
440 | VX_NUM v3, \vr3 | |
0eab11c7 MS |
441 | .word 0xE700 | ((v1&15) << 4) | (v2&15) |
442 | .word ((v3&15) << 12) | |
bd550337 HB |
443 | MRXBOPC \m4, 0xB4, v1, v2, v3 |
444 | .endm | |
445 | .macro VGFMB vr1, vr2, vr3 | |
446 | VGFM \vr1, \vr2, \vr3, 0 | |
447 | .endm | |
448 | .macro VGFMH vr1, vr2, vr3 | |
449 | VGFM \vr1, \vr2, \vr3, 1 | |
450 | .endm | |
451 | .macro VGFMF vr1, vr2, vr3 | |
452 | VGFM \vr1, \vr2, \vr3, 2 | |
453 | .endm | |
454 | .macro VGFMG vr1, vr2, vr3 | |
455 | VGFM \vr1, \vr2, \vr3, 3 | |
456 | .endm | |
457 | ||
458 | /* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */ | |
459 | .macro VGFMA vr1, vr2, vr3, vr4, m5 | |
460 | VX_NUM v1, \vr1 | |
461 | VX_NUM v2, \vr2 | |
462 | VX_NUM v3, \vr3 | |
463 | VX_NUM v4, \vr4 | |
0eab11c7 MS |
464 | .word 0xE700 | ((v1&15) << 4) | (v2&15) |
465 | .word ((v3&15) << 12) | (\m5 << 8) | |
466 | MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4 | |
bd550337 HB |
467 | .endm |
468 | .macro VGFMAB vr1, vr2, vr3, vr4 | |
469 | VGFMA \vr1, \vr2, \vr3, \vr4, 0 | |
470 | .endm | |
471 | .macro VGFMAH vr1, vr2, vr3, vr4 | |
472 | VGFMA \vr1, \vr2, \vr3, \vr4, 1 | |
473 | .endm | |
474 | .macro VGFMAF vr1, vr2, vr3, vr4 | |
475 | VGFMA \vr1, \vr2, \vr3, \vr4, 2 | |
476 | .endm | |
477 | .macro VGFMAG vr1, vr2, vr3, vr4 | |
478 | VGFMA \vr1, \vr2, \vr3, \vr4, 3 | |
479 | .endm | |
480 | ||
481 | /* VECTOR SHIFT RIGHT LOGICAL BY BYTE */ | |
482 | .macro VSRLB vr1, vr2, vr3 | |
483 | VX_NUM v1, \vr1 | |
484 | VX_NUM v2, \vr2 | |
485 | VX_NUM v3, \vr3 | |
0eab11c7 MS |
486 | .word 0xE700 | ((v1&15) << 4) | (v2&15) |
487 | .word ((v3&15) << 12) | |
bd550337 HB |
488 | MRXBOPC 0, 0x7D, v1, v2, v3 |
489 | .endm | |
490 | ||
474fd6e8 MS |
491 | /* VECTOR REPLICATE IMMEDIATE */ |
492 | .macro VREPI vr1, imm2, m3 | |
493 | VX_NUM v1, \vr1 | |
494 | .word 0xE700 | ((v1&15) << 4) | |
495 | .word \imm2 | |
496 | MRXBOPC \m3, 0x45, v1 | |
497 | .endm | |
498 | .macro VREPIB vr1, imm2 | |
499 | VREPI \vr1, \imm2, 0 | |
500 | .endm | |
501 | .macro VREPIH vr1, imm2 | |
502 | VREPI \vr1, \imm2, 1 | |
503 | .endm | |
504 | .macro VREPIF vr1, imm2 | |
505 | VREPI \vr1, \imm2, 2 | |
506 | .endm | |
507 | .macro VREPIG vr1, imm2 | |
508 | VREP \vr1, \imm2, 3 | |
509 | .endm | |
510 | ||
511 | /* VECTOR ADD */ | |
512 | .macro VA vr1, vr2, vr3, m4 | |
513 | VX_NUM v1, \vr1 | |
514 | VX_NUM v2, \vr2 | |
515 | VX_NUM v3, \vr3 | |
516 | .word 0xE700 | ((v1&15) << 4) | (v2&15) | |
517 | .word ((v3&15) << 12) | |
518 | MRXBOPC \m4, 0xF3, v1, v2, v3 | |
519 | .endm | |
520 | .macro VAB vr1, vr2, vr3 | |
521 | VA \vr1, \vr2, \vr3, 0 | |
522 | .endm | |
523 | .macro VAH vr1, vr2, vr3 | |
524 | VA \vr1, \vr2, \vr3, 1 | |
525 | .endm | |
526 | .macro VAF vr1, vr2, vr3 | |
527 | VA \vr1, \vr2, \vr3, 2 | |
528 | .endm | |
529 | .macro VAG vr1, vr2, vr3 | |
530 | VA \vr1, \vr2, \vr3, 3 | |
531 | .endm | |
532 | .macro VAQ vr1, vr2, vr3 | |
533 | VA \vr1, \vr2, \vr3, 4 | |
534 | .endm | |
535 | ||
536 | /* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */ | |
537 | .macro VESRAV vr1, vr2, vr3, m4 | |
538 | VX_NUM v1, \vr1 | |
539 | VX_NUM v2, \vr2 | |
540 | VX_NUM v3, \vr3 | |
541 | .word 0xE700 | ((v1&15) << 4) | (v2&15) | |
542 | .word ((v3&15) << 12) | |
543 | MRXBOPC \m4, 0x7A, v1, v2, v3 | |
544 | .endm | |
545 | ||
546 | .macro VESRAVB vr1, vr2, vr3 | |
547 | VESRAV \vr1, \vr2, \vr3, 0 | |
548 | .endm | |
549 | .macro VESRAVH vr1, vr2, vr3 | |
550 | VESRAV \vr1, \vr2, \vr3, 1 | |
551 | .endm | |
552 | .macro VESRAVF vr1, vr2, vr3 | |
553 | VESRAV \vr1, \vr2, \vr3, 2 | |
554 | .endm | |
555 | .macro VESRAVG vr1, vr2, vr3 | |
556 | VESRAV \vr1, \vr2, \vr3, 3 | |
557 | .endm | |
bd550337 HB |
558 | |
559 | #endif /* __ASSEMBLY__ */ | |
560 | #endif /* __ASM_S390_VX_INSN_H */ |