Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * S390 low-level entry points. |
3 | * | |
a53c8fab | 4 | * Copyright IBM Corp. 1999, 2012 |
1da177e4 | 5 | * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), |
25d83cbf HC |
6 | * Hartmut Penner (hp@de.ibm.com), |
7 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), | |
77fa2245 | 8 | * Heiko Carstens <heiko.carstens@de.ibm.com> |
1da177e4 LT |
9 | */ |
10 | ||
2bc89b5e | 11 | #include <linux/init.h> |
144d634a | 12 | #include <linux/linkage.h> |
eb608fb3 | 13 | #include <asm/processor.h> |
1da177e4 | 14 | #include <asm/cache.h> |
1da177e4 LT |
15 | #include <asm/errno.h> |
16 | #include <asm/ptrace.h> | |
17 | #include <asm/thread_info.h> | |
0013a854 | 18 | #include <asm/asm-offsets.h> |
1da177e4 LT |
19 | #include <asm/unistd.h> |
20 | #include <asm/page.h> | |
eb546195 | 21 | #include <asm/sigp.h> |
1f44a225 | 22 | #include <asm/irq.h> |
9977e886 HB |
23 | #include <asm/fpu-internal.h> |
24 | #include <asm/vx-insn.h> | |
1da177e4 | 25 | |
c5328901 MS |
26 | __PT_R0 = __PT_GPRS |
27 | __PT_R1 = __PT_GPRS + 8 | |
28 | __PT_R2 = __PT_GPRS + 16 | |
29 | __PT_R3 = __PT_GPRS + 24 | |
30 | __PT_R4 = __PT_GPRS + 32 | |
31 | __PT_R5 = __PT_GPRS + 40 | |
32 | __PT_R6 = __PT_GPRS + 48 | |
33 | __PT_R7 = __PT_GPRS + 56 | |
34 | __PT_R8 = __PT_GPRS + 64 | |
35 | __PT_R9 = __PT_GPRS + 72 | |
36 | __PT_R10 = __PT_GPRS + 80 | |
37 | __PT_R11 = __PT_GPRS + 88 | |
38 | __PT_R12 = __PT_GPRS + 96 | |
39 | __PT_R13 = __PT_GPRS + 104 | |
40 | __PT_R14 = __PT_GPRS + 112 | |
41 | __PT_R15 = __PT_GPRS + 120 | |
1da177e4 LT |
42 | |
43 | STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER | |
44 | STACK_SIZE = 1 << STACK_SHIFT | |
dc7ee00d | 45 | STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE |
1da177e4 | 46 | |
2a0a5b22 JW |
47 | _TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \ |
48 | _TIF_UPROBE) | |
d3a73acb MS |
49 | _TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \ |
50 | _TIF_SYSCALL_TRACEPOINT) | |
9977e886 | 51 | _CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE | _CIF_FPU) |
d3a73acb | 52 | _PIF_WORK = (_PIF_PER_TRAP) |
1da177e4 | 53 | |
9977e886 | 54 | #define BASED(name) name-cleanup_critical(%r13) |
1da177e4 | 55 | |
1f194a4c | 56 | .macro TRACE_IRQS_ON |
c5328901 | 57 | #ifdef CONFIG_TRACE_IRQFLAGS |
6a2df3a8 MS |
58 | basr %r2,%r0 |
59 | brasl %r14,trace_hardirqs_on_caller | |
c5328901 | 60 | #endif |
1f194a4c HC |
61 | .endm |
62 | ||
63 | .macro TRACE_IRQS_OFF | |
c5328901 | 64 | #ifdef CONFIG_TRACE_IRQFLAGS |
6a2df3a8 MS |
65 | basr %r2,%r0 |
66 | brasl %r14,trace_hardirqs_off_caller | |
411788ea | 67 | #endif |
c5328901 | 68 | .endm |
411788ea | 69 | |
411788ea | 70 | .macro LOCKDEP_SYS_EXIT |
c5328901 MS |
71 | #ifdef CONFIG_LOCKDEP |
72 | tm __PT_PSW+1(%r11),0x01 # returning to user ? | |
73 | jz .+10 | |
411788ea | 74 | brasl %r14,lockdep_sys_exit |
1f194a4c | 75 | #endif |
1da177e4 | 76 | .endm |
1da177e4 | 77 | |
c5328901 | 78 | .macro CHECK_STACK stacksize,savearea |
63b12246 | 79 | #ifdef CONFIG_CHECK_STACK |
c5328901 MS |
80 | tml %r15,\stacksize - CONFIG_STACK_GUARD |
81 | lghi %r14,\savearea | |
82 | jz stack_overflow | |
63b12246 | 83 | #endif |
63b12246 MS |
84 | .endm |
85 | ||
2acb94f4 | 86 | .macro SWITCH_ASYNC savearea,timer |
c5328901 MS |
87 | tmhh %r8,0x0001 # interrupting from user ? |
88 | jnz 1f | |
89 | lgr %r14,%r9 | |
90 | slg %r14,BASED(.Lcritical_start) | |
91 | clg %r14,BASED(.Lcritical_length) | |
1da177e4 | 92 | jhe 0f |
c5328901 | 93 | lghi %r11,\savearea # inside critical section, do cleanup |
1da177e4 | 94 | brasl %r14,cleanup_critical |
c5328901 | 95 | tmhh %r8,0x0001 # retest problem state after cleanup |
1da177e4 | 96 | jnz 1f |
2acb94f4 | 97 | 0: lg %r14,__LC_ASYNC_STACK # are we already on the async stack? |
1da177e4 | 98 | slgr %r14,%r15 |
2acb94f4 | 99 | srag %r14,%r14,STACK_SHIFT |
a359bb11 | 100 | jnz 2f |
2acb94f4 | 101 | CHECK_STACK 1<<STACK_SHIFT,\savearea |
dc7ee00d | 102 | aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) |
a359bb11 MS |
103 | j 3f |
104 | 1: LAST_BREAK %r14 | |
105 | UPDATE_VTIME %r14,%r15,\timer | |
2acb94f4 | 106 | 2: lg %r15,__LC_ASYNC_STACK # load async stack |
a359bb11 | 107 | 3: la %r11,STACK_FRAME_OVERHEAD(%r15) |
25d83cbf | 108 | .endm |
1da177e4 | 109 | |
a359bb11 MS |
110 | .macro UPDATE_VTIME w1,w2,enter_timer |
111 | lg \w1,__LC_EXIT_TIMER | |
112 | lg \w2,__LC_LAST_UPDATE_TIMER | |
113 | slg \w1,\enter_timer | |
114 | slg \w2,__LC_EXIT_TIMER | |
115 | alg \w1,__LC_USER_TIMER | |
116 | alg \w2,__LC_SYSTEM_TIMER | |
117 | stg \w1,__LC_USER_TIMER | |
118 | stg \w2,__LC_SYSTEM_TIMER | |
c5328901 | 119 | mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer |
1da177e4 LT |
120 | .endm |
121 | ||
c5328901 MS |
122 | .macro LAST_BREAK scratch |
123 | srag \scratch,%r10,23 | |
124 | jz .+10 | |
125 | stg %r10,__TI_last_break(%r12) | |
86f2552b MS |
126 | .endm |
127 | ||
1e54622e | 128 | .macro REENABLE_IRQS |
c5328901 MS |
129 | stg %r8,__LC_RETURN_PSW |
130 | ni __LC_RETURN_PSW,0xbf | |
131 | ssm __LC_RETURN_PSW | |
1e54622e MS |
132 | .endm |
133 | ||
473e66ba | 134 | .macro STCK savearea |
d652d596 | 135 | #ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES |
473e66ba HC |
136 | .insn s,0xb27c0000,\savearea # store clock fast |
137 | #else | |
138 | .insn s,0xb2050000,\savearea # store clock | |
139 | #endif | |
140 | .endm | |
141 | ||
860dba45 MS |
142 | .section .kprobes.text, "ax" |
143 | ||
1da177e4 LT |
144 | /* |
145 | * Scheduler resume function, called by switch_to | |
146 | * gpr2 = (task_struct *) prev | |
147 | * gpr3 = (task_struct *) next | |
148 | * Returns: | |
149 | * gpr2 = prev | |
150 | */ | |
144d634a | 151 | ENTRY(__switch_to) |
eda0c6d6 | 152 | stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task |
3827ec3d MS |
153 | lgr %r1,%r2 |
154 | aghi %r1,__TASK_thread # thread_struct of prev task | |
155 | lg %r4,__TASK_thread_info(%r2) # get thread_info of prev | |
156 | lg %r5,__TASK_thread_info(%r3) # get thread_info of next | |
157 | stg %r15,__THREAD_ksp(%r1) # store kernel stack of prev | |
158 | lgr %r1,%r3 | |
159 | aghi %r1,__TASK_thread # thread_struct of next task | |
eda0c6d6 | 160 | lgr %r15,%r5 |
dc7ee00d | 161 | aghi %r15,STACK_INIT # end of kernel stack of next |
eda0c6d6 MS |
162 | stg %r3,__LC_CURRENT # store task struct of next |
163 | stg %r5,__LC_THREAD_INFO # store thread info of next | |
164 | stg %r15,__LC_KERNEL_STACK # store end of kernel stack | |
3827ec3d | 165 | lg %r15,__THREAD_ksp(%r1) # load kernel stack of next |
eda0c6d6 MS |
166 | lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 |
167 | mvc __LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next | |
d3a73acb | 168 | lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task |
1da177e4 LT |
169 | br %r14 |
170 | ||
86ed42f4 | 171 | .L__critical_start: |
d0fc4107 MS |
172 | |
173 | #if IS_ENABLED(CONFIG_KVM) | |
174 | /* | |
175 | * sie64a calling convention: | |
176 | * %r2 pointer to sie control block | |
177 | * %r3 guest register save area | |
178 | */ | |
179 | ENTRY(sie64a) | |
180 | stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers | |
181 | stg %r2,__SF_EMPTY(%r15) # save control block pointer | |
182 | stg %r3,__SF_EMPTY+8(%r15) # save guest register save area | |
183 | xc __SF_EMPTY+16(16,%r15),__SF_EMPTY+16(%r15) # host id & reason | |
184 | tm __LC_CPU_FLAGS+7,_CIF_FPU # load guest fp/vx registers ? | |
185 | jno .Lsie_load_guest_gprs | |
d0fc4107 MS |
186 | brasl %r14,load_fpu_regs # load guest fp/vx regs |
187 | .Lsie_load_guest_gprs: | |
188 | lmg %r0,%r13,0(%r3) # load guest gprs 0-13 | |
189 | lg %r14,__LC_GMAP # get gmap pointer | |
190 | ltgr %r14,%r14 | |
191 | jz .Lsie_gmap | |
192 | lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce | |
193 | .Lsie_gmap: | |
194 | lg %r14,__SF_EMPTY(%r15) # get control block pointer | |
195 | oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now | |
196 | tm __SIE_PROG20+3(%r14),3 # last exit... | |
197 | jnz .Lsie_skip | |
198 | tm __LC_CPU_FLAGS+7,_CIF_FPU | |
199 | jo .Lsie_skip # exit if fp/vx regs changed | |
200 | tm __LC_MACHINE_FLAGS+6,0x20 # MACHINE_FLAG_LPP | |
201 | jz .Lsie_enter | |
888d5e98 | 202 | .insn s,0xb2800000,__LC_CURRENT_PID # set guest id to pid |
d0fc4107 MS |
203 | .Lsie_enter: |
204 | sie 0(%r14) | |
205 | tm __LC_MACHINE_FLAGS+6,0x20 # MACHINE_FLAG_LPP | |
206 | jz .Lsie_skip | |
207 | .insn s,0xb2800000,__SF_EMPTY+16(%r15)# set host id | |
208 | .Lsie_skip: | |
209 | ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE | |
210 | lctlg %c1,%c1,__LC_USER_ASCE # load primary asce | |
211 | .Lsie_done: | |
212 | # some program checks are suppressing. C code (e.g. do_protection_exception) | |
213 | # will rewind the PSW by the ILC, which is 4 bytes in case of SIE. Other | |
214 | # instructions between sie64a and .Lsie_done should not cause program | |
215 | # interrupts. So lets use a nop (47 00 00 00) as a landing pad. | |
216 | # See also .Lcleanup_sie | |
217 | .Lrewind_pad: | |
218 | nop 0 | |
219 | .globl sie_exit | |
220 | sie_exit: | |
221 | lg %r14,__SF_EMPTY+8(%r15) # load guest register save area | |
222 | stmg %r0,%r13,0(%r14) # save guest gprs 0-13 | |
223 | lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers | |
224 | lg %r2,__SF_EMPTY+24(%r15) # return exit reason code | |
225 | br %r14 | |
226 | .Lsie_fault: | |
227 | lghi %r14,-EFAULT | |
228 | stg %r14,__SF_EMPTY+24(%r15) # set exit reason code | |
229 | j sie_exit | |
230 | ||
231 | EX_TABLE(.Lrewind_pad,.Lsie_fault) | |
232 | EX_TABLE(sie_exit,.Lsie_fault) | |
233 | #endif | |
234 | ||
1da177e4 LT |
235 | /* |
236 | * SVC interrupt handler routine. System calls are synchronous events and | |
237 | * are executed with interrupts enabled. | |
238 | */ | |
239 | ||
144d634a | 240 | ENTRY(system_call) |
c185b783 | 241 | stpt __LC_SYNC_ENTER_TIMER |
86ed42f4 | 242 | .Lsysc_stmg: |
c5328901 MS |
243 | stmg %r8,%r15,__LC_SAVE_AREA_SYNC |
244 | lg %r10,__LC_LAST_BREAK | |
245 | lg %r12,__LC_THREAD_INFO | |
d3a73acb | 246 | lghi %r14,_PIF_SYSCALL |
86ed42f4 | 247 | .Lsysc_per: |
c5328901 | 248 | lg %r15,__LC_KERNEL_STACK |
c5328901 | 249 | la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs |
c5328901 | 250 | LAST_BREAK %r13 |
a359bb11 MS |
251 | .Lsysc_vtime: |
252 | UPDATE_VTIME %r10,%r13,__LC_SYNC_ENTER_TIMER | |
c5328901 MS |
253 | stmg %r0,%r7,__PT_R0(%r11) |
254 | mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC | |
255 | mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW | |
aa33c8cb | 256 | mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC |
d3a73acb | 257 | stg %r14,__PT_FLAGS(%r11) |
86ed42f4 | 258 | .Lsysc_do_svc: |
61649881 | 259 | lg %r10,__TI_sysc_table(%r12) # address of system call table |
aa33c8cb | 260 | llgh %r8,__PT_INT_CODE+2(%r11) |
c5328901 | 261 | slag %r8,%r8,2 # shift and test for svc 0 |
86ed42f4 | 262 | jnz .Lsysc_nr_ok |
1da177e4 | 263 | # svc 0: system call number in %r1 |
c5328901 | 264 | llgfr %r1,%r1 # clear high word in r1 |
86f2552b | 265 | cghi %r1,NR_syscalls |
86ed42f4 | 266 | jnl .Lsysc_nr_ok |
aa33c8cb | 267 | sth %r1,__PT_INT_CODE+2(%r11) |
c5328901 | 268 | slag %r8,%r1,2 |
86ed42f4 | 269 | .Lsysc_nr_ok: |
c5328901 MS |
270 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) |
271 | stg %r2,__PT_ORIG_GPR2(%r11) | |
272 | stg %r7,STACK_FRAME_OVERHEAD(%r15) | |
273 | lgf %r9,0(%r8,%r10) # get system call add. | |
d3a73acb | 274 | tm __TI_flags+7(%r12),_TIF_TRACE |
86ed42f4 | 275 | jnz .Lsysc_tracesys |
c5328901 MS |
276 | basr %r14,%r9 # call sys_xxxx |
277 | stg %r2,__PT_R2(%r11) # store return value | |
1da177e4 | 278 | |
86ed42f4 | 279 | .Lsysc_return: |
6a2df3a8 | 280 | LOCKDEP_SYS_EXIT |
86ed42f4 | 281 | .Lsysc_tif: |
d3a73acb | 282 | tm __PT_FLAGS+7(%r11),_PIF_WORK |
86ed42f4 | 283 | jnz .Lsysc_work |
d3a73acb | 284 | tm __TI_flags+7(%r12),_TIF_WORK |
86ed42f4 | 285 | jnz .Lsysc_work # check for work |
d3a73acb | 286 | tm __LC_CPU_FLAGS+7,_CIF_WORK |
86ed42f4 MS |
287 | jnz .Lsysc_work |
288 | .Lsysc_restore: | |
c5328901 MS |
289 | lg %r14,__LC_VDSO_PER_CPU |
290 | lmg %r0,%r10,__PT_R0(%r11) | |
291 | mvc __LC_RETURN_PSW(16),__PT_PSW(%r11) | |
292 | stpt __LC_EXIT_TIMER | |
293 | mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER | |
294 | lmg %r11,%r15,__PT_R11(%r11) | |
295 | lpswe __LC_RETURN_PSW | |
86ed42f4 | 296 | .Lsysc_done: |
411788ea | 297 | |
43d399d2 MS |
298 | # |
299 | # One of the work bits is on. Find out which one. | |
300 | # | |
86ed42f4 | 301 | .Lsysc_work: |
d3a73acb | 302 | tm __LC_CPU_FLAGS+7,_CIF_MCCK_PENDING |
86ed42f4 | 303 | jo .Lsysc_mcck_pending |
86f2552b | 304 | tm __TI_flags+7(%r12),_TIF_NEED_RESCHED |
86ed42f4 | 305 | jo .Lsysc_reschedule |
2a0a5b22 JW |
306 | #ifdef CONFIG_UPROBES |
307 | tm __TI_flags+7(%r12),_TIF_UPROBE | |
86ed42f4 | 308 | jo .Lsysc_uprobe_notify |
2a0a5b22 | 309 | #endif |
d3a73acb | 310 | tm __PT_FLAGS+7(%r11),_PIF_PER_TRAP |
86ed42f4 | 311 | jo .Lsysc_singlestep |
86f2552b | 312 | tm __TI_flags+7(%r12),_TIF_SIGPENDING |
86ed42f4 | 313 | jo .Lsysc_sigpending |
86f2552b | 314 | tm __TI_flags+7(%r12),_TIF_NOTIFY_RESUME |
86ed42f4 | 315 | jo .Lsysc_notify_resume |
9977e886 HB |
316 | tm __LC_CPU_FLAGS+7,_CIF_FPU |
317 | jo .Lsysc_vxrs | |
d3a73acb | 318 | tm __LC_CPU_FLAGS+7,_CIF_ASCE |
86ed42f4 MS |
319 | jo .Lsysc_uaccess |
320 | j .Lsysc_return # beware of critical section cleanup | |
1da177e4 LT |
321 | |
322 | # | |
323 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf | 324 | # |
86ed42f4 MS |
325 | .Lsysc_reschedule: |
326 | larl %r14,.Lsysc_return | |
c5328901 | 327 | jg schedule |
1da177e4 | 328 | |
77fa2245 | 329 | # |
d3a73acb | 330 | # _CIF_MCCK_PENDING is set, call handler |
77fa2245 | 331 | # |
86ed42f4 MS |
332 | .Lsysc_mcck_pending: |
333 | larl %r14,.Lsysc_return | |
25d83cbf | 334 | jg s390_handle_mcck # TIF bit will be cleared by handler |
77fa2245 | 335 | |
457f2180 | 336 | # |
d3a73acb | 337 | # _CIF_ASCE is set, load user space asce |
457f2180 | 338 | # |
86ed42f4 | 339 | .Lsysc_uaccess: |
d3a73acb | 340 | ni __LC_CPU_FLAGS+7,255-_CIF_ASCE |
457f2180 | 341 | lctlg %c1,%c1,__LC_USER_ASCE # load primary asce |
86ed42f4 | 342 | j .Lsysc_return |
457f2180 | 343 | |
9977e886 HB |
344 | # |
345 | # CIF_FPU is set, restore floating-point controls and floating-point registers. | |
346 | # | |
347 | .Lsysc_vxrs: | |
348 | larl %r14,.Lsysc_return | |
349 | jg load_fpu_regs | |
350 | ||
1da177e4 | 351 | # |
02a029b3 | 352 | # _TIF_SIGPENDING is set, call do_signal |
1da177e4 | 353 | # |
86ed42f4 | 354 | .Lsysc_sigpending: |
c5328901 MS |
355 | lgr %r2,%r11 # pass pointer to pt_regs |
356 | brasl %r14,do_signal | |
d3a73acb | 357 | tm __PT_FLAGS+7(%r11),_PIF_SYSCALL |
86ed42f4 | 358 | jno .Lsysc_return |
c5328901 | 359 | lmg %r2,%r7,__PT_R2(%r11) # load svc arguments |
dbbfe487 | 360 | lg %r10,__TI_sysc_table(%r12) # address of system call table |
c5328901 | 361 | lghi %r8,0 # svc 0 returns -ENOSYS |
450e47da | 362 | llgh %r1,__PT_INT_CODE+2(%r11) # load new svc number |
b6ef5bb3 | 363 | cghi %r1,NR_syscalls |
86ed42f4 | 364 | jnl .Lsysc_nr_ok # invalid svc number -> do svc 0 |
c5328901 | 365 | slag %r8,%r1,2 |
86ed42f4 | 366 | j .Lsysc_nr_ok # restart svc |
1da177e4 | 367 | |
753c4dd6 MS |
368 | # |
369 | # _TIF_NOTIFY_RESUME is set, call do_notify_resume | |
370 | # | |
86ed42f4 | 371 | .Lsysc_notify_resume: |
c5328901 | 372 | lgr %r2,%r11 # pass pointer to pt_regs |
86ed42f4 | 373 | larl %r14,.Lsysc_return |
c5328901 | 374 | jg do_notify_resume |
753c4dd6 | 375 | |
2a0a5b22 JW |
376 | # |
377 | # _TIF_UPROBE is set, call uprobe_notify_resume | |
378 | # | |
379 | #ifdef CONFIG_UPROBES | |
86ed42f4 | 380 | .Lsysc_uprobe_notify: |
2a0a5b22 | 381 | lgr %r2,%r11 # pass pointer to pt_regs |
86ed42f4 | 382 | larl %r14,.Lsysc_return |
2a0a5b22 JW |
383 | jg uprobe_notify_resume |
384 | #endif | |
385 | ||
1da177e4 | 386 | # |
d3a73acb | 387 | # _PIF_PER_TRAP is set, call do_per_trap |
1da177e4 | 388 | # |
86ed42f4 | 389 | .Lsysc_singlestep: |
d3a73acb | 390 | ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP |
c5328901 | 391 | lgr %r2,%r11 # pass pointer to pt_regs |
86ed42f4 | 392 | larl %r14,.Lsysc_return |
5e9a2692 | 393 | jg do_per_trap |
1da177e4 | 394 | |
1da177e4 | 395 | # |
753c4dd6 MS |
396 | # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before |
397 | # and after the system call | |
1da177e4 | 398 | # |
86ed42f4 | 399 | .Lsysc_tracesys: |
c5328901 | 400 | lgr %r2,%r11 # pass pointer to pt_regs |
1da177e4 | 401 | la %r3,0 |
aa33c8cb | 402 | llgh %r0,__PT_INT_CODE+2(%r11) |
c5328901 | 403 | stg %r0,__PT_R2(%r11) |
753c4dd6 | 404 | brasl %r14,do_syscall_trace_enter |
1da177e4 | 405 | lghi %r0,NR_syscalls |
753c4dd6 | 406 | clgr %r0,%r2 |
86ed42f4 | 407 | jnh .Lsysc_tracenogo |
c5328901 MS |
408 | sllg %r8,%r2,2 |
409 | lgf %r9,0(%r8,%r10) | |
86ed42f4 | 410 | .Lsysc_tracego: |
c5328901 MS |
411 | lmg %r3,%r7,__PT_R3(%r11) |
412 | stg %r7,STACK_FRAME_OVERHEAD(%r15) | |
413 | lg %r2,__PT_ORIG_GPR2(%r11) | |
414 | basr %r14,%r9 # call sys_xxx | |
415 | stg %r2,__PT_R2(%r11) # store return value | |
86ed42f4 | 416 | .Lsysc_tracenogo: |
d3a73acb | 417 | tm __TI_flags+7(%r12),_TIF_TRACE |
86ed42f4 | 418 | jz .Lsysc_return |
c5328901 | 419 | lgr %r2,%r11 # pass pointer to pt_regs |
86ed42f4 | 420 | larl %r14,.Lsysc_return |
753c4dd6 | 421 | jg do_syscall_trace_exit |
1da177e4 LT |
422 | |
423 | # | |
424 | # a new process exits the kernel with ret_from_fork | |
425 | # | |
144d634a | 426 | ENTRY(ret_from_fork) |
c5328901 MS |
427 | la %r11,STACK_FRAME_OVERHEAD(%r15) |
428 | lg %r12,__LC_THREAD_INFO | |
37fe5d41 AV |
429 | brasl %r14,schedule_tail |
430 | TRACE_IRQS_ON | |
431 | ssm __LC_SVC_NEW_PSW # reenable interrupts | |
30dcb099 | 432 | tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ? |
86ed42f4 | 433 | jne .Lsysc_tracenogo |
30dcb099 AV |
434 | # it's a kernel thread |
435 | lmg %r9,%r10,__PT_R9(%r11) # load gprs | |
37fe5d41 AV |
436 | ENTRY(kernel_thread_starter) |
437 | la %r2,0(%r10) | |
438 | basr %r14,%r9 | |
86ed42f4 | 439 | j .Lsysc_tracenogo |
1da177e4 LT |
440 | |
441 | /* | |
442 | * Program check handler routine | |
443 | */ | |
444 | ||
144d634a | 445 | ENTRY(pgm_check_handler) |
c185b783 | 446 | stpt __LC_SYNC_ENTER_TIMER |
c5328901 MS |
447 | stmg %r8,%r15,__LC_SAVE_AREA_SYNC |
448 | lg %r10,__LC_LAST_BREAK | |
449 | lg %r12,__LC_THREAD_INFO | |
9977e886 | 450 | larl %r13,cleanup_critical |
c5328901 | 451 | lmg %r8,%r9,__LC_PGM_OLD_PSW |
c5328901 | 452 | tmhh %r8,0x0001 # test problem state bit |
d0fc4107 MS |
453 | jnz 2f # -> fault in user space |
454 | #if IS_ENABLED(CONFIG_KVM) | |
455 | # cleanup critical section for sie64a | |
456 | lgr %r14,%r9 | |
457 | slg %r14,BASED(.Lsie_critical_start) | |
458 | clg %r14,BASED(.Lsie_critical_length) | |
459 | jhe 0f | |
460 | brasl %r14,.Lcleanup_sie | |
461 | #endif | |
462 | 0: tmhh %r8,0x4000 # PER bit set in old PSW ? | |
463 | jnz 1f # -> enabled, can't be a double fault | |
c5328901 | 464 | tm __LC_PGM_ILC+3,0x80 # check for per exception |
86ed42f4 | 465 | jnz .Lpgm_svcper # -> single stepped svc |
d0fc4107 | 466 | 1: CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC |
dc7ee00d | 467 | aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) |
d0fc4107 | 468 | j 3f |
a359bb11 MS |
469 | 2: LAST_BREAK %r14 |
470 | UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER | |
c5328901 | 471 | lg %r15,__LC_KERNEL_STACK |
d35339a4 | 472 | lg %r14,__TI_task(%r12) |
3827ec3d | 473 | aghi %r14,__TASK_thread # pointer to thread_struct |
d35339a4 MS |
474 | lghi %r13,__LC_PGM_TDB |
475 | tm __LC_PGM_ILC+2,0x02 # check for transaction abort | |
d0fc4107 | 476 | jz 3f |
d35339a4 | 477 | mvc __THREAD_trap_tdb(256,%r14),0(%r13) |
d0fc4107 | 478 | 3: la %r11,STACK_FRAME_OVERHEAD(%r15) |
c5328901 MS |
479 | stmg %r0,%r7,__PT_R0(%r11) |
480 | mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC | |
481 | stmg %r8,%r9,__PT_PSW(%r11) | |
aa33c8cb MS |
482 | mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC |
483 | mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE | |
d3a73acb | 484 | xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) |
c5328901 MS |
485 | stg %r10,__PT_ARGS(%r11) |
486 | tm __LC_PGM_ILC+3,0x80 # check for per exception | |
d0fc4107 | 487 | jz 4f |
c5328901 | 488 | tmhh %r8,0x0001 # kernel per event ? |
86ed42f4 | 489 | jz .Lpgm_kprobe |
d3a73acb | 490 | oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP |
d35339a4 | 491 | mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS |
21ee7ffd JF |
492 | mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE |
493 | mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID | |
d0fc4107 | 494 | 4: REENABLE_IRQS |
c5328901 | 495 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) |
f5cdac27 | 496 | larl %r1,pgm_check_table |
aa33c8cb MS |
497 | llgh %r10,__PT_INT_CODE+2(%r11) |
498 | nill %r10,0x007f | |
b01a37a7 | 499 | sll %r10,2 |
a359bb11 | 500 | je .Lpgm_return |
b01a37a7 | 501 | lgf %r1,0(%r10,%r1) # load address of handler routine |
c5328901 | 502 | lgr %r2,%r11 # pass pointer to pt_regs |
f5cdac27 | 503 | basr %r14,%r1 # branch to interrupt-handler |
a359bb11 MS |
504 | .Lpgm_return: |
505 | LOCKDEP_SYS_EXIT | |
506 | tm __PT_PSW+1(%r11),0x01 # returning to user ? | |
507 | jno .Lsysc_restore | |
508 | j .Lsysc_tif | |
1da177e4 LT |
509 | |
510 | # | |
c5328901 | 511 | # PER event in supervisor state, must be kprobes |
1da177e4 | 512 | # |
86ed42f4 | 513 | .Lpgm_kprobe: |
c5328901 MS |
514 | REENABLE_IRQS |
515 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) | |
516 | lgr %r2,%r11 # pass pointer to pt_regs | |
517 | brasl %r14,do_per_trap | |
a359bb11 | 518 | j .Lpgm_return |
1da177e4 | 519 | |
4ba069b8 | 520 | # |
c5328901 | 521 | # single stepped system call |
4ba069b8 | 522 | # |
86ed42f4 | 523 | .Lpgm_svcper: |
c5328901 | 524 | mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW |
86ed42f4 | 525 | larl %r14,.Lsysc_per |
c5328901 | 526 | stg %r14,__LC_RETURN_PSW+8 |
d3a73acb | 527 | lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP |
86ed42f4 | 528 | lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs |
4ba069b8 | 529 | |
1da177e4 LT |
530 | /* |
531 | * IO interrupt handler routine | |
532 | */ | |
144d634a | 533 | ENTRY(io_int_handler) |
473e66ba | 534 | STCK __LC_INT_CLOCK |
9cfb9b3c | 535 | stpt __LC_ASYNC_ENTER_TIMER |
c5328901 MS |
536 | stmg %r8,%r15,__LC_SAVE_AREA_ASYNC |
537 | lg %r10,__LC_LAST_BREAK | |
538 | lg %r12,__LC_THREAD_INFO | |
9977e886 | 539 | larl %r13,cleanup_critical |
c5328901 | 540 | lmg %r8,%r9,__LC_IO_OLD_PSW |
2acb94f4 | 541 | SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER |
c5328901 MS |
542 | stmg %r0,%r7,__PT_R0(%r11) |
543 | mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC | |
544 | stmg %r8,%r9,__PT_PSW(%r11) | |
48f6b00c | 545 | mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID |
d3a73acb | 546 | xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) |
1f194a4c | 547 | TRACE_IRQS_OFF |
c5328901 | 548 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) |
86ed42f4 | 549 | .Lio_loop: |
c5328901 | 550 | lgr %r2,%r11 # pass pointer to pt_regs |
1f44a225 MS |
551 | lghi %r3,IO_INTERRUPT |
552 | tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ? | |
86ed42f4 | 553 | jz .Lio_call |
1f44a225 | 554 | lghi %r3,THIN_INTERRUPT |
86ed42f4 | 555 | .Lio_call: |
c5328901 | 556 | brasl %r14,do_IRQ |
48f6b00c | 557 | tm __LC_MACHINE_FLAGS+6,0x10 # MACHINE_FLAG_LPAR |
86ed42f4 | 558 | jz .Lio_return |
48f6b00c | 559 | tpi 0 |
86ed42f4 | 560 | jz .Lio_return |
48f6b00c | 561 | mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID |
86ed42f4 MS |
562 | j .Lio_loop |
563 | .Lio_return: | |
6a2df3a8 MS |
564 | LOCKDEP_SYS_EXIT |
565 | TRACE_IRQS_ON | |
86ed42f4 | 566 | .Lio_tif: |
d3a73acb | 567 | tm __TI_flags+7(%r12),_TIF_WORK |
86ed42f4 | 568 | jnz .Lio_work # there is work to do (signals etc.) |
d3a73acb | 569 | tm __LC_CPU_FLAGS+7,_CIF_WORK |
86ed42f4 MS |
570 | jnz .Lio_work |
571 | .Lio_restore: | |
c5328901 MS |
572 | lg %r14,__LC_VDSO_PER_CPU |
573 | lmg %r0,%r10,__PT_R0(%r11) | |
574 | mvc __LC_RETURN_PSW(16),__PT_PSW(%r11) | |
c5328901 MS |
575 | stpt __LC_EXIT_TIMER |
576 | mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER | |
577 | lmg %r11,%r15,__PT_R11(%r11) | |
578 | lpswe __LC_RETURN_PSW | |
86ed42f4 | 579 | .Lio_done: |
1da177e4 | 580 | |
2688905e | 581 | # |
43d399d2 | 582 | # There is work todo, find out in which context we have been interrupted: |
d3a73acb | 583 | # 1) if we return to user space we can do all _TIF_WORK work |
43d399d2 MS |
584 | # 2) if we return to kernel code and kvm is enabled check if we need to |
585 | # modify the psw to leave SIE | |
586 | # 3) if we return to kernel code and preemptive scheduling is enabled check | |
587 | # the preemption counter and if it is zero call preempt_schedule_irq | |
588 | # Before any work can be done, a switch to the kernel stack is required. | |
2688905e | 589 | # |
86ed42f4 | 590 | .Lio_work: |
c5328901 | 591 | tm __PT_PSW+1(%r11),0x01 # returning to user ? |
86ed42f4 | 592 | jo .Lio_work_user # yes -> do resched & signal |
43d399d2 | 593 | #ifdef CONFIG_PREEMPT |
2688905e | 594 | # check for preemptive scheduling |
86f2552b | 595 | icm %r0,15,__TI_precount(%r12) |
86ed42f4 | 596 | jnz .Lio_restore # preemption is disabled |
6a2df3a8 | 597 | tm __TI_flags+7(%r12),_TIF_NEED_RESCHED |
86ed42f4 | 598 | jno .Lio_restore |
1da177e4 | 599 | # switch to kernel stack |
c5328901 MS |
600 | lg %r1,__PT_R15(%r11) |
601 | aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE) | |
602 | mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11) | |
603 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) | |
604 | la %r11,STACK_FRAME_OVERHEAD(%r1) | |
1da177e4 | 605 | lgr %r15,%r1 |
86ed42f4 | 606 | # TRACE_IRQS_ON already done at .Lio_return, call |
6a2df3a8 MS |
607 | # TRACE_IRQS_OFF to keep things symmetrical |
608 | TRACE_IRQS_OFF | |
609 | brasl %r14,preempt_schedule_irq | |
86ed42f4 | 610 | j .Lio_return |
6a2df3a8 | 611 | #else |
86ed42f4 | 612 | j .Lio_restore |
6a2df3a8 | 613 | #endif |
1da177e4 | 614 | |
43d399d2 MS |
615 | # |
616 | # Need to do work before returning to userspace, switch to kernel stack | |
617 | # | |
86ed42f4 | 618 | .Lio_work_user: |
1da177e4 | 619 | lg %r1,__LC_KERNEL_STACK |
c5328901 MS |
620 | mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11) |
621 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) | |
622 | la %r11,STACK_FRAME_OVERHEAD(%r1) | |
1da177e4 | 623 | lgr %r15,%r1 |
43d399d2 | 624 | |
1da177e4 LT |
625 | # |
626 | # One of the work bits is on. Find out which one. | |
1da177e4 | 627 | # |
86ed42f4 | 628 | .Lio_work_tif: |
d3a73acb | 629 | tm __LC_CPU_FLAGS+7,_CIF_MCCK_PENDING |
86ed42f4 | 630 | jo .Lio_mcck_pending |
86f2552b | 631 | tm __TI_flags+7(%r12),_TIF_NEED_RESCHED |
86ed42f4 | 632 | jo .Lio_reschedule |
86f2552b | 633 | tm __TI_flags+7(%r12),_TIF_SIGPENDING |
86ed42f4 | 634 | jo .Lio_sigpending |
86f2552b | 635 | tm __TI_flags+7(%r12),_TIF_NOTIFY_RESUME |
86ed42f4 | 636 | jo .Lio_notify_resume |
9977e886 HB |
637 | tm __LC_CPU_FLAGS+7,_CIF_FPU |
638 | jo .Lio_vxrs | |
d3a73acb | 639 | tm __LC_CPU_FLAGS+7,_CIF_ASCE |
86ed42f4 MS |
640 | jo .Lio_uaccess |
641 | j .Lio_return # beware of critical section cleanup | |
0eaeafa1 | 642 | |
77fa2245 | 643 | # |
d3a73acb | 644 | # _CIF_MCCK_PENDING is set, call handler |
77fa2245 | 645 | # |
86ed42f4 MS |
646 | .Lio_mcck_pending: |
647 | # TRACE_IRQS_ON already done at .Lio_return | |
b771aeac | 648 | brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler |
6a2df3a8 | 649 | TRACE_IRQS_OFF |
86ed42f4 | 650 | j .Lio_return |
77fa2245 | 651 | |
457f2180 | 652 | # |
d3a73acb | 653 | # _CIF_ASCE is set, load user space asce |
457f2180 | 654 | # |
86ed42f4 | 655 | .Lio_uaccess: |
d3a73acb | 656 | ni __LC_CPU_FLAGS+7,255-_CIF_ASCE |
457f2180 | 657 | lctlg %c1,%c1,__LC_USER_ASCE # load primary asce |
86ed42f4 | 658 | j .Lio_return |
457f2180 | 659 | |
9977e886 HB |
660 | # |
661 | # CIF_FPU is set, restore floating-point controls and floating-point registers. | |
662 | # | |
663 | .Lio_vxrs: | |
664 | larl %r14,.Lio_return | |
665 | jg load_fpu_regs | |
666 | ||
1da177e4 LT |
667 | # |
668 | # _TIF_NEED_RESCHED is set, call schedule | |
25d83cbf | 669 | # |
86ed42f4 MS |
670 | .Lio_reschedule: |
671 | # TRACE_IRQS_ON already done at .Lio_return | |
c5328901 | 672 | ssm __LC_SVC_NEW_PSW # reenable interrupts |
25d83cbf | 673 | brasl %r14,schedule # call scheduler |
c5328901 | 674 | ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts |
411788ea | 675 | TRACE_IRQS_OFF |
86ed42f4 | 676 | j .Lio_return |
1da177e4 LT |
677 | |
678 | # | |
02a029b3 | 679 | # _TIF_SIGPENDING or is set, call do_signal |
1da177e4 | 680 | # |
86ed42f4 MS |
681 | .Lio_sigpending: |
682 | # TRACE_IRQS_ON already done at .Lio_return | |
c5328901 MS |
683 | ssm __LC_SVC_NEW_PSW # reenable interrupts |
684 | lgr %r2,%r11 # pass pointer to pt_regs | |
685 | brasl %r14,do_signal | |
686 | ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts | |
411788ea | 687 | TRACE_IRQS_OFF |
86ed42f4 | 688 | j .Lio_return |
1da177e4 | 689 | |
753c4dd6 MS |
690 | # |
691 | # _TIF_NOTIFY_RESUME or is set, call do_notify_resume | |
692 | # | |
86ed42f4 MS |
693 | .Lio_notify_resume: |
694 | # TRACE_IRQS_ON already done at .Lio_return | |
c5328901 MS |
695 | ssm __LC_SVC_NEW_PSW # reenable interrupts |
696 | lgr %r2,%r11 # pass pointer to pt_regs | |
697 | brasl %r14,do_notify_resume | |
698 | ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts | |
753c4dd6 | 699 | TRACE_IRQS_OFF |
86ed42f4 | 700 | j .Lio_return |
753c4dd6 | 701 | |
1da177e4 LT |
702 | /* |
703 | * External interrupt handler routine | |
704 | */ | |
144d634a | 705 | ENTRY(ext_int_handler) |
473e66ba | 706 | STCK __LC_INT_CLOCK |
9cfb9b3c | 707 | stpt __LC_ASYNC_ENTER_TIMER |
c5328901 MS |
708 | stmg %r8,%r15,__LC_SAVE_AREA_ASYNC |
709 | lg %r10,__LC_LAST_BREAK | |
710 | lg %r12,__LC_THREAD_INFO | |
9977e886 | 711 | larl %r13,cleanup_critical |
c5328901 | 712 | lmg %r8,%r9,__LC_EXT_OLD_PSW |
2acb94f4 | 713 | SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER |
c5328901 MS |
714 | stmg %r0,%r7,__PT_R0(%r11) |
715 | mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC | |
716 | stmg %r8,%r9,__PT_PSW(%r11) | |
48f6b00c MS |
717 | lghi %r1,__LC_EXT_PARAMS2 |
718 | mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR | |
719 | mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS | |
720 | mvc __PT_INT_PARM_LONG(8,%r11),0(%r1) | |
d3a73acb | 721 | xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) |
1f194a4c | 722 | TRACE_IRQS_OFF |
0de9db37 | 723 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) |
c5328901 | 724 | lgr %r2,%r11 # pass pointer to pt_regs |
1f44a225 MS |
725 | lghi %r3,EXT_INTERRUPT |
726 | brasl %r14,do_IRQ | |
86ed42f4 | 727 | j .Lio_return |
1da177e4 | 728 | |
4c1051e3 | 729 | /* |
86ed42f4 | 730 | * Load idle PSW. The second "half" of this function is in .Lcleanup_idle. |
4c1051e3 MS |
731 | */ |
732 | ENTRY(psw_idle) | |
27f6b416 | 733 | stg %r3,__SF_EMPTY(%r15) |
86ed42f4 | 734 | larl %r1,.Lpsw_idle_lpsw+4 |
4c1051e3 | 735 | stg %r1,__SF_EMPTY+8(%r15) |
72d38b19 MS |
736 | #ifdef CONFIG_SMP |
737 | larl %r1,smp_cpu_mtid | |
738 | llgf %r1,0(%r1) | |
739 | ltgr %r1,%r1 | |
740 | jz .Lpsw_idle_stcctm | |
741 | .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15) | |
742 | .Lpsw_idle_stcctm: | |
743 | #endif | |
27f6b416 MS |
744 | STCK __CLOCK_IDLE_ENTER(%r2) |
745 | stpt __TIMER_IDLE_ENTER(%r2) | |
86ed42f4 | 746 | .Lpsw_idle_lpsw: |
4c1051e3 MS |
747 | lpswe __SF_EMPTY(%r15) |
748 | br %r14 | |
86ed42f4 | 749 | .Lpsw_idle_end: |
4c1051e3 | 750 | |
9977e886 HB |
751 | /* Store floating-point controls and floating-point or vector extension |
752 | * registers instead. A critical section cleanup assures that the registers | |
753 | * are stored even if interrupted for some other work. The register %r2 | |
754 | * designates a struct fpu to store register contents. If the specified | |
755 | * structure does not contain a register save area, the register store is | |
756 | * omitted (see also comments in arch_dup_task_struct()). | |
757 | * | |
758 | * The CIF_FPU flag is set in any case. The CIF_FPU triggers a lazy restore | |
759 | * of the register contents at system call or io return. | |
760 | */ | |
761 | ENTRY(save_fpu_regs) | |
d0164ee2 HB |
762 | lg %r2,__LC_CURRENT |
763 | aghi %r2,__TASK_thread | |
9977e886 HB |
764 | tm __LC_CPU_FLAGS+7,_CIF_FPU |
765 | bor %r14 | |
d0164ee2 | 766 | stfpc __THREAD_FPU_fpc(%r2) |
9977e886 | 767 | .Lsave_fpu_regs_fpc_end: |
d0164ee2 | 768 | lg %r3,__THREAD_FPU_regs(%r2) |
9977e886 HB |
769 | ltgr %r3,%r3 |
770 | jz .Lsave_fpu_regs_done # no save area -> set CIF_FPU | |
d0164ee2 | 771 | tm __THREAD_FPU_flags+3(%r2),FPU_USE_VX |
9977e886 HB |
772 | jz .Lsave_fpu_regs_fp # no -> store FP regs |
773 | .Lsave_fpu_regs_vx_low: | |
774 | VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3) | |
775 | .Lsave_fpu_regs_vx_high: | |
776 | VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3) | |
777 | j .Lsave_fpu_regs_done # -> set CIF_FPU flag | |
778 | .Lsave_fpu_regs_fp: | |
779 | std 0,0(%r3) | |
780 | std 1,8(%r3) | |
781 | std 2,16(%r3) | |
782 | std 3,24(%r3) | |
783 | std 4,32(%r3) | |
784 | std 5,40(%r3) | |
785 | std 6,48(%r3) | |
786 | std 7,56(%r3) | |
787 | std 8,64(%r3) | |
788 | std 9,72(%r3) | |
789 | std 10,80(%r3) | |
790 | std 11,88(%r3) | |
791 | std 12,96(%r3) | |
792 | std 13,104(%r3) | |
793 | std 14,112(%r3) | |
794 | std 15,120(%r3) | |
795 | .Lsave_fpu_regs_done: | |
796 | oi __LC_CPU_FLAGS+7,_CIF_FPU | |
797 | br %r14 | |
798 | .Lsave_fpu_regs_end: | |
799 | ||
800 | /* Load floating-point controls and floating-point or vector extension | |
801 | * registers. A critical section cleanup assures that the register contents | |
802 | * are loaded even if interrupted for some other work. Depending on the saved | |
803 | * FP/VX state, the vector-enablement control, CR0.46, is either set or cleared. | |
804 | * | |
805 | * There are special calling conventions to fit into sysc and io return work: | |
9977e886 HB |
806 | * %r15: <kernel stack> |
807 | * The function requires: | |
808 | * %r4 and __SF_EMPTY+32(%r15) | |
809 | */ | |
810 | load_fpu_regs: | |
d0164ee2 HB |
811 | lg %r4,__LC_CURRENT |
812 | aghi %r4,__TASK_thread | |
9977e886 HB |
813 | tm __LC_CPU_FLAGS+7,_CIF_FPU |
814 | bnor %r14 | |
d0164ee2 | 815 | lfpc __THREAD_FPU_fpc(%r4) |
9977e886 | 816 | stctg %c0,%c0,__SF_EMPTY+32(%r15) # store CR0 |
d0164ee2 HB |
817 | tm __THREAD_FPU_flags+3(%r4),FPU_USE_VX # VX-enabled task ? |
818 | lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area | |
9977e886 HB |
819 | jz .Lload_fpu_regs_fp_ctl # -> no VX, load FP regs |
820 | .Lload_fpu_regs_vx_ctl: | |
821 | tm __SF_EMPTY+32+5(%r15),2 # test VX control | |
822 | jo .Lload_fpu_regs_vx | |
823 | oi __SF_EMPTY+32+5(%r15),2 # set VX control | |
824 | lctlg %c0,%c0,__SF_EMPTY+32(%r15) | |
825 | .Lload_fpu_regs_vx: | |
826 | VLM %v0,%v15,0,%r4 | |
827 | .Lload_fpu_regs_vx_high: | |
828 | VLM %v16,%v31,256,%r4 | |
829 | j .Lload_fpu_regs_done | |
830 | .Lload_fpu_regs_fp_ctl: | |
831 | tm __SF_EMPTY+32+5(%r15),2 # test VX control | |
832 | jz .Lload_fpu_regs_fp | |
833 | ni __SF_EMPTY+32+5(%r15),253 # clear VX control | |
834 | lctlg %c0,%c0,__SF_EMPTY+32(%r15) | |
835 | .Lload_fpu_regs_fp: | |
836 | ld 0,0(%r4) | |
837 | ld 1,8(%r4) | |
838 | ld 2,16(%r4) | |
839 | ld 3,24(%r4) | |
840 | ld 4,32(%r4) | |
841 | ld 5,40(%r4) | |
842 | ld 6,48(%r4) | |
843 | ld 7,56(%r4) | |
844 | ld 8,64(%r4) | |
845 | ld 9,72(%r4) | |
846 | ld 10,80(%r4) | |
847 | ld 11,88(%r4) | |
848 | ld 12,96(%r4) | |
849 | ld 13,104(%r4) | |
850 | ld 14,112(%r4) | |
851 | ld 15,120(%r4) | |
852 | .Lload_fpu_regs_done: | |
853 | ni __LC_CPU_FLAGS+7,255-_CIF_FPU | |
854 | br %r14 | |
855 | .Lload_fpu_regs_end: | |
856 | ||
857 | /* Test and set the vector enablement control in CR0.46 */ | |
858 | ENTRY(__ctl_set_vx) | |
859 | stctg %c0,%c0,__SF_EMPTY(%r15) | |
860 | tm __SF_EMPTY+5(%r15),2 | |
861 | bor %r14 | |
862 | oi __SF_EMPTY+5(%r15),2 | |
863 | lctlg %c0,%c0,__SF_EMPTY(%r15) | |
864 | br %r14 | |
865 | .L__ctl_set_vx_end: | |
866 | ||
86ed42f4 | 867 | .L__critical_end: |
ae6aa2ea | 868 | |
1da177e4 LT |
869 | /* |
870 | * Machine check handler routines | |
871 | */ | |
144d634a | 872 | ENTRY(mcck_int_handler) |
473e66ba | 873 | STCK __LC_MCCK_CLOCK |
77fa2245 HC |
874 | la %r1,4095 # revalidate r1 |
875 | spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer | |
25d83cbf | 876 | lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs |
c5328901 MS |
877 | lg %r10,__LC_LAST_BREAK |
878 | lg %r12,__LC_THREAD_INFO | |
9977e886 | 879 | larl %r13,cleanup_critical |
c5328901 | 880 | lmg %r8,%r9,__LC_MCK_OLD_PSW |
25d83cbf | 881 | tm __LC_MCCK_CODE,0x80 # system damage? |
86ed42f4 | 882 | jo .Lmcck_panic # yes -> rest of mcck code invalid |
c5328901 MS |
883 | lghi %r14,__LC_CPU_TIMER_SAVE_AREA |
884 | mvc __LC_MCCK_ENTER_TIMER(8),0(%r14) | |
63b12246 | 885 | tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid? |
c5328901 | 886 | jo 3f |
63b12246 MS |
887 | la %r14,__LC_SYNC_ENTER_TIMER |
888 | clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER | |
889 | jl 0f | |
890 | la %r14,__LC_ASYNC_ENTER_TIMER | |
891 | 0: clc 0(8,%r14),__LC_EXIT_TIMER | |
c5328901 | 892 | jl 1f |
63b12246 | 893 | la %r14,__LC_EXIT_TIMER |
c5328901 MS |
894 | 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER |
895 | jl 2f | |
63b12246 | 896 | la %r14,__LC_LAST_UPDATE_TIMER |
c5328901 | 897 | 2: spt 0(%r14) |
6377981f | 898 | mvc __LC_MCCK_ENTER_TIMER(8),0(%r14) |
c5328901 | 899 | 3: tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid? |
86ed42f4 | 900 | jno .Lmcck_panic # no -> skip cleanup critical |
2acb94f4 | 901 | SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER |
86ed42f4 | 902 | .Lmcck_skip: |
6551fbdf MS |
903 | lghi %r14,__LC_GPREGS_SAVE_AREA+64 |
904 | stmg %r0,%r7,__PT_R0(%r11) | |
905 | mvc __PT_R8(64,%r11),0(%r14) | |
c5328901 | 906 | stmg %r8,%r9,__PT_PSW(%r11) |
d3a73acb | 907 | xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) |
c5328901 MS |
908 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) |
909 | lgr %r2,%r11 # pass pointer to pt_regs | |
77fa2245 | 910 | brasl %r14,s390_do_machine_check |
c5328901 | 911 | tm __PT_PSW+1(%r11),0x01 # returning to user ? |
86ed42f4 | 912 | jno .Lmcck_return |
77fa2245 | 913 | lg %r1,__LC_KERNEL_STACK # switch to kernel stack |
c5328901 MS |
914 | mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11) |
915 | xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) | |
916 | la %r11,STACK_FRAME_OVERHEAD(%r1) | |
77fa2245 | 917 | lgr %r15,%r1 |
c5328901 | 918 | ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off |
d3a73acb | 919 | tm __LC_CPU_FLAGS+7,_CIF_MCCK_PENDING |
86ed42f4 | 920 | jno .Lmcck_return |
1f194a4c | 921 | TRACE_IRQS_OFF |
77fa2245 | 922 | brasl %r14,s390_handle_mcck |
1f194a4c | 923 | TRACE_IRQS_ON |
86ed42f4 | 924 | .Lmcck_return: |
c5328901 MS |
925 | lg %r14,__LC_VDSO_PER_CPU |
926 | lmg %r0,%r10,__PT_R0(%r11) | |
927 | mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW | |
63b12246 MS |
928 | tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ? |
929 | jno 0f | |
930 | stpt __LC_EXIT_TIMER | |
c5328901 MS |
931 | mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER |
932 | 0: lmg %r11,%r15,__PT_R11(%r11) | |
933 | lpswe __LC_RETURN_MCCK_PSW | |
934 | ||
86ed42f4 | 935 | .Lmcck_panic: |
c5328901 | 936 | lg %r15,__LC_PANIC_STACK |
2acb94f4 | 937 | aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) |
86ed42f4 | 938 | j .Lmcck_skip |
1da177e4 | 939 | |
7dd6b334 MH |
940 | # |
941 | # PSW restart interrupt handler | |
942 | # | |
8b646bd7 | 943 | ENTRY(restart_int_handler) |
c5328901 | 944 | stg %r15,__LC_SAVE_AREA_RESTART |
8b646bd7 | 945 | lg %r15,__LC_RESTART_STACK |
c5328901 | 946 | aghi %r15,-__PT_SIZE # create pt_regs on stack |
8b646bd7 | 947 | xc 0(__PT_SIZE,%r15),0(%r15) |
c5328901 MS |
948 | stmg %r0,%r14,__PT_R0(%r15) |
949 | mvc __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART | |
950 | mvc __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw | |
8b646bd7 MS |
951 | aghi %r15,-STACK_FRAME_OVERHEAD # create stack frame on stack |
952 | xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15) | |
fbe76568 HC |
953 | lg %r1,__LC_RESTART_FN # load fn, parm & source cpu |
954 | lg %r2,__LC_RESTART_DATA | |
955 | lg %r3,__LC_RESTART_SOURCE | |
8b646bd7 MS |
956 | ltgr %r3,%r3 # test source cpu address |
957 | jm 1f # negative -> skip source stop | |
eb546195 | 958 | 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu |
8b646bd7 MS |
959 | brc 10,0b # wait for status stored |
960 | 1: basr %r14,%r1 # call function | |
961 | stap __SF_EMPTY(%r15) # store cpu address | |
962 | llgh %r3,__SF_EMPTY(%r15) | |
eb546195 | 963 | 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu |
8b646bd7 MS |
964 | brc 2,2b |
965 | 3: j 3b | |
7dd6b334 | 966 | |
860dba45 MS |
967 | .section .kprobes.text, "ax" |
968 | ||
1da177e4 LT |
969 | #ifdef CONFIG_CHECK_STACK |
970 | /* | |
971 | * The synchronous or the asynchronous stack overflowed. We are dead. | |
972 | * No need to properly save the registers, we are going to panic anyway. | |
973 | * Setup a pt_regs so that show_trace can provide a good call trace. | |
974 | */ | |
975 | stack_overflow: | |
dc7ee00d MS |
976 | lg %r15,__LC_PANIC_STACK # change to panic stack |
977 | la %r11,STACK_FRAME_OVERHEAD(%r15) | |
c5328901 MS |
978 | stmg %r0,%r7,__PT_R0(%r11) |
979 | stmg %r8,%r9,__PT_PSW(%r11) | |
980 | mvc __PT_R8(64,%r11),0(%r14) | |
981 | stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2 | |
c5328901 MS |
982 | xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) |
983 | lgr %r2,%r11 # pass pointer to pt_regs | |
1da177e4 LT |
984 | jg kernel_stack_overflow |
985 | #endif | |
986 | ||
1da177e4 | 987 | cleanup_critical: |
d0fc4107 MS |
988 | #if IS_ENABLED(CONFIG_KVM) |
989 | clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap | |
990 | jl 0f | |
991 | clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done | |
992 | jl .Lcleanup_sie | |
993 | #endif | |
86ed42f4 | 994 | clg %r9,BASED(.Lcleanup_table) # system_call |
1da177e4 | 995 | jl 0f |
86ed42f4 MS |
996 | clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc |
997 | jl .Lcleanup_system_call | |
998 | clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif | |
1da177e4 | 999 | jl 0f |
86ed42f4 MS |
1000 | clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore |
1001 | jl .Lcleanup_sysc_tif | |
1002 | clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done | |
1003 | jl .Lcleanup_sysc_restore | |
1004 | clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif | |
63b12246 | 1005 | jl 0f |
86ed42f4 MS |
1006 | clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore |
1007 | jl .Lcleanup_io_tif | |
1008 | clg %r9,BASED(.Lcleanup_table+56) # .Lio_done | |
1009 | jl .Lcleanup_io_restore | |
1010 | clg %r9,BASED(.Lcleanup_table+64) # psw_idle | |
4c1051e3 | 1011 | jl 0f |
86ed42f4 MS |
1012 | clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end |
1013 | jl .Lcleanup_idle | |
9977e886 HB |
1014 | clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs |
1015 | jl 0f | |
1016 | clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end | |
1017 | jl .Lcleanup_save_fpu_regs | |
1018 | clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs | |
1019 | jl 0f | |
1020 | clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end | |
1021 | jl .Lcleanup_load_fpu_regs | |
1022 | clg %r9,BASED(.Lcleanup_table+112) # __ctl_set_vx | |
1023 | jl 0f | |
1024 | clg %r9,BASED(.Lcleanup_table+120) # .L__ctl_set_vx_end | |
1025 | jl .Lcleanup___ctl_set_vx | |
c5328901 MS |
1026 | 0: br %r14 |
1027 | ||
d0fc4107 MS |
1028 | .align 8 |
1029 | .Lcleanup_table: | |
1030 | .quad system_call | |
1031 | .quad .Lsysc_do_svc | |
1032 | .quad .Lsysc_tif | |
1033 | .quad .Lsysc_restore | |
1034 | .quad .Lsysc_done | |
1035 | .quad .Lio_tif | |
1036 | .quad .Lio_restore | |
1037 | .quad .Lio_done | |
1038 | .quad psw_idle | |
1039 | .quad .Lpsw_idle_end | |
1040 | .quad save_fpu_regs | |
1041 | .quad .Lsave_fpu_regs_end | |
1042 | .quad load_fpu_regs | |
1043 | .quad .Lload_fpu_regs_end | |
1044 | .quad __ctl_set_vx | |
1045 | .quad .L__ctl_set_vx_end | |
1046 | ||
1047 | #if IS_ENABLED(CONFIG_KVM) | |
1048 | .Lcleanup_table_sie: | |
1049 | .quad .Lsie_gmap | |
1050 | .quad .Lsie_done | |
1051 | ||
1052 | .Lcleanup_sie: | |
1053 | lg %r9,__SF_EMPTY(%r15) # get control block pointer | |
1054 | tm __LC_MACHINE_FLAGS+6,0x20 # MACHINE_FLAG_LPP | |
1055 | jz 0f | |
1056 | .insn s,0xb2800000,__SF_EMPTY+16(%r15)# set host id | |
1057 | 0: ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE | |
1058 | lctlg %c1,%c1,__LC_USER_ASCE # load primary asce | |
1059 | larl %r9,sie_exit # skip forward to sie_exit | |
1060 | br %r14 | |
1061 | #endif | |
1da177e4 | 1062 | |
86ed42f4 | 1063 | .Lcleanup_system_call: |
c5328901 | 1064 | # check if stpt has been executed |
86ed42f4 | 1065 | clg %r9,BASED(.Lcleanup_system_call_insn) |
1da177e4 LT |
1066 | jh 0f |
1067 | mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER | |
c5328901 | 1068 | cghi %r11,__LC_SAVE_AREA_ASYNC |
6377981f | 1069 | je 0f |
c5328901 MS |
1070 | mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER |
1071 | 0: # check if stmg has been executed | |
86ed42f4 | 1072 | clg %r9,BASED(.Lcleanup_system_call_insn+8) |
1da177e4 | 1073 | jh 0f |
c5328901 MS |
1074 | mvc __LC_SAVE_AREA_SYNC(64),0(%r11) |
1075 | 0: # check if base register setup + TIF bit load has been done | |
86ed42f4 | 1076 | clg %r9,BASED(.Lcleanup_system_call_insn+16) |
c5328901 MS |
1077 | jhe 0f |
1078 | # set up saved registers r10 and r12 | |
1079 | stg %r10,16(%r11) # r10 last break | |
1080 | stg %r12,32(%r11) # r12 thread-info pointer | |
1081 | 0: # check if the user time update has been done | |
86ed42f4 | 1082 | clg %r9,BASED(.Lcleanup_system_call_insn+24) |
c5328901 MS |
1083 | jh 0f |
1084 | lg %r15,__LC_EXIT_TIMER | |
1085 | slg %r15,__LC_SYNC_ENTER_TIMER | |
1086 | alg %r15,__LC_USER_TIMER | |
1087 | stg %r15,__LC_USER_TIMER | |
1088 | 0: # check if the system time update has been done | |
86ed42f4 | 1089 | clg %r9,BASED(.Lcleanup_system_call_insn+32) |
c5328901 MS |
1090 | jh 0f |
1091 | lg %r15,__LC_LAST_UPDATE_TIMER | |
1092 | slg %r15,__LC_EXIT_TIMER | |
1093 | alg %r15,__LC_SYSTEM_TIMER | |
1094 | stg %r15,__LC_SYSTEM_TIMER | |
1095 | 0: # update accounting time stamp | |
1da177e4 | 1096 | mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER |
c5328901 MS |
1097 | # do LAST_BREAK |
1098 | lg %r9,16(%r11) | |
1099 | srag %r9,%r9,23 | |
86f2552b | 1100 | jz 0f |
c5328901 MS |
1101 | mvc __TI_last_break(8,%r12),16(%r11) |
1102 | 0: # set up saved register r11 | |
1103 | lg %r15,__LC_KERNEL_STACK | |
dc7ee00d MS |
1104 | la %r9,STACK_FRAME_OVERHEAD(%r15) |
1105 | stg %r9,24(%r11) # r11 pt_regs pointer | |
c5328901 | 1106 | # fill pt_regs |
dc7ee00d MS |
1107 | mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC |
1108 | stmg %r0,%r7,__PT_R0(%r9) | |
1109 | mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW | |
1110 | mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC | |
d3a73acb MS |
1111 | xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9) |
1112 | mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL | |
c5328901 | 1113 | # setup saved register r15 |
c5328901 MS |
1114 | stg %r15,56(%r11) # r15 stack pointer |
1115 | # set new psw address and exit | |
86ed42f4 | 1116 | larl %r9,.Lsysc_do_svc |
1da177e4 | 1117 | br %r14 |
86ed42f4 | 1118 | .Lcleanup_system_call_insn: |
25d83cbf | 1119 | .quad system_call |
86ed42f4 MS |
1120 | .quad .Lsysc_stmg |
1121 | .quad .Lsysc_per | |
a359bb11 | 1122 | .quad .Lsysc_vtime+36 |
86ed42f4 | 1123 | .quad .Lsysc_vtime+42 |
1da177e4 | 1124 | |
86ed42f4 MS |
1125 | .Lcleanup_sysc_tif: |
1126 | larl %r9,.Lsysc_tif | |
1da177e4 LT |
1127 | br %r14 |
1128 | ||
86ed42f4 MS |
1129 | .Lcleanup_sysc_restore: |
1130 | clg %r9,BASED(.Lcleanup_sysc_restore_insn) | |
6377981f | 1131 | je 0f |
c5328901 MS |
1132 | lg %r9,24(%r11) # get saved pointer to pt_regs |
1133 | mvc __LC_RETURN_PSW(16),__PT_PSW(%r9) | |
1134 | mvc 0(64,%r11),__PT_R8(%r9) | |
1135 | lmg %r0,%r7,__PT_R0(%r9) | |
1136 | 0: lmg %r8,%r9,__LC_RETURN_PSW | |
1da177e4 | 1137 | br %r14 |
86ed42f4 MS |
1138 | .Lcleanup_sysc_restore_insn: |
1139 | .quad .Lsysc_done - 4 | |
1da177e4 | 1140 | |
86ed42f4 MS |
1141 | .Lcleanup_io_tif: |
1142 | larl %r9,.Lio_tif | |
176b1803 MS |
1143 | br %r14 |
1144 | ||
86ed42f4 MS |
1145 | .Lcleanup_io_restore: |
1146 | clg %r9,BASED(.Lcleanup_io_restore_insn) | |
c5328901 MS |
1147 | je 0f |
1148 | lg %r9,24(%r11) # get saved r11 pointer to pt_regs | |
1149 | mvc __LC_RETURN_PSW(16),__PT_PSW(%r9) | |
c5328901 MS |
1150 | mvc 0(64,%r11),__PT_R8(%r9) |
1151 | lmg %r0,%r7,__PT_R0(%r9) | |
1152 | 0: lmg %r8,%r9,__LC_RETURN_PSW | |
ae6aa2ea | 1153 | br %r14 |
86ed42f4 MS |
1154 | .Lcleanup_io_restore_insn: |
1155 | .quad .Lio_done - 4 | |
ae6aa2ea | 1156 | |
86ed42f4 | 1157 | .Lcleanup_idle: |
4c1051e3 | 1158 | # copy interrupt clock & cpu timer |
27f6b416 MS |
1159 | mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK |
1160 | mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER | |
4c1051e3 MS |
1161 | cghi %r11,__LC_SAVE_AREA_ASYNC |
1162 | je 0f | |
27f6b416 MS |
1163 | mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK |
1164 | mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER | |
4c1051e3 | 1165 | 0: # check if stck & stpt have been executed |
86ed42f4 | 1166 | clg %r9,BASED(.Lcleanup_idle_insn) |
4c1051e3 | 1167 | jhe 1f |
27f6b416 MS |
1168 | mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2) |
1169 | mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2) | |
72d38b19 MS |
1170 | 1: # calculate idle cycles |
1171 | #ifdef CONFIG_SMP | |
1172 | clg %r9,BASED(.Lcleanup_idle_insn) | |
1173 | jl 3f | |
1174 | larl %r1,smp_cpu_mtid | |
1175 | llgf %r1,0(%r1) | |
1176 | ltgr %r1,%r1 | |
1177 | jz 3f | |
1178 | .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15) | |
1179 | larl %r3,mt_cycles | |
1180 | ag %r3,__LC_PERCPU_OFFSET | |
1181 | la %r4,__SF_EMPTY+16(%r15) | |
1182 | 2: lg %r0,0(%r3) | |
1183 | slg %r0,0(%r4) | |
1184 | alg %r0,64(%r4) | |
1185 | stg %r0,0(%r3) | |
1186 | la %r3,8(%r3) | |
1187 | la %r4,8(%r4) | |
1188 | brct %r1,2b | |
1189 | #endif | |
1190 | 3: # account system time going idle | |
4c1051e3 | 1191 | lg %r9,__LC_STEAL_TIMER |
27f6b416 | 1192 | alg %r9,__CLOCK_IDLE_ENTER(%r2) |
4c1051e3 MS |
1193 | slg %r9,__LC_LAST_UPDATE_CLOCK |
1194 | stg %r9,__LC_STEAL_TIMER | |
27f6b416 | 1195 | mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2) |
4c1051e3 MS |
1196 | lg %r9,__LC_SYSTEM_TIMER |
1197 | alg %r9,__LC_LAST_UPDATE_TIMER | |
27f6b416 | 1198 | slg %r9,__TIMER_IDLE_ENTER(%r2) |
4c1051e3 | 1199 | stg %r9,__LC_SYSTEM_TIMER |
27f6b416 | 1200 | mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2) |
4c1051e3 | 1201 | # prepare return psw |
0587d409 | 1202 | nihh %r8,0xfcfd # clear irq & wait state bits |
4c1051e3 MS |
1203 | lg %r9,48(%r11) # return from psw_idle |
1204 | br %r14 | |
86ed42f4 MS |
1205 | .Lcleanup_idle_insn: |
1206 | .quad .Lpsw_idle_lpsw | |
4c1051e3 | 1207 | |
9977e886 HB |
1208 | .Lcleanup_save_fpu_regs: |
1209 | tm __LC_CPU_FLAGS+7,_CIF_FPU | |
1210 | bor %r14 | |
1211 | clg %r9,BASED(.Lcleanup_save_fpu_regs_done) | |
1212 | jhe 5f | |
1213 | clg %r9,BASED(.Lcleanup_save_fpu_regs_fp) | |
1214 | jhe 4f | |
1215 | clg %r9,BASED(.Lcleanup_save_fpu_regs_vx_high) | |
1216 | jhe 3f | |
1217 | clg %r9,BASED(.Lcleanup_save_fpu_regs_vx_low) | |
1218 | jhe 2f | |
1219 | clg %r9,BASED(.Lcleanup_save_fpu_fpc_end) | |
1220 | jhe 1f | |
d0164ee2 | 1221 | lg %r2,__LC_CURRENT |
9380cf5a | 1222 | aghi %r2,__TASK_thread |
9977e886 | 1223 | 0: # Store floating-point controls |
d0164ee2 | 1224 | stfpc __THREAD_FPU_fpc(%r2) |
9977e886 | 1225 | 1: # Load register save area and check if VX is active |
d0164ee2 | 1226 | lg %r3,__THREAD_FPU_regs(%r2) |
9977e886 HB |
1227 | ltgr %r3,%r3 |
1228 | jz 5f # no save area -> set CIF_FPU | |
d0164ee2 | 1229 | tm __THREAD_FPU_flags+3(%r2),FPU_USE_VX |
9977e886 HB |
1230 | jz 4f # no VX -> store FP regs |
1231 | 2: # Store vector registers (V0-V15) | |
1232 | VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3) | |
1233 | 3: # Store vector registers (V16-V31) | |
1234 | VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3) | |
1235 | j 5f # -> done, set CIF_FPU flag | |
1236 | 4: # Store floating-point registers | |
1237 | std 0,0(%r3) | |
1238 | std 1,8(%r3) | |
1239 | std 2,16(%r3) | |
1240 | std 3,24(%r3) | |
1241 | std 4,32(%r3) | |
1242 | std 5,40(%r3) | |
1243 | std 6,48(%r3) | |
1244 | std 7,56(%r3) | |
1245 | std 8,64(%r3) | |
1246 | std 9,72(%r3) | |
1247 | std 10,80(%r3) | |
1248 | std 11,88(%r3) | |
1249 | std 12,96(%r3) | |
1250 | std 13,104(%r3) | |
1251 | std 14,112(%r3) | |
1252 | std 15,120(%r3) | |
1253 | 5: # Set CIF_FPU flag | |
1254 | oi __LC_CPU_FLAGS+7,_CIF_FPU | |
1255 | lg %r9,48(%r11) # return from save_fpu_regs | |
1256 | br %r14 | |
1257 | .Lcleanup_save_fpu_fpc_end: | |
1258 | .quad .Lsave_fpu_regs_fpc_end | |
1259 | .Lcleanup_save_fpu_regs_vx_low: | |
1260 | .quad .Lsave_fpu_regs_vx_low | |
1261 | .Lcleanup_save_fpu_regs_vx_high: | |
1262 | .quad .Lsave_fpu_regs_vx_high | |
1263 | .Lcleanup_save_fpu_regs_fp: | |
1264 | .quad .Lsave_fpu_regs_fp | |
1265 | .Lcleanup_save_fpu_regs_done: | |
1266 | .quad .Lsave_fpu_regs_done | |
1267 | ||
1268 | .Lcleanup_load_fpu_regs: | |
1269 | tm __LC_CPU_FLAGS+7,_CIF_FPU | |
1270 | bnor %r14 | |
1271 | clg %r9,BASED(.Lcleanup_load_fpu_regs_done) | |
1272 | jhe 1f | |
1273 | clg %r9,BASED(.Lcleanup_load_fpu_regs_fp) | |
1274 | jhe 2f | |
1275 | clg %r9,BASED(.Lcleanup_load_fpu_regs_fp_ctl) | |
1276 | jhe 3f | |
1277 | clg %r9,BASED(.Lcleanup_load_fpu_regs_vx_high) | |
1278 | jhe 4f | |
1279 | clg %r9,BASED(.Lcleanup_load_fpu_regs_vx) | |
1280 | jhe 5f | |
1281 | clg %r9,BASED(.Lcleanup_load_fpu_regs_vx_ctl) | |
1282 | jhe 6f | |
d0164ee2 | 1283 | lg %r4,__LC_CURRENT |
9380cf5a | 1284 | aghi %r4,__TASK_thread |
d0164ee2 HB |
1285 | lfpc __THREAD_FPU_fpc(%r4) |
1286 | tm __THREAD_FPU_flags+3(%r4),FPU_USE_VX # VX-enabled task ? | |
1287 | lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area | |
9977e886 HB |
1288 | jz 3f # -> no VX, load FP regs |
1289 | 6: # Set VX-enablement control | |
1290 | stctg %c0,%c0,__SF_EMPTY+32(%r15) # store CR0 | |
1291 | tm __SF_EMPTY+32+5(%r15),2 # test VX control | |
1292 | jo 5f | |
1293 | oi __SF_EMPTY+32+5(%r15),2 # set VX control | |
1294 | lctlg %c0,%c0,__SF_EMPTY+32(%r15) | |
1295 | 5: # Load V0 ..V15 registers | |
1296 | VLM %v0,%v15,0,%r4 | |
1297 | 4: # Load V16..V31 registers | |
1298 | VLM %v16,%v31,256,%r4 | |
1299 | j 1f | |
1300 | 3: # Clear VX-enablement control for FP | |
1301 | stctg %c0,%c0,__SF_EMPTY+32(%r15) # store CR0 | |
1302 | tm __SF_EMPTY+32+5(%r15),2 # test VX control | |
1303 | jz 2f | |
1304 | ni __SF_EMPTY+32+5(%r15),253 # clear VX control | |
1305 | lctlg %c0,%c0,__SF_EMPTY+32(%r15) | |
1306 | 2: # Load floating-point registers | |
1307 | ld 0,0(%r4) | |
1308 | ld 1,8(%r4) | |
1309 | ld 2,16(%r4) | |
1310 | ld 3,24(%r4) | |
1311 | ld 4,32(%r4) | |
1312 | ld 5,40(%r4) | |
1313 | ld 6,48(%r4) | |
1314 | ld 7,56(%r4) | |
1315 | ld 8,64(%r4) | |
1316 | ld 9,72(%r4) | |
1317 | ld 10,80(%r4) | |
1318 | ld 11,88(%r4) | |
1319 | ld 12,96(%r4) | |
1320 | ld 13,104(%r4) | |
1321 | ld 14,112(%r4) | |
1322 | ld 15,120(%r4) | |
1323 | 1: # Clear CIF_FPU bit | |
1324 | ni __LC_CPU_FLAGS+7,255-_CIF_FPU | |
1325 | lg %r9,48(%r11) # return from load_fpu_regs | |
1326 | br %r14 | |
1327 | .Lcleanup_load_fpu_regs_vx_ctl: | |
1328 | .quad .Lload_fpu_regs_vx_ctl | |
1329 | .Lcleanup_load_fpu_regs_vx: | |
1330 | .quad .Lload_fpu_regs_vx | |
1331 | .Lcleanup_load_fpu_regs_vx_high: | |
1332 | .quad .Lload_fpu_regs_vx_high | |
1333 | .Lcleanup_load_fpu_regs_fp_ctl: | |
1334 | .quad .Lload_fpu_regs_fp_ctl | |
1335 | .Lcleanup_load_fpu_regs_fp: | |
1336 | .quad .Lload_fpu_regs_fp | |
1337 | .Lcleanup_load_fpu_regs_done: | |
1338 | .quad .Lload_fpu_regs_done | |
1339 | ||
1340 | .Lcleanup___ctl_set_vx: | |
1341 | stctg %c0,%c0,__SF_EMPTY(%r15) | |
1342 | tm __SF_EMPTY+5(%r15),2 | |
1343 | bor %r14 | |
1344 | oi __SF_EMPTY+5(%r15),2 | |
1345 | lctlg %c0,%c0,__SF_EMPTY(%r15) | |
1346 | lg %r9,48(%r11) # return from __ctl_set_vx | |
1347 | br %r14 | |
1348 | ||
1da177e4 LT |
1349 | /* |
1350 | * Integer constants | |
1351 | */ | |
c5328901 | 1352 | .align 8 |
1da177e4 | 1353 | .Lcritical_start: |
86ed42f4 | 1354 | .quad .L__critical_start |
c5328901 | 1355 | .Lcritical_length: |
86ed42f4 | 1356 | .quad .L__critical_end - .L__critical_start |
61aa4884 | 1357 | #if IS_ENABLED(CONFIG_KVM) |
d0fc4107 | 1358 | .Lsie_critical_start: |
86ed42f4 | 1359 | .quad .Lsie_gmap |
7c470539 | 1360 | .Lsie_critical_length: |
86ed42f4 | 1361 | .quad .Lsie_done - .Lsie_gmap |
603d1a50 MS |
1362 | #endif |
1363 | ||
a876cb3f HC |
1364 | .section .rodata, "a" |
1365 | #define SYSCALL(esame,emu) .long esame | |
9bf1226b | 1366 | .globl sys_call_table |
1da177e4 LT |
1367 | sys_call_table: |
1368 | #include "syscalls.S" | |
1369 | #undef SYSCALL | |
1370 | ||
347a8dc3 | 1371 | #ifdef CONFIG_COMPAT |
1da177e4 | 1372 | |
a876cb3f | 1373 | #define SYSCALL(esame,emu) .long emu |
61649881 | 1374 | .globl sys_call_table_emu |
1da177e4 LT |
1375 | sys_call_table_emu: |
1376 | #include "syscalls.S" | |
1377 | #undef SYSCALL | |
1378 | #endif |