projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 0ad775db | 2 | * arch/s390/kernel/head64.S |
| 1da177e4 | 3 | * |
| 1844c9bc | 4 | * Copyright (C) IBM Corp. 1999,2010 |
| 0ad775db HC |
5 | * |
| 6 | * Author(s): Hartmut Penner <hp@de.ibm.com> | |
| 7 | * Martin Schwidefsky <schwidefsky@de.ibm.com> | |
| 8 | * Rob van der Heij <rvdhei@iae.nl> | |
| 9 | * Heiko Carstens <heiko.carstens@de.ibm.com> | |
| 1da177e4 | 10 | * |
| 1da177e4 LT |
11 | */ |
| 12 | ||
| 1844c9bc | 13 | #include <linux/init.h> |
| 144d634a | 14 | #include <linux/linkage.h> |
| 1844c9bc MS |
15 | #include <asm/asm-offsets.h> |
| 16 | #include <asm/thread_info.h> | |
| 17 | #include <asm/page.h> | |
| b1b70306 | 18 | |
| 1844c9bc | 19 | __HEAD |
| 144d634a | 20 | ENTRY(startup_continue) |
| 1844c9bc MS |
21 | larl %r1,sched_clock_base_cc |
| 22 | mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK | |
| 23 | larl %r13,.LPG1 # get base | |
| 25d83cbf HC |
24 | lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers |
| 25 | lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area | |
| 26 | # move IPL device to lowcore | |
| c742b31c MS |
27 | lghi %r0,__LC_PASTE |
| 28 | stg %r0,__LC_VDSO_PER_CPU | |
| e87bfe51 HC |
29 | # |
| 30 | # Setup stack | |
| 31 | # | |
| 25d83cbf | 32 | larl %r15,init_thread_union |
| 0c88ee5b | 33 | stg %r15,__LC_THREAD_INFO # cache thread info in lowcore |
| 25d83cbf HC |
34 | lg %r14,__TI_task(%r15) # cache current in lowcore |
| 35 | stg %r14,__LC_CURRENT | |
| 36 | aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE | |
| 37 | stg %r15,__LC_KERNEL_STACK # set end of kernel stack | |
| 38 | aghi %r15,-160 | |
| 1da177e4 | 39 | # |
| fe355b7f HY |
40 | # Save ipl parameters, clear bss memory, initialize storage key for kernel pages, |
| 41 | # and create a kernel NSS if the SAVESYS= parm is defined | |
| 1da177e4 | 42 | # |
| fe355b7f | 43 | brasl %r14,startup_init |
| 25d83cbf HC |
44 | lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space, |
| 45 | # virtual and never return ... | |
| 46 | .align 16 | |
| 1844c9bc | 47 | .LPG1: |
| 25d83cbf | 48 | .Lentry:.quad 0x0000000180000000,_stext |
| c76e70d3 | 49 | .Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space |
| 25d83cbf HC |
50 | .quad 0 # cr1: primary space segment table |
| 51 | .quad .Lduct # cr2: dispatchable unit control table | |
| 52 | .quad 0 # cr3: instruction authorization | |
| 53 | .quad 0 # cr4: instruction authorization | |
| 482b05dd | 54 | .quad .Lduct # cr5: primary-aste origin |
| 25d83cbf HC |
55 | .quad 0 # cr6: I/O interrupts |
| 56 | .quad 0 # cr7: secondary space segment table | |
| 57 | .quad 0 # cr8: access registers translation | |
| 58 | .quad 0 # cr9: tracing off | |
| 59 | .quad 0 # cr10: tracing off | |
| 60 | .quad 0 # cr11: tracing off | |
| 61 | .quad 0 # cr12: tracing off | |
| 62 | .quad 0 # cr13: home space segment table | |
| 63 | .quad 0xc0000000 # cr14: machine check handling off | |
| 64 | .quad 0 # cr15: linkage stack operations | |
| 25d83cbf | 65 | .Lpcmsk:.quad 0x0000000180000000 |
| 1da177e4 | 66 | .L4malign:.quad 0xffffffffffc00000 |
| 25d83cbf HC |
67 | .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8 |
| 68 | .Lnop: .long 0x07000700 | |
| b1b70306 HC |
69 | .Lparmaddr: |
| 70 | .quad PARMAREA | |
| 482b05dd GS |
71 | .align 64 |
| 72 | .Lduct: .long 0,0,0,0,.Lduald,0,0,0 | |
| 73 | .long 0,0,0,0,0,0,0,0 | |
| 74 | .align 128 | |
| 75 | .Lduald:.rept 8 | |
| 76 | .long 0x80000000,0,0,0 # invalid access-list entries | |
| 77 | .endr | |
| 1da177e4 | 78 | |
| 144d634a | 79 | ENTRY(_ehead) |
| 1844c9bc | 80 | |
| 1da177e4 | 81 | #ifdef CONFIG_SHARED_KERNEL |
| 57d84906 | 82 | .org 0x100000 - 0x11000 # head.o ends at 0x11000 |
| 1da177e4 | 83 | #endif |
| 25d83cbf | 84 | |
| 1da177e4 | 85 | # |
| b1b70306 | 86 | # startup-code, running in absolute addressing mode |
| 1da177e4 | 87 | # |
| 144d634a JG |
88 | ENTRY(_stext) |
| 89 | basr %r13,0 # get base | |
| 1e8e3383 | 90 | .LPG3: |
| 1da177e4 | 91 | # check control registers |
| 25d83cbf | 92 | stctg %c0,%c15,0(%r15) |
| d98e19cc | 93 | oi 6(%r15),0x60 # enable sigp emergency & external call |
| 25d83cbf HC |
94 | oi 4(%r15),0x10 # switch on low address proctection |
| 95 | lctlg %c0,%c15,0(%r15) | |
| 1da177e4 | 96 | |
| 25d83cbf HC |
97 | lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess |
| 98 | brasl %r14,start_kernel # go to C code | |
| 1da177e4 LT |
99 | # |
| 100 | # We returned from start_kernel ?!? PANIK | |
| 101 | # | |
| 25d83cbf HC |
102 | basr %r13,0 |
| 103 | lpswe .Ldw-.(%r13) # load disabled wait psw | |
| e87bfe51 | 104 | |
| 25d83cbf HC |
105 | .align 8 |
| 106 | .Ldw: .quad 0x0002000180000000,0x0000000000000000 | |
| 107 | .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 |