Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
8b646bd7 | 2 | * SMP related functions |
1da177e4 | 3 | * |
8b646bd7 MS |
4 | * Copyright IBM Corp. 1999,2012 |
5 | * Author(s): Denis Joseph Barrow, | |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
8b646bd7 MS |
13 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
14 | * the translation of logical to physical cpu ids. All new code that | |
15 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
16 | */ |
17 | ||
395d31d4 MS |
18 | #define KMSG_COMPONENT "cpu" |
19 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
20 | ||
f230886b | 21 | #include <linux/workqueue.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/init.h> | |
1da177e4 | 24 | #include <linux/mm.h> |
4e950f6f | 25 | #include <linux/err.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kernel_stat.h> | |
1da177e4 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/interrupt.h> |
3324e60a | 30 | #include <linux/irqflags.h> |
1da177e4 | 31 | #include <linux/cpu.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
60a0c68d | 33 | #include <linux/crash_dump.h> |
cbb870c8 | 34 | #include <asm/asm-offsets.h> |
1e3cab2f HC |
35 | #include <asm/switch_to.h> |
36 | #include <asm/facility.h> | |
46b05d26 | 37 | #include <asm/ipl.h> |
2b67fc46 | 38 | #include <asm/setup.h> |
1da177e4 | 39 | #include <asm/irq.h> |
1da177e4 | 40 | #include <asm/tlbflush.h> |
2b67fc46 | 41 | #include <asm/timer.h> |
411ed322 | 42 | #include <asm/lowcore.h> |
08d07968 | 43 | #include <asm/sclp.h> |
c742b31c | 44 | #include <asm/vdso.h> |
3ab121ab | 45 | #include <asm/debug.h> |
4857d4bb | 46 | #include <asm/os_info.h> |
a9ae32c3 | 47 | #include <asm/sigp.h> |
a806170e | 48 | #include "entry.h" |
1da177e4 | 49 | |
8b646bd7 MS |
50 | enum { |
51 | ec_schedule = 0, | |
52 | ec_call_function, | |
53 | ec_call_function_single, | |
54 | ec_stop_cpu, | |
55 | }; | |
08d07968 | 56 | |
8b646bd7 | 57 | enum { |
08d07968 HC |
58 | CPU_STATE_STANDBY, |
59 | CPU_STATE_CONFIGURED, | |
60 | }; | |
61 | ||
8b646bd7 MS |
62 | struct pcpu { |
63 | struct cpu cpu; | |
8b646bd7 MS |
64 | struct _lowcore *lowcore; /* lowcore page(s) for the cpu */ |
65 | unsigned long async_stack; /* async stack for the cpu */ | |
66 | unsigned long panic_stack; /* panic stack for the cpu */ | |
67 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ | |
68 | int state; /* physical cpu state */ | |
69 | u32 status; /* last status received via sigp */ | |
70 | u16 address; /* physical cpu address */ | |
71 | }; | |
72 | ||
73 | static u8 boot_cpu_type; | |
74 | static u16 boot_cpu_address; | |
75 | static struct pcpu pcpu_devices[NR_CPUS]; | |
76 | ||
dbd70fb4 | 77 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 78 | |
8b646bd7 MS |
79 | /* |
80 | * Signal processor helper functions. | |
81 | */ | |
82 | static inline int __pcpu_sigp(u16 addr, u8 order, u32 parm, u32 *status) | |
83 | { | |
84 | register unsigned int reg1 asm ("1") = parm; | |
85 | int cc; | |
08d07968 | 86 | |
8b646bd7 MS |
87 | asm volatile( |
88 | " sigp %1,%2,0(%3)\n" | |
89 | " ipm %0\n" | |
90 | " srl %0,28\n" | |
91 | : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); | |
92 | if (status && cc == 1) | |
93 | *status = reg1; | |
94 | return cc; | |
95 | } | |
1da177e4 | 96 | |
8b646bd7 | 97 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, u32 parm, u32 *status) |
5c0b912e | 98 | { |
8b646bd7 | 99 | int cc; |
5c0b912e | 100 | |
8b646bd7 MS |
101 | while (1) { |
102 | cc = __pcpu_sigp(addr, order, parm, status); | |
a9ae32c3 | 103 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
104 | return cc; |
105 | cpu_relax(); | |
5c0b912e | 106 | } |
5c0b912e HC |
107 | } |
108 | ||
8b646bd7 | 109 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 110 | { |
8b646bd7 MS |
111 | int cc, retry; |
112 | ||
113 | for (retry = 0; ; retry++) { | |
114 | cc = __pcpu_sigp(pcpu->address, order, parm, &pcpu->status); | |
a9ae32c3 | 115 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
116 | break; |
117 | if (retry >= 3) | |
118 | udelay(10); | |
119 | } | |
120 | return cc; | |
121 | } | |
122 | ||
123 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
124 | { | |
a9ae32c3 HC |
125 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
126 | 0, &pcpu->status) != SIGP_CC_STATUS_STORED) | |
8b646bd7 | 127 | return 0; |
a095a8a9 | 128 | return !!(pcpu->status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
129 | } |
130 | ||
131 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 132 | { |
a9ae32c3 HC |
133 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
134 | 0, &pcpu->status) != SIGP_CC_STATUS_STORED) | |
8b646bd7 | 135 | return 1; |
524b24ad HC |
136 | /* Status stored condition code is equivalent to cpu not running. */ |
137 | return 0; | |
a93b8ec1 HC |
138 | } |
139 | ||
1943f53c | 140 | /* |
8b646bd7 | 141 | * Find struct pcpu by cpu address. |
1943f53c | 142 | */ |
8b646bd7 | 143 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, int address) |
1943f53c MH |
144 | { |
145 | int cpu; | |
146 | ||
8b646bd7 MS |
147 | for_each_cpu(cpu, mask) |
148 | if (pcpu_devices[cpu].address == address) | |
149 | return pcpu_devices + cpu; | |
150 | return NULL; | |
151 | } | |
152 | ||
153 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
154 | { | |
155 | int order; | |
156 | ||
157 | set_bit(ec_bit, &pcpu->ec_mask); | |
158 | order = pcpu_running(pcpu) ? | |
a9ae32c3 | 159 | SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; |
8b646bd7 MS |
160 | pcpu_sigp_retry(pcpu, order, 0); |
161 | } | |
162 | ||
163 | static int __cpuinit pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) | |
164 | { | |
165 | struct _lowcore *lc; | |
166 | ||
167 | if (pcpu != &pcpu_devices[0]) { | |
168 | pcpu->lowcore = (struct _lowcore *) | |
169 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); | |
170 | pcpu->async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
171 | pcpu->panic_stack = __get_free_page(GFP_KERNEL); | |
172 | if (!pcpu->lowcore || !pcpu->panic_stack || !pcpu->async_stack) | |
173 | goto out; | |
1943f53c | 174 | } |
8b646bd7 MS |
175 | lc = pcpu->lowcore; |
176 | memcpy(lc, &S390_lowcore, 512); | |
177 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
178 | lc->async_stack = pcpu->async_stack + ASYNC_SIZE; | |
179 | lc->panic_stack = pcpu->panic_stack + PAGE_SIZE; | |
180 | lc->cpu_nr = cpu; | |
181 | #ifndef CONFIG_64BIT | |
182 | if (MACHINE_HAS_IEEE) { | |
183 | lc->extended_save_area_addr = get_zeroed_page(GFP_KERNEL); | |
184 | if (!lc->extended_save_area_addr) | |
185 | goto out; | |
186 | } | |
187 | #else | |
188 | if (vdso_alloc_per_cpu(lc)) | |
189 | goto out; | |
190 | #endif | |
191 | lowcore_ptr[cpu] = lc; | |
a9ae32c3 | 192 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 MS |
193 | return 0; |
194 | out: | |
195 | if (pcpu != &pcpu_devices[0]) { | |
196 | free_page(pcpu->panic_stack); | |
197 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
198 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
199 | } | |
200 | return -ENOMEM; | |
1943f53c MH |
201 | } |
202 | ||
9d0f46af HC |
203 | #ifdef CONFIG_HOTPLUG_CPU |
204 | ||
8b646bd7 | 205 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 206 | { |
a9ae32c3 | 207 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 MS |
208 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
209 | #ifndef CONFIG_64BIT | |
210 | if (MACHINE_HAS_IEEE) { | |
211 | struct _lowcore *lc = pcpu->lowcore; | |
212 | ||
213 | free_page((unsigned long) lc->extended_save_area_addr); | |
214 | lc->extended_save_area_addr = 0; | |
215 | } | |
216 | #else | |
217 | vdso_free_per_cpu(pcpu->lowcore); | |
218 | #endif | |
219 | if (pcpu != &pcpu_devices[0]) { | |
220 | free_page(pcpu->panic_stack); | |
221 | free_pages(pcpu->async_stack, ASYNC_ORDER); | |
222 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
223 | } | |
224 | } | |
225 | ||
9d0f46af HC |
226 | #endif /* CONFIG_HOTPLUG_CPU */ |
227 | ||
8b646bd7 MS |
228 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
229 | { | |
230 | struct _lowcore *lc = pcpu->lowcore; | |
231 | ||
232 | atomic_inc(&init_mm.context.attach_count); | |
233 | lc->cpu_nr = cpu; | |
234 | lc->percpu_offset = __per_cpu_offset[cpu]; | |
235 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
236 | lc->machine_flags = S390_lowcore.machine_flags; | |
237 | lc->ftrace_func = S390_lowcore.ftrace_func; | |
238 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; | |
239 | __ctl_store(lc->cregs_save_area, 0, 15); | |
240 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
241 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
242 | MAX_FACILITY_BIT/8); | |
243 | } | |
244 | ||
245 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
246 | { | |
247 | struct _lowcore *lc = pcpu->lowcore; | |
248 | struct thread_info *ti = task_thread_info(tsk); | |
249 | ||
250 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) + THREAD_SIZE; | |
251 | lc->thread_info = (unsigned long) task_thread_info(tsk); | |
252 | lc->current_task = (unsigned long) tsk; | |
253 | lc->user_timer = ti->user_timer; | |
254 | lc->system_timer = ti->system_timer; | |
255 | lc->steal_timer = 0; | |
256 | } | |
257 | ||
258 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
259 | { | |
260 | struct _lowcore *lc = pcpu->lowcore; | |
261 | ||
262 | lc->restart_stack = lc->kernel_stack; | |
263 | lc->restart_fn = (unsigned long) func; | |
264 | lc->restart_data = (unsigned long) data; | |
265 | lc->restart_source = -1UL; | |
a9ae32c3 | 266 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
267 | } |
268 | ||
269 | /* | |
270 | * Call function via PSW restart on pcpu and stop the current cpu. | |
271 | */ | |
272 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
273 | void *data, unsigned long stack) | |
274 | { | |
061da3df | 275 | struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 276 | unsigned long source_cpu = stap(); |
8b646bd7 MS |
277 | |
278 | __load_psw_mask(psw_kernel_bits); | |
fbe76568 | 279 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
280 | func(data); /* should not return */ |
281 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 282 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 283 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
284 | mem_assign_absolute(lc->restart_stack, stack); |
285 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
286 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
287 | mem_assign_absolute(lc->restart_source, source_cpu); | |
8b646bd7 | 288 | asm volatile( |
eb546195 | 289 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 290 | " brc 2,0b # busy, try again\n" |
eb546195 | 291 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 292 | " brc 2,1b # busy, try again\n" |
fbe76568 | 293 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
294 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
295 | : "0", "1", "cc"); | |
8b646bd7 MS |
296 | for (;;) ; |
297 | } | |
298 | ||
299 | /* | |
300 | * Call function on an online CPU. | |
301 | */ | |
302 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
303 | { | |
304 | struct pcpu *pcpu; | |
305 | ||
306 | /* Use the current cpu if it is online. */ | |
307 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
308 | if (!pcpu) | |
309 | /* Use the first online cpu. */ | |
310 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
311 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
312 | } | |
313 | ||
314 | /* | |
315 | * Call function on the ipl CPU. | |
316 | */ | |
317 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
318 | { | |
c6da39f2 MH |
319 | pcpu_delegate(&pcpu_devices[0], func, data, |
320 | pcpu_devices->panic_stack + PAGE_SIZE); | |
8b646bd7 MS |
321 | } |
322 | ||
323 | int smp_find_processor_id(u16 address) | |
324 | { | |
325 | int cpu; | |
326 | ||
327 | for_each_present_cpu(cpu) | |
328 | if (pcpu_devices[cpu].address == address) | |
329 | return cpu; | |
330 | return -1; | |
2c2df118 HC |
331 | } |
332 | ||
8b646bd7 | 333 | int smp_vcpu_scheduled(int cpu) |
85ac7ca5 | 334 | { |
8b646bd7 MS |
335 | return pcpu_running(pcpu_devices + cpu); |
336 | } | |
337 | ||
338 | void smp_yield(void) | |
339 | { | |
340 | if (MACHINE_HAS_DIAG44) | |
341 | asm volatile("diag 0,0,0x44"); | |
2c2df118 HC |
342 | } |
343 | ||
8b646bd7 | 344 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 345 | { |
8b646bd7 MS |
346 | if (MACHINE_HAS_DIAG9C) |
347 | asm volatile("diag %0,0,0x9c" | |
348 | : : "d" (pcpu_devices[cpu].address)); | |
349 | else if (MACHINE_HAS_DIAG44) | |
350 | asm volatile("diag 0,0,0x44"); | |
351 | } | |
352 | ||
353 | /* | |
354 | * Send cpus emergency shutdown signal. This gives the cpus the | |
355 | * opportunity to complete outstanding interrupts. | |
356 | */ | |
357 | void smp_emergency_stop(cpumask_t *cpumask) | |
358 | { | |
359 | u64 end; | |
360 | int cpu; | |
361 | ||
362 | end = get_clock() + (1000000UL << 12); | |
363 | for_each_cpu(cpu, cpumask) { | |
364 | struct pcpu *pcpu = pcpu_devices + cpu; | |
365 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
366 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
367 | 0, NULL) == SIGP_CC_BUSY && | |
8b646bd7 MS |
368 | get_clock() < end) |
369 | cpu_relax(); | |
370 | } | |
371 | while (get_clock() < end) { | |
372 | for_each_cpu(cpu, cpumask) | |
373 | if (pcpu_stopped(pcpu_devices + cpu)) | |
374 | cpumask_clear_cpu(cpu, cpumask); | |
375 | if (cpumask_empty(cpumask)) | |
376 | break; | |
85ac7ca5 | 377 | cpu_relax(); |
8b646bd7 | 378 | } |
85ac7ca5 MS |
379 | } |
380 | ||
8b646bd7 MS |
381 | /* |
382 | * Stop all cpus but the current one. | |
383 | */ | |
677d7623 | 384 | void smp_send_stop(void) |
1da177e4 | 385 | { |
85ac7ca5 MS |
386 | cpumask_t cpumask; |
387 | int cpu; | |
1da177e4 | 388 | |
677d7623 | 389 | /* Disable all interrupts/machine checks */ |
b50511e4 | 390 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); |
3324e60a | 391 | trace_hardirqs_off(); |
1da177e4 | 392 | |
3ab121ab | 393 | debug_set_critical(); |
85ac7ca5 MS |
394 | cpumask_copy(&cpumask, cpu_online_mask); |
395 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
396 | ||
8b646bd7 MS |
397 | if (oops_in_progress) |
398 | smp_emergency_stop(&cpumask); | |
1da177e4 | 399 | |
85ac7ca5 MS |
400 | /* stop all processors */ |
401 | for_each_cpu(cpu, &cpumask) { | |
8b646bd7 | 402 | struct pcpu *pcpu = pcpu_devices + cpu; |
a9ae32c3 | 403 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 404 | while (!pcpu_stopped(pcpu)) |
c6b5b847 HC |
405 | cpu_relax(); |
406 | } | |
407 | } | |
408 | ||
8b646bd7 MS |
409 | /* |
410 | * Stop the current cpu. | |
411 | */ | |
412 | void smp_stop_cpu(void) | |
413 | { | |
a9ae32c3 | 414 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 MS |
415 | for (;;) ; |
416 | } | |
417 | ||
1da177e4 LT |
418 | /* |
419 | * This is the main routine where commands issued by other | |
420 | * cpus are handled. | |
421 | */ | |
fde15c3a | 422 | static void do_ext_call_interrupt(struct ext_code ext_code, |
f6649a7e | 423 | unsigned int param32, unsigned long param64) |
1da177e4 | 424 | { |
39ce010d | 425 | unsigned long bits; |
8b646bd7 | 426 | int cpu; |
1da177e4 | 427 | |
8b646bd7 | 428 | cpu = smp_processor_id(); |
fde15c3a | 429 | if (ext_code.code == 0x1202) |
8b646bd7 | 430 | kstat_cpu(cpu).irqs[EXTINT_EXC]++; |
2a3a2d66 | 431 | else |
8b646bd7 | 432 | kstat_cpu(cpu).irqs[EXTINT_EMS]++; |
39ce010d HC |
433 | /* |
434 | * handle bit signal external calls | |
39ce010d | 435 | */ |
8b646bd7 | 436 | bits = xchg(&pcpu_devices[cpu].ec_mask, 0); |
1da177e4 | 437 | |
85ac7ca5 MS |
438 | if (test_bit(ec_stop_cpu, &bits)) |
439 | smp_stop_cpu(); | |
440 | ||
184748cc PZ |
441 | if (test_bit(ec_schedule, &bits)) |
442 | scheduler_ipi(); | |
443 | ||
39ce010d | 444 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a HC |
445 | generic_smp_call_function_interrupt(); |
446 | ||
447 | if (test_bit(ec_call_function_single, &bits)) | |
448 | generic_smp_call_function_single_interrupt(); | |
85ac7ca5 | 449 | |
1da177e4 LT |
450 | } |
451 | ||
630cd046 | 452 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
453 | { |
454 | int cpu; | |
455 | ||
630cd046 | 456 | for_each_cpu(cpu, mask) |
8b646bd7 | 457 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function); |
ca9fc75a HC |
458 | } |
459 | ||
460 | void arch_send_call_function_single_ipi(int cpu) | |
461 | { | |
8b646bd7 | 462 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
463 | } |
464 | ||
347a8dc3 | 465 | #ifndef CONFIG_64BIT |
1da177e4 LT |
466 | /* |
467 | * this function sends a 'purge tlb' signal to another CPU. | |
468 | */ | |
a806170e | 469 | static void smp_ptlb_callback(void *info) |
1da177e4 | 470 | { |
ba8a9229 | 471 | __tlb_flush_local(); |
1da177e4 LT |
472 | } |
473 | ||
474 | void smp_ptlb_all(void) | |
475 | { | |
15c8b6c1 | 476 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
477 | } |
478 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 479 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
480 | |
481 | /* | |
482 | * this function sends a 'reschedule' IPI to another CPU. | |
483 | * it goes straight through and wastes no time serializing | |
484 | * anything. Worst case is that we lose a reschedule ... | |
485 | */ | |
486 | void smp_send_reschedule(int cpu) | |
487 | { | |
8b646bd7 | 488 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
489 | } |
490 | ||
491 | /* | |
492 | * parameter area for the set/clear control bit callbacks | |
493 | */ | |
94c12cc7 | 494 | struct ec_creg_mask_parms { |
8b646bd7 MS |
495 | unsigned long orval; |
496 | unsigned long andval; | |
497 | int cr; | |
94c12cc7 | 498 | }; |
1da177e4 LT |
499 | |
500 | /* | |
501 | * callback for setting/clearing control bits | |
502 | */ | |
39ce010d HC |
503 | static void smp_ctl_bit_callback(void *info) |
504 | { | |
94c12cc7 | 505 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 506 | unsigned long cregs[16]; |
39ce010d | 507 | |
94c12cc7 | 508 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 509 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 510 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
511 | } |
512 | ||
513 | /* | |
514 | * Set a bit in a control register of all cpus | |
515 | */ | |
94c12cc7 MS |
516 | void smp_ctl_set_bit(int cr, int bit) |
517 | { | |
8b646bd7 | 518 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 519 | |
15c8b6c1 | 520 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 521 | } |
39ce010d | 522 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
523 | |
524 | /* | |
525 | * Clear a bit in a control register of all cpus | |
526 | */ | |
94c12cc7 MS |
527 | void smp_ctl_clear_bit(int cr, int bit) |
528 | { | |
8b646bd7 | 529 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 530 | |
15c8b6c1 | 531 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 532 | } |
39ce010d | 533 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 534 | |
60a0c68d | 535 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP) |
411ed322 | 536 | |
8b646bd7 MS |
537 | struct save_area *zfcpdump_save_areas[NR_CPUS + 1]; |
538 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); | |
539 | ||
540 | static void __init smp_get_save_area(int cpu, u16 address) | |
411ed322 | 541 | { |
8b646bd7 MS |
542 | void *lc = pcpu_devices[0].lowcore; |
543 | struct save_area *save_area; | |
544 | ||
60a0c68d | 545 | if (is_kdump_kernel()) |
411ed322 | 546 | return; |
8b646bd7 MS |
547 | if (!OLDMEM_BASE && (address == boot_cpu_address || |
548 | ipl_info.type != IPL_TYPE_FCP_DUMP)) | |
549 | return; | |
285f6722 | 550 | if (cpu >= NR_CPUS) { |
8b646bd7 MS |
551 | pr_warning("CPU %i exceeds the maximum %i and is excluded " |
552 | "from the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 553 | return; |
411ed322 | 554 | } |
8b646bd7 MS |
555 | save_area = kmalloc(sizeof(struct save_area), GFP_KERNEL); |
556 | if (!save_area) | |
557 | panic("could not allocate memory for save area\n"); | |
558 | zfcpdump_save_areas[cpu] = save_area; | |
559 | #ifdef CONFIG_CRASH_DUMP | |
560 | if (address == boot_cpu_address) { | |
561 | /* Copy the registers of the boot cpu. */ | |
562 | copy_oldmem_page(1, (void *) save_area, sizeof(*save_area), | |
563 | SAVE_AREA_BASE - PAGE_SIZE, 0); | |
564 | return; | |
565 | } | |
566 | #endif | |
567 | /* Get the registers of a non-boot cpu. */ | |
a9ae32c3 | 568 | __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL); |
8b646bd7 | 569 | memcpy_real(save_area, lc + SAVE_AREA_BASE, sizeof(*save_area)); |
411ed322 MH |
570 | } |
571 | ||
8b646bd7 | 572 | int smp_store_status(int cpu) |
08d07968 | 573 | { |
8b646bd7 | 574 | struct pcpu *pcpu; |
08d07968 | 575 | |
8b646bd7 | 576 | pcpu = pcpu_devices + cpu; |
a9ae32c3 HC |
577 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS, |
578 | 0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
8b646bd7 | 579 | return -EIO; |
08d07968 HC |
580 | return 0; |
581 | } | |
582 | ||
8b646bd7 | 583 | #else /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 584 | |
8b646bd7 | 585 | static inline void smp_get_save_area(int cpu, u16 address) { } |
08d07968 | 586 | |
8b646bd7 | 587 | #endif /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */ |
08d07968 | 588 | |
8b646bd7 | 589 | static struct sclp_cpu_info *smp_get_cpu_info(void) |
08d07968 | 590 | { |
8b646bd7 | 591 | static int use_sigp_detection; |
08d07968 | 592 | struct sclp_cpu_info *info; |
8b646bd7 MS |
593 | int address; |
594 | ||
595 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
596 | if (info && (use_sigp_detection || sclp_get_cpu_info(info))) { | |
597 | use_sigp_detection = 1; | |
598 | for (address = 0; address <= MAX_CPU_ADDRESS; address++) { | |
a9ae32c3 HC |
599 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) == |
600 | SIGP_CC_NOT_OPERATIONAL) | |
8b646bd7 MS |
601 | continue; |
602 | info->cpu[info->configured].address = address; | |
603 | info->configured++; | |
604 | } | |
605 | info->combined = info->configured; | |
08d07968 | 606 | } |
8b646bd7 | 607 | return info; |
08d07968 HC |
608 | } |
609 | ||
8b646bd7 MS |
610 | static int __devinit smp_add_present_cpu(int cpu); |
611 | ||
612 | static int __devinit __smp_rescan_cpus(struct sclp_cpu_info *info, | |
613 | int sysfs_add) | |
08d07968 | 614 | { |
8b646bd7 | 615 | struct pcpu *pcpu; |
08d07968 | 616 | cpumask_t avail; |
8b646bd7 | 617 | int cpu, nr, i; |
08d07968 | 618 | |
8b646bd7 | 619 | nr = 0; |
0f1959f5 | 620 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
621 | cpu = cpumask_first(&avail); |
622 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
623 | if (info->has_cpu_type && info->cpu[i].type != boot_cpu_type) | |
624 | continue; | |
625 | if (pcpu_find_address(cpu_present_mask, info->cpu[i].address)) | |
626 | continue; | |
627 | pcpu = pcpu_devices + cpu; | |
628 | pcpu->address = info->cpu[i].address; | |
629 | pcpu->state = (cpu >= info->configured) ? | |
630 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; | |
631 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
632 | set_cpu_present(cpu, true); | |
633 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
634 | set_cpu_present(cpu, false); | |
635 | else | |
636 | nr++; | |
637 | cpu = cpumask_next(cpu, &avail); | |
638 | } | |
639 | return nr; | |
1da177e4 LT |
640 | } |
641 | ||
48483b32 HC |
642 | static void __init smp_detect_cpus(void) |
643 | { | |
644 | unsigned int cpu, c_cpus, s_cpus; | |
645 | struct sclp_cpu_info *info; | |
48483b32 | 646 | |
8b646bd7 | 647 | info = smp_get_cpu_info(); |
48483b32 HC |
648 | if (!info) |
649 | panic("smp_detect_cpus failed to allocate memory\n"); | |
48483b32 HC |
650 | if (info->has_cpu_type) { |
651 | for (cpu = 0; cpu < info->combined; cpu++) { | |
8b646bd7 MS |
652 | if (info->cpu[cpu].address != boot_cpu_address) |
653 | continue; | |
654 | /* The boot cpu dictates the cpu type. */ | |
655 | boot_cpu_type = info->cpu[cpu].type; | |
656 | break; | |
48483b32 HC |
657 | } |
658 | } | |
8b646bd7 | 659 | c_cpus = s_cpus = 0; |
48483b32 | 660 | for (cpu = 0; cpu < info->combined; cpu++) { |
8b646bd7 | 661 | if (info->has_cpu_type && info->cpu[cpu].type != boot_cpu_type) |
48483b32 | 662 | continue; |
8b646bd7 MS |
663 | if (cpu < info->configured) { |
664 | smp_get_save_area(c_cpus, info->cpu[cpu].address); | |
665 | c_cpus++; | |
666 | } else | |
48483b32 | 667 | s_cpus++; |
48483b32 | 668 | } |
395d31d4 | 669 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 670 | get_online_cpus(); |
8b646bd7 | 671 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 672 | put_online_cpus(); |
8b646bd7 | 673 | kfree(info); |
48483b32 HC |
674 | } |
675 | ||
1da177e4 | 676 | /* |
39ce010d | 677 | * Activate a secondary processor. |
1da177e4 | 678 | */ |
8b646bd7 | 679 | static void __cpuinit smp_start_secondary(void *cpuvoid) |
1da177e4 | 680 | { |
8b646bd7 MS |
681 | S390_lowcore.last_update_clock = get_clock(); |
682 | S390_lowcore.restart_stack = (unsigned long) restart_stack; | |
683 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
684 | S390_lowcore.restart_data = 0; | |
685 | S390_lowcore.restart_source = -1UL; | |
686 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
687 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
688 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); | |
39ce010d | 689 | cpu_init(); |
5bfb5d69 | 690 | preempt_disable(); |
39ce010d | 691 | init_cpu_timer(); |
39ce010d | 692 | init_cpu_vtimer(); |
29b08d2b | 693 | pfault_init(); |
e545a614 | 694 | notify_cpu_starting(smp_processor_id()); |
ca9fc75a | 695 | ipi_call_lock(); |
0f1959f5 | 696 | set_cpu_online(smp_processor_id(), true); |
ca9fc75a | 697 | ipi_call_unlock(); |
1da177e4 | 698 | local_irq_enable(); |
39ce010d HC |
699 | /* cpu_idle will call schedule for us */ |
700 | cpu_idle(); | |
1da177e4 LT |
701 | } |
702 | ||
1da177e4 | 703 | /* Upping and downing of CPUs */ |
8239c25f | 704 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 705 | { |
8b646bd7 MS |
706 | struct pcpu *pcpu; |
707 | int rc; | |
1da177e4 | 708 | |
8b646bd7 MS |
709 | pcpu = pcpu_devices + cpu; |
710 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 711 | return -EIO; |
a9ae32c3 HC |
712 | if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != |
713 | SIGP_CC_ORDER_CODE_ACCEPTED) | |
08d07968 | 714 | return -EIO; |
e80e7813 | 715 | |
8b646bd7 MS |
716 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
717 | if (rc) | |
718 | return rc; | |
719 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 720 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 721 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
1da177e4 LT |
722 | while (!cpu_online(cpu)) |
723 | cpu_relax(); | |
724 | return 0; | |
725 | } | |
726 | ||
48483b32 | 727 | static int __init setup_possible_cpus(char *s) |
255acee7 | 728 | { |
8b646bd7 | 729 | int max, cpu; |
255acee7 | 730 | |
8b646bd7 MS |
731 | if (kstrtoint(s, 0, &max) < 0) |
732 | return 0; | |
88e01285 | 733 | init_cpu_possible(cpumask_of(0)); |
8b646bd7 | 734 | for (cpu = 1; cpu < max && cpu < nr_cpu_ids; cpu++) |
def6cfb7 | 735 | set_cpu_possible(cpu, true); |
37a33026 HC |
736 | return 0; |
737 | } | |
738 | early_param("possible_cpus", setup_possible_cpus); | |
739 | ||
48483b32 HC |
740 | #ifdef CONFIG_HOTPLUG_CPU |
741 | ||
39ce010d | 742 | int __cpu_disable(void) |
1da177e4 | 743 | { |
8b646bd7 | 744 | unsigned long cregs[16]; |
1da177e4 | 745 | |
8b646bd7 MS |
746 | set_cpu_online(smp_processor_id(), false); |
747 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 748 | pfault_fini(); |
8b646bd7 MS |
749 | /* Disable interrupt sources via control register. */ |
750 | __ctl_store(cregs, 0, 15); | |
751 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
752 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
753 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
754 | __ctl_load(cregs, 0, 15); | |
1da177e4 LT |
755 | return 0; |
756 | } | |
757 | ||
39ce010d | 758 | void __cpu_die(unsigned int cpu) |
1da177e4 | 759 | { |
8b646bd7 MS |
760 | struct pcpu *pcpu; |
761 | ||
1da177e4 | 762 | /* Wait until target cpu is down */ |
8b646bd7 MS |
763 | pcpu = pcpu_devices + cpu; |
764 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 765 | cpu_relax(); |
8b646bd7 | 766 | pcpu_free_lowcore(pcpu); |
050eef36 | 767 | atomic_dec(&init_mm.context.attach_count); |
1da177e4 LT |
768 | } |
769 | ||
b456d94a | 770 | void __noreturn cpu_die(void) |
1da177e4 LT |
771 | { |
772 | idle_task_exit(); | |
a9ae32c3 | 773 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 774 | for (;;) ; |
1da177e4 LT |
775 | } |
776 | ||
255acee7 HC |
777 | #endif /* CONFIG_HOTPLUG_CPU */ |
778 | ||
1da177e4 LT |
779 | void __init smp_prepare_cpus(unsigned int max_cpus) |
780 | { | |
39ce010d HC |
781 | /* request the 0x1201 emergency signal external interrupt */ |
782 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
783 | panic("Couldn't request external interrupt 0x1201"); | |
d98e19cc MS |
784 | /* request the 0x1202 external call external interrupt */ |
785 | if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0) | |
786 | panic("Couldn't request external interrupt 0x1202"); | |
8b646bd7 | 787 | smp_detect_cpus(); |
1da177e4 LT |
788 | } |
789 | ||
ea1f4eec | 790 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 791 | { |
8b646bd7 MS |
792 | struct pcpu *pcpu = pcpu_devices; |
793 | ||
794 | boot_cpu_address = stap(); | |
8b646bd7 MS |
795 | pcpu->state = CPU_STATE_CONFIGURED; |
796 | pcpu->address = boot_cpu_address; | |
797 | pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix(); | |
798 | pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE; | |
799 | pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE; | |
1da177e4 | 800 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
83a24e32 | 801 | cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
8b646bd7 MS |
802 | set_cpu_present(0, true); |
803 | set_cpu_online(0, true); | |
1da177e4 LT |
804 | } |
805 | ||
ea1f4eec | 806 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 807 | { |
1da177e4 LT |
808 | } |
809 | ||
02beaccc HC |
810 | void __init smp_setup_processor_id(void) |
811 | { | |
812 | S390_lowcore.cpu_nr = 0; | |
02beaccc HC |
813 | } |
814 | ||
1da177e4 LT |
815 | /* |
816 | * the frequency of the profiling timer can be changed | |
817 | * by writing a multiplier value into /proc/profile. | |
818 | * | |
819 | * usually you want to run this on all CPUs ;) | |
820 | */ | |
821 | int setup_profiling_timer(unsigned int multiplier) | |
822 | { | |
39ce010d | 823 | return 0; |
1da177e4 LT |
824 | } |
825 | ||
08d07968 | 826 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 827 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 828 | struct device_attribute *attr, char *buf) |
08d07968 HC |
829 | { |
830 | ssize_t count; | |
831 | ||
832 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 833 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
834 | mutex_unlock(&smp_cpu_state_mutex); |
835 | return count; | |
836 | } | |
837 | ||
8a25a2fd | 838 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
839 | struct device_attribute *attr, |
840 | const char *buf, size_t count) | |
08d07968 | 841 | { |
8b646bd7 MS |
842 | struct pcpu *pcpu; |
843 | int cpu, val, rc; | |
08d07968 HC |
844 | char delim; |
845 | ||
846 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
847 | return -EINVAL; | |
848 | if (val != 0 && val != 1) | |
849 | return -EINVAL; | |
9d40d2e3 | 850 | get_online_cpus(); |
0b18d318 | 851 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 852 | rc = -EBUSY; |
2c2df118 | 853 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 854 | cpu = dev->id; |
2c2df118 | 855 | if (cpu_online(cpu) || cpu == 0) |
08d07968 | 856 | goto out; |
8b646bd7 | 857 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
858 | rc = 0; |
859 | switch (val) { | |
860 | case 0: | |
8b646bd7 MS |
861 | if (pcpu->state != CPU_STATE_CONFIGURED) |
862 | break; | |
863 | rc = sclp_cpu_deconfigure(pcpu->address); | |
864 | if (rc) | |
865 | break; | |
866 | pcpu->state = CPU_STATE_STANDBY; | |
867 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
868 | topology_expect_change(); | |
08d07968 HC |
869 | break; |
870 | case 1: | |
8b646bd7 MS |
871 | if (pcpu->state != CPU_STATE_STANDBY) |
872 | break; | |
873 | rc = sclp_cpu_configure(pcpu->address); | |
874 | if (rc) | |
875 | break; | |
876 | pcpu->state = CPU_STATE_CONFIGURED; | |
877 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
878 | topology_expect_change(); | |
08d07968 HC |
879 | break; |
880 | default: | |
881 | break; | |
882 | } | |
883 | out: | |
08d07968 | 884 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 885 | put_online_cpus(); |
08d07968 HC |
886 | return rc ? rc : count; |
887 | } | |
8a25a2fd | 888 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
889 | #endif /* CONFIG_HOTPLUG_CPU */ |
890 | ||
8a25a2fd KS |
891 | static ssize_t show_cpu_address(struct device *dev, |
892 | struct device_attribute *attr, char *buf) | |
08d07968 | 893 | { |
8b646bd7 | 894 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 895 | } |
8a25a2fd | 896 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 897 | |
08d07968 HC |
898 | static struct attribute *cpu_common_attrs[] = { |
899 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 900 | &dev_attr_configure.attr, |
08d07968 | 901 | #endif |
8a25a2fd | 902 | &dev_attr_address.attr, |
08d07968 HC |
903 | NULL, |
904 | }; | |
905 | ||
906 | static struct attribute_group cpu_common_attr_group = { | |
907 | .attrs = cpu_common_attrs, | |
908 | }; | |
1da177e4 | 909 | |
8a25a2fd KS |
910 | static ssize_t show_idle_count(struct device *dev, |
911 | struct device_attribute *attr, char *buf) | |
fae8b22d | 912 | { |
4c1051e3 | 913 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
fae8b22d | 914 | unsigned long long idle_count; |
e98bbaaf | 915 | unsigned int sequence; |
fae8b22d | 916 | |
4c1051e3 MS |
917 | do { |
918 | sequence = ACCESS_ONCE(idle->sequence); | |
919 | idle_count = ACCESS_ONCE(idle->idle_count); | |
920 | if (ACCESS_ONCE(idle->idle_enter)) | |
921 | idle_count++; | |
922 | } while ((sequence & 1) || (idle->sequence != sequence)); | |
fae8b22d HC |
923 | return sprintf(buf, "%llu\n", idle_count); |
924 | } | |
8a25a2fd | 925 | static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); |
fae8b22d | 926 | |
8a25a2fd KS |
927 | static ssize_t show_idle_time(struct device *dev, |
928 | struct device_attribute *attr, char *buf) | |
fae8b22d | 929 | { |
4c1051e3 MS |
930 | struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id); |
931 | unsigned long long now, idle_time, idle_enter, idle_exit; | |
e98bbaaf | 932 | unsigned int sequence; |
fae8b22d | 933 | |
4c1051e3 MS |
934 | do { |
935 | now = get_clock(); | |
936 | sequence = ACCESS_ONCE(idle->sequence); | |
937 | idle_time = ACCESS_ONCE(idle->idle_time); | |
938 | idle_enter = ACCESS_ONCE(idle->idle_enter); | |
939 | idle_exit = ACCESS_ONCE(idle->idle_exit); | |
940 | } while ((sequence & 1) || (idle->sequence != sequence)); | |
941 | idle_time += idle_enter ? ((idle_exit ? : now) - idle_enter) : 0; | |
6f430924 | 942 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 943 | } |
8a25a2fd | 944 | static DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 945 | |
08d07968 | 946 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
947 | &dev_attr_idle_count.attr, |
948 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
949 | NULL, |
950 | }; | |
951 | ||
08d07968 HC |
952 | static struct attribute_group cpu_online_attr_group = { |
953 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
954 | }; |
955 | ||
2fc2d1e9 HC |
956 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
957 | unsigned long action, void *hcpu) | |
958 | { | |
959 | unsigned int cpu = (unsigned int)(long)hcpu; | |
8b646bd7 | 960 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 961 | struct device *s = &c->dev; |
fae8b22d | 962 | struct s390_idle_data *idle; |
d882ba69 | 963 | int err = 0; |
2fc2d1e9 HC |
964 | |
965 | switch (action) { | |
966 | case CPU_ONLINE: | |
8bb78442 | 967 | case CPU_ONLINE_FROZEN: |
fae8b22d | 968 | idle = &per_cpu(s390_idle, cpu); |
e98bbaaf | 969 | memset(idle, 0, sizeof(struct s390_idle_data)); |
d882ba69 | 970 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
971 | break; |
972 | case CPU_DEAD: | |
8bb78442 | 973 | case CPU_DEAD_FROZEN: |
08d07968 | 974 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
975 | break; |
976 | } | |
d882ba69 | 977 | return notifier_from_errno(err); |
2fc2d1e9 HC |
978 | } |
979 | ||
980 | static struct notifier_block __cpuinitdata smp_cpu_nb = { | |
39ce010d | 981 | .notifier_call = smp_cpu_notify, |
2fc2d1e9 HC |
982 | }; |
983 | ||
2bc89b5e | 984 | static int __devinit smp_add_present_cpu(int cpu) |
08d07968 | 985 | { |
8b646bd7 | 986 | struct cpu *c = &pcpu_devices[cpu].cpu; |
8a25a2fd | 987 | struct device *s = &c->dev; |
08d07968 HC |
988 | int rc; |
989 | ||
990 | c->hotpluggable = 1; | |
991 | rc = register_cpu(c, cpu); | |
992 | if (rc) | |
993 | goto out; | |
994 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
995 | if (rc) | |
996 | goto out_cpu; | |
83a24e32 HC |
997 | if (cpu_online(cpu)) { |
998 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
999 | if (rc) | |
1000 | goto out_online; | |
1001 | } | |
1002 | rc = topology_cpu_init(c); | |
1003 | if (rc) | |
1004 | goto out_topology; | |
1005 | return 0; | |
1006 | ||
1007 | out_topology: | |
1008 | if (cpu_online(cpu)) | |
1009 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1010 | out_online: | |
08d07968 HC |
1011 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1012 | out_cpu: | |
1013 | #ifdef CONFIG_HOTPLUG_CPU | |
1014 | unregister_cpu(c); | |
1015 | #endif | |
1016 | out: | |
1017 | return rc; | |
1018 | } | |
1019 | ||
1020 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1021 | |
67060d9c | 1022 | int __ref smp_rescan_cpus(void) |
08d07968 | 1023 | { |
8b646bd7 MS |
1024 | struct sclp_cpu_info *info; |
1025 | int nr; | |
08d07968 | 1026 | |
8b646bd7 MS |
1027 | info = smp_get_cpu_info(); |
1028 | if (!info) | |
1029 | return -ENOMEM; | |
9d40d2e3 | 1030 | get_online_cpus(); |
0b18d318 | 1031 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1032 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1033 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1034 | put_online_cpus(); |
8b646bd7 MS |
1035 | kfree(info); |
1036 | if (nr) | |
c10fde0d | 1037 | topology_schedule_update(); |
8b646bd7 | 1038 | return 0; |
1e489518 HC |
1039 | } |
1040 | ||
8a25a2fd KS |
1041 | static ssize_t __ref rescan_store(struct device *dev, |
1042 | struct device_attribute *attr, | |
c9be0a36 | 1043 | const char *buf, |
1e489518 HC |
1044 | size_t count) |
1045 | { | |
1046 | int rc; | |
1047 | ||
1048 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1049 | return rc ? rc : count; |
1050 | } | |
8a25a2fd | 1051 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1052 | #endif /* CONFIG_HOTPLUG_CPU */ |
1053 | ||
83a24e32 | 1054 | static int __init s390_smp_init(void) |
1da177e4 | 1055 | { |
83a24e32 | 1056 | int cpu, rc; |
2fc2d1e9 HC |
1057 | |
1058 | register_cpu_notifier(&smp_cpu_nb); | |
08d07968 | 1059 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1060 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1061 | if (rc) |
1062 | return rc; | |
1063 | #endif | |
1064 | for_each_present_cpu(cpu) { | |
1065 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1066 | if (rc) |
1067 | return rc; | |
1da177e4 LT |
1068 | } |
1069 | return 0; | |
1070 | } | |
83a24e32 | 1071 | subsys_initcall(s390_smp_init); |