Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Time of day based timer functions. |
3 | * | |
4 | * S390 version | |
d2fec595 | 5 | * Copyright IBM Corp. 1999, 2008 |
1da177e4 LT |
6 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
7 | * Martin Schwidefsky (schwidefsky@de.ibm.com), | |
8 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) | |
9 | * | |
10 | * Derived from "arch/i386/kernel/time.c" | |
11 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
12 | */ | |
13 | ||
feab6501 MS |
14 | #define KMSG_COMPONENT "time" |
15 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
16 | ||
052ff461 | 17 | #include <linux/kernel_stat.h> |
1da177e4 LT |
18 | #include <linux/errno.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/param.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/mm.h> | |
25 | #include <linux/interrupt.h> | |
750887de HC |
26 | #include <linux/cpu.h> |
27 | #include <linux/stop_machine.h> | |
1da177e4 | 28 | #include <linux/time.h> |
3fbacffb | 29 | #include <linux/device.h> |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/init.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/types.h> | |
34 | #include <linux/profile.h> | |
35 | #include <linux/timex.h> | |
36 | #include <linux/notifier.h> | |
189374ae | 37 | #include <linux/timekeeper_internal.h> |
5a62b192 | 38 | #include <linux/clockchips.h> |
5a0e3ad6 | 39 | #include <linux/gfp.h> |
860dba45 | 40 | #include <linux/kprobes.h> |
1da177e4 LT |
41 | #include <asm/uaccess.h> |
42 | #include <asm/delay.h> | |
1da177e4 | 43 | #include <asm/div64.h> |
b020632e | 44 | #include <asm/vdso.h> |
1da177e4 | 45 | #include <asm/irq.h> |
5a489b98 | 46 | #include <asm/irq_regs.h> |
27f6b416 | 47 | #include <asm/vtimer.h> |
d54853ef | 48 | #include <asm/etr.h> |
a806170e | 49 | #include <asm/cio.h> |
638ad34a | 50 | #include "entry.h" |
1da177e4 LT |
51 | |
52 | /* change this if you have some constant time drift */ | |
53 | #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) | |
54 | #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) | |
55 | ||
b6112ccb | 56 | u64 sched_clock_base_cc = -1; /* Force to data section. */ |
05e7ff7d | 57 | EXPORT_SYMBOL_GPL(sched_clock_base_cc); |
b6112ccb | 58 | |
5a62b192 | 59 | static DEFINE_PER_CPU(struct clock_event_device, comparators); |
1da177e4 | 60 | |
fdf03650 FZ |
61 | ATOMIC_NOTIFIER_HEAD(s390_epoch_delta_notifier); |
62 | EXPORT_SYMBOL(s390_epoch_delta_notifier); | |
63 | ||
1da177e4 LT |
64 | /* |
65 | * Scheduler clock - returns current time in nanosec units. | |
66 | */ | |
7a5388de | 67 | unsigned long long notrace sched_clock(void) |
1da177e4 | 68 | { |
1aae0560 | 69 | return tod_to_ns(get_tod_clock_monotonic()); |
1da177e4 | 70 | } |
7a5388de | 71 | NOKPROBE_SYMBOL(sched_clock); |
1da177e4 | 72 | |
32f65f27 JG |
73 | /* |
74 | * Monotonic_clock - returns # of nanoseconds passed since time_init() | |
75 | */ | |
76 | unsigned long long monotonic_clock(void) | |
77 | { | |
78 | return sched_clock(); | |
79 | } | |
80 | EXPORT_SYMBOL(monotonic_clock); | |
81 | ||
689911c7 | 82 | void tod_to_timeval(__u64 todval, struct timespec64 *xt) |
1da177e4 LT |
83 | { |
84 | unsigned long long sec; | |
85 | ||
86 | sec = todval >> 12; | |
87 | do_div(sec, 1000000); | |
b1e2ba8d | 88 | xt->tv_sec = sec; |
1da177e4 | 89 | todval -= (sec * 1000000) << 12; |
b1e2ba8d | 90 | xt->tv_nsec = ((todval * 1000) >> 12); |
1da177e4 | 91 | } |
b592e89a | 92 | EXPORT_SYMBOL(tod_to_timeval); |
1da177e4 | 93 | |
5a62b192 | 94 | void clock_comparator_work(void) |
1da177e4 | 95 | { |
5a62b192 | 96 | struct clock_event_device *cd; |
1da177e4 | 97 | |
5a62b192 | 98 | S390_lowcore.clock_comparator = -1ULL; |
eb7e7d76 | 99 | cd = this_cpu_ptr(&comparators); |
5a62b192 | 100 | cd->event_handler(cd); |
1da177e4 LT |
101 | } |
102 | ||
1da177e4 | 103 | /* |
5a62b192 | 104 | * Fixup the clock comparator. |
1da177e4 | 105 | */ |
5a62b192 | 106 | static void fixup_clock_comparator(unsigned long long delta) |
1da177e4 | 107 | { |
5a62b192 HC |
108 | /* If nobody is waiting there's nothing to fix. */ |
109 | if (S390_lowcore.clock_comparator == -1ULL) | |
1da177e4 | 110 | return; |
5a62b192 HC |
111 | S390_lowcore.clock_comparator += delta; |
112 | set_clock_comparator(S390_lowcore.clock_comparator); | |
1da177e4 LT |
113 | } |
114 | ||
8adbf78e | 115 | static int s390_next_event(unsigned long delta, |
5a62b192 | 116 | struct clock_event_device *evt) |
1da177e4 | 117 | { |
8adbf78e | 118 | S390_lowcore.clock_comparator = get_tod_clock() + delta; |
5a62b192 HC |
119 | set_clock_comparator(S390_lowcore.clock_comparator); |
120 | return 0; | |
1da177e4 LT |
121 | } |
122 | ||
d54853ef MS |
123 | /* |
124 | * Set up lowcore and control register of the current cpu to | |
125 | * enable TOD clock and clock comparator interrupts. | |
1da177e4 LT |
126 | */ |
127 | void init_cpu_timer(void) | |
128 | { | |
5a62b192 HC |
129 | struct clock_event_device *cd; |
130 | int cpu; | |
131 | ||
132 | S390_lowcore.clock_comparator = -1ULL; | |
133 | set_clock_comparator(S390_lowcore.clock_comparator); | |
134 | ||
135 | cpu = smp_processor_id(); | |
136 | cd = &per_cpu(comparators, cpu); | |
137 | cd->name = "comparator"; | |
8adbf78e | 138 | cd->features = CLOCK_EVT_FEAT_ONESHOT; |
5a62b192 HC |
139 | cd->mult = 16777; |
140 | cd->shift = 12; | |
141 | cd->min_delta_ns = 1; | |
142 | cd->max_delta_ns = LONG_MAX; | |
143 | cd->rating = 400; | |
320ab2b0 | 144 | cd->cpumask = cpumask_of(cpu); |
8adbf78e | 145 | cd->set_next_event = s390_next_event; |
5a62b192 HC |
146 | |
147 | clockevents_register_device(cd); | |
d54853ef MS |
148 | |
149 | /* Enable clock comparator timer interrupt. */ | |
150 | __ctl_set_bit(0,11); | |
151 | ||
d2fec595 | 152 | /* Always allow the timing alert external interrupt. */ |
d54853ef MS |
153 | __ctl_set_bit(0, 4); |
154 | } | |
155 | ||
fde15c3a | 156 | static void clock_comparator_interrupt(struct ext_code ext_code, |
f6649a7e MS |
157 | unsigned int param32, |
158 | unsigned long param64) | |
d54853ef | 159 | { |
420f42ec | 160 | inc_irq_stat(IRQEXT_CLK); |
d3d238c7 HC |
161 | if (S390_lowcore.clock_comparator == -1ULL) |
162 | set_clock_comparator(S390_lowcore.clock_comparator); | |
d54853ef MS |
163 | } |
164 | ||
d2fec595 MS |
165 | static void etr_timing_alert(struct etr_irq_parm *); |
166 | static void stp_timing_alert(struct stp_irq_parm *); | |
167 | ||
fde15c3a | 168 | static void timing_alert_interrupt(struct ext_code ext_code, |
f6649a7e | 169 | unsigned int param32, unsigned long param64) |
d2fec595 | 170 | { |
420f42ec | 171 | inc_irq_stat(IRQEXT_TLA); |
f6649a7e MS |
172 | if (param32 & 0x00c40000) |
173 | etr_timing_alert((struct etr_irq_parm *) ¶m32); | |
174 | if (param32 & 0x00038000) | |
175 | stp_timing_alert((struct stp_irq_parm *) ¶m32); | |
d2fec595 MS |
176 | } |
177 | ||
d54853ef | 178 | static void etr_reset(void); |
d2fec595 | 179 | static void stp_reset(void); |
d54853ef | 180 | |
689911c7 | 181 | void read_persistent_clock64(struct timespec64 *ts) |
d54853ef | 182 | { |
1aae0560 | 183 | tod_to_timeval(get_tod_clock() - TOD_UNIX_EPOCH, ts); |
1da177e4 | 184 | } |
d54853ef | 185 | |
689911c7 | 186 | void read_boot_clock64(struct timespec64 *ts) |
23970e38 MS |
187 | { |
188 | tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, ts); | |
1da177e4 LT |
189 | } |
190 | ||
8e19608e | 191 | static cycle_t read_tod_clock(struct clocksource *cs) |
dc64bef5 | 192 | { |
1aae0560 | 193 | return get_tod_clock(); |
dc64bef5 MS |
194 | } |
195 | ||
196 | static struct clocksource clocksource_tod = { | |
197 | .name = "tod", | |
d2cb0e6e | 198 | .rating = 400, |
dc64bef5 MS |
199 | .read = read_tod_clock, |
200 | .mask = -1ULL, | |
201 | .mult = 1000, | |
202 | .shift = 12, | |
cc02d809 | 203 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
dc64bef5 MS |
204 | }; |
205 | ||
f1b82746 MS |
206 | struct clocksource * __init clocksource_default_clock(void) |
207 | { | |
208 | return &clocksource_tod; | |
209 | } | |
dc64bef5 | 210 | |
79c74ecb | 211 | void update_vsyscall(struct timekeeper *tk) |
b020632e | 212 | { |
79c74ecb MS |
213 | u64 nsecps; |
214 | ||
876e7881 | 215 | if (tk->tkr_mono.clock != &clocksource_tod) |
b020632e MS |
216 | return; |
217 | ||
218 | /* Make userspace gettimeofday spin until we're done. */ | |
219 | ++vdso_data->tb_update_count; | |
220 | smp_wmb(); | |
876e7881 | 221 | vdso_data->xtime_tod_stamp = tk->tkr_mono.cycle_last; |
79c74ecb | 222 | vdso_data->xtime_clock_sec = tk->xtime_sec; |
876e7881 | 223 | vdso_data->xtime_clock_nsec = tk->tkr_mono.xtime_nsec; |
79c74ecb MS |
224 | vdso_data->wtom_clock_sec = |
225 | tk->xtime_sec + tk->wall_to_monotonic.tv_sec; | |
876e7881 PZ |
226 | vdso_data->wtom_clock_nsec = tk->tkr_mono.xtime_nsec + |
227 | + ((u64) tk->wall_to_monotonic.tv_nsec << tk->tkr_mono.shift); | |
228 | nsecps = (u64) NSEC_PER_SEC << tk->tkr_mono.shift; | |
79c74ecb MS |
229 | while (vdso_data->wtom_clock_nsec >= nsecps) { |
230 | vdso_data->wtom_clock_nsec -= nsecps; | |
231 | vdso_data->wtom_clock_sec++; | |
232 | } | |
b7eacb59 MS |
233 | |
234 | vdso_data->xtime_coarse_sec = tk->xtime_sec; | |
235 | vdso_data->xtime_coarse_nsec = | |
876e7881 | 236 | (long)(tk->tkr_mono.xtime_nsec >> tk->tkr_mono.shift); |
b7eacb59 MS |
237 | vdso_data->wtom_coarse_sec = |
238 | vdso_data->xtime_coarse_sec + tk->wall_to_monotonic.tv_sec; | |
239 | vdso_data->wtom_coarse_nsec = | |
240 | vdso_data->xtime_coarse_nsec + tk->wall_to_monotonic.tv_nsec; | |
241 | while (vdso_data->wtom_coarse_nsec >= NSEC_PER_SEC) { | |
242 | vdso_data->wtom_coarse_nsec -= NSEC_PER_SEC; | |
243 | vdso_data->wtom_coarse_sec++; | |
244 | } | |
245 | ||
876e7881 PZ |
246 | vdso_data->tk_mult = tk->tkr_mono.mult; |
247 | vdso_data->tk_shift = tk->tkr_mono.shift; | |
b020632e MS |
248 | smp_wmb(); |
249 | ++vdso_data->tb_update_count; | |
250 | } | |
251 | ||
252 | extern struct timezone sys_tz; | |
253 | ||
254 | void update_vsyscall_tz(void) | |
255 | { | |
256 | /* Make userspace gettimeofday spin until we're done. */ | |
257 | ++vdso_data->tb_update_count; | |
258 | smp_wmb(); | |
259 | vdso_data->tz_minuteswest = sys_tz.tz_minuteswest; | |
260 | vdso_data->tz_dsttime = sys_tz.tz_dsttime; | |
261 | smp_wmb(); | |
262 | ++vdso_data->tb_update_count; | |
263 | } | |
264 | ||
1da177e4 LT |
265 | /* |
266 | * Initialize the TOD clock and the CPU timer of | |
267 | * the boot cpu. | |
268 | */ | |
269 | void __init time_init(void) | |
270 | { | |
b6112ccb MS |
271 | /* Reset time synchronization interfaces. */ |
272 | etr_reset(); | |
273 | stp_reset(); | |
1da177e4 | 274 | |
1da177e4 | 275 | /* request the clock comparator external interrupt */ |
1dad093b TH |
276 | if (register_external_irq(EXT_IRQ_CLK_COMP, clock_comparator_interrupt)) |
277 | panic("Couldn't request external interrupt 0x1004"); | |
1da177e4 | 278 | |
d2fec595 | 279 | /* request the timing alert external interrupt */ |
1dad093b | 280 | if (register_external_irq(EXT_IRQ_TIMING_ALERT, timing_alert_interrupt)) |
d54853ef MS |
281 | panic("Couldn't request external interrupt 0x1406"); |
282 | ||
f8935983 | 283 | if (__clocksource_register(&clocksource_tod) != 0) |
ab96e798 MS |
284 | panic("Could not register TOD clock source"); |
285 | ||
d54853ef MS |
286 | /* Enable TOD clock interrupts on the boot cpu. */ |
287 | init_cpu_timer(); | |
ab96e798 | 288 | |
c185b783 | 289 | /* Enable cpu timer interrupts on the boot cpu. */ |
1da177e4 | 290 | vtime_init(); |
d54853ef MS |
291 | } |
292 | ||
d2fec595 MS |
293 | /* |
294 | * The time is "clock". old is what we think the time is. | |
295 | * Adjust the value by a multiple of jiffies and add the delta to ntp. | |
296 | * "delay" is an approximation how long the synchronization took. If | |
297 | * the time correction is positive, then "delay" is subtracted from | |
298 | * the time difference and only the remaining part is passed to ntp. | |
299 | */ | |
300 | static unsigned long long adjust_time(unsigned long long old, | |
301 | unsigned long long clock, | |
302 | unsigned long long delay) | |
303 | { | |
304 | unsigned long long delta, ticks; | |
305 | struct timex adjust; | |
306 | ||
307 | if (clock > old) { | |
308 | /* It is later than we thought. */ | |
309 | delta = ticks = clock - old; | |
310 | delta = ticks = (delta < delay) ? 0 : delta - delay; | |
311 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
312 | adjust.offset = ticks * (1000000 / HZ); | |
313 | } else { | |
314 | /* It is earlier than we thought. */ | |
315 | delta = ticks = old - clock; | |
316 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
317 | delta = -delta; | |
318 | adjust.offset = -ticks * (1000000 / HZ); | |
319 | } | |
8107d829 | 320 | sched_clock_base_cc += delta; |
d2fec595 | 321 | if (adjust.offset != 0) { |
feab6501 MS |
322 | pr_notice("The ETR interface has adjusted the clock " |
323 | "by %li microseconds\n", adjust.offset); | |
d2fec595 MS |
324 | adjust.modes = ADJ_OFFSET_SINGLESHOT; |
325 | do_adjtimex(&adjust); | |
326 | } | |
327 | return delta; | |
328 | } | |
329 | ||
330 | static DEFINE_PER_CPU(atomic_t, clock_sync_word); | |
8283cb43 | 331 | static DEFINE_MUTEX(clock_sync_mutex); |
d2fec595 MS |
332 | static unsigned long clock_sync_flags; |
333 | ||
334 | #define CLOCK_SYNC_HAS_ETR 0 | |
335 | #define CLOCK_SYNC_HAS_STP 1 | |
336 | #define CLOCK_SYNC_ETR 2 | |
337 | #define CLOCK_SYNC_STP 3 | |
338 | ||
339 | /* | |
340 | * The synchronous get_clock function. It will write the current clock | |
341 | * value to the clock pointer and return 0 if the clock is in sync with | |
342 | * the external time source. If the clock mode is local it will return | |
a8f6db4d | 343 | * -EOPNOTSUPP and -EAGAIN if the clock is not in sync with the external |
d2fec595 MS |
344 | * reference. |
345 | */ | |
346 | int get_sync_clock(unsigned long long *clock) | |
347 | { | |
348 | atomic_t *sw_ptr; | |
349 | unsigned int sw0, sw1; | |
350 | ||
351 | sw_ptr = &get_cpu_var(clock_sync_word); | |
352 | sw0 = atomic_read(sw_ptr); | |
1aae0560 | 353 | *clock = get_tod_clock(); |
d2fec595 | 354 | sw1 = atomic_read(sw_ptr); |
bd119ee2 | 355 | put_cpu_var(clock_sync_word); |
d2fec595 MS |
356 | if (sw0 == sw1 && (sw0 & 0x80000000U)) |
357 | /* Success: time is in sync. */ | |
358 | return 0; | |
359 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) && | |
360 | !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
a8f6db4d | 361 | return -EOPNOTSUPP; |
d2fec595 MS |
362 | if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) && |
363 | !test_bit(CLOCK_SYNC_STP, &clock_sync_flags)) | |
364 | return -EACCES; | |
365 | return -EAGAIN; | |
366 | } | |
367 | EXPORT_SYMBOL(get_sync_clock); | |
368 | ||
369 | /* | |
370 | * Make get_sync_clock return -EAGAIN. | |
371 | */ | |
372 | static void disable_sync_clock(void *dummy) | |
373 | { | |
eb7e7d76 | 374 | atomic_t *sw_ptr = this_cpu_ptr(&clock_sync_word); |
d2fec595 MS |
375 | /* |
376 | * Clear the in-sync bit 2^31. All get_sync_clock calls will | |
377 | * fail until the sync bit is turned back on. In addition | |
378 | * increase the "sequence" counter to avoid the race of an | |
379 | * etr event and the complete recovery against get_sync_clock. | |
380 | */ | |
805de8f4 | 381 | atomic_andnot(0x80000000, sw_ptr); |
d2fec595 MS |
382 | atomic_inc(sw_ptr); |
383 | } | |
384 | ||
385 | /* | |
386 | * Make get_sync_clock return 0 again. | |
387 | * Needs to be called from a context disabled for preemption. | |
388 | */ | |
389 | static void enable_sync_clock(void) | |
390 | { | |
eb7e7d76 | 391 | atomic_t *sw_ptr = this_cpu_ptr(&clock_sync_word); |
805de8f4 | 392 | atomic_or(0x80000000, sw_ptr); |
d2fec595 MS |
393 | } |
394 | ||
8283cb43 MS |
395 | /* |
396 | * Function to check if the clock is in sync. | |
397 | */ | |
398 | static inline int check_sync_clock(void) | |
399 | { | |
400 | atomic_t *sw_ptr; | |
401 | int rc; | |
402 | ||
403 | sw_ptr = &get_cpu_var(clock_sync_word); | |
404 | rc = (atomic_read(sw_ptr) & 0x80000000U) != 0; | |
bd119ee2 | 405 | put_cpu_var(clock_sync_word); |
8283cb43 MS |
406 | return rc; |
407 | } | |
408 | ||
750887de HC |
409 | /* Single threaded workqueue used for etr and stp sync events */ |
410 | static struct workqueue_struct *time_sync_wq; | |
411 | ||
412 | static void __init time_init_wq(void) | |
413 | { | |
179cb81a HC |
414 | if (time_sync_wq) |
415 | return; | |
416 | time_sync_wq = create_singlethread_workqueue("timesync"); | |
750887de HC |
417 | } |
418 | ||
d54853ef MS |
419 | /* |
420 | * External Time Reference (ETR) code. | |
421 | */ | |
422 | static int etr_port0_online; | |
423 | static int etr_port1_online; | |
d2fec595 | 424 | static int etr_steai_available; |
d54853ef MS |
425 | |
426 | static int __init early_parse_etr(char *p) | |
427 | { | |
428 | if (strncmp(p, "off", 3) == 0) | |
429 | etr_port0_online = etr_port1_online = 0; | |
430 | else if (strncmp(p, "port0", 5) == 0) | |
431 | etr_port0_online = 1; | |
432 | else if (strncmp(p, "port1", 5) == 0) | |
433 | etr_port1_online = 1; | |
434 | else if (strncmp(p, "on", 2) == 0) | |
435 | etr_port0_online = etr_port1_online = 1; | |
436 | return 0; | |
437 | } | |
438 | early_param("etr", early_parse_etr); | |
439 | ||
440 | enum etr_event { | |
441 | ETR_EVENT_PORT0_CHANGE, | |
442 | ETR_EVENT_PORT1_CHANGE, | |
443 | ETR_EVENT_PORT_ALERT, | |
444 | ETR_EVENT_SYNC_CHECK, | |
445 | ETR_EVENT_SWITCH_LOCAL, | |
446 | ETR_EVENT_UPDATE, | |
447 | }; | |
448 | ||
d54853ef MS |
449 | /* |
450 | * Valid bit combinations of the eacr register are (x = don't care): | |
451 | * e0 e1 dp p0 p1 ea es sl | |
452 | * 0 0 x 0 0 0 0 0 initial, disabled state | |
453 | * 0 0 x 0 1 1 0 0 port 1 online | |
454 | * 0 0 x 1 0 1 0 0 port 0 online | |
455 | * 0 0 x 1 1 1 0 0 both ports online | |
456 | * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode | |
457 | * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode | |
458 | * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync | |
459 | * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync | |
460 | * 0 1 x 1 1 1 0 0 both ports online, port 1 usable | |
461 | * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync | |
462 | * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync | |
463 | * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode | |
464 | * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode | |
465 | * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync | |
466 | * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync | |
467 | * 1 0 x 1 1 1 0 0 both ports online, port 0 usable | |
468 | * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync | |
469 | * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync | |
470 | * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync | |
471 | * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync | |
472 | */ | |
473 | static struct etr_eacr etr_eacr; | |
474 | static u64 etr_tolec; /* time of last eacr update */ | |
d54853ef MS |
475 | static struct etr_aib etr_port0; |
476 | static int etr_port0_uptodate; | |
477 | static struct etr_aib etr_port1; | |
478 | static int etr_port1_uptodate; | |
479 | static unsigned long etr_events; | |
480 | static struct timer_list etr_timer; | |
d54853ef MS |
481 | |
482 | static void etr_timeout(unsigned long dummy); | |
ecdcc023 | 483 | static void etr_work_fn(struct work_struct *work); |
0b3016b7 | 484 | static DEFINE_MUTEX(etr_work_mutex); |
ecdcc023 | 485 | static DECLARE_WORK(etr_work, etr_work_fn); |
d54853ef | 486 | |
d54853ef MS |
487 | /* |
488 | * Reset ETR attachment. | |
489 | */ | |
490 | static void etr_reset(void) | |
491 | { | |
492 | etr_eacr = (struct etr_eacr) { | |
493 | .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, | |
494 | .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, | |
495 | .es = 0, .sl = 0 }; | |
d2fec595 | 496 | if (etr_setr(&etr_eacr) == 0) { |
1aae0560 | 497 | etr_tolec = get_tod_clock(); |
d2fec595 | 498 | set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags); |
8283cb43 MS |
499 | if (etr_port0_online && etr_port1_online) |
500 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d2fec595 | 501 | } else if (etr_port0_online || etr_port1_online) { |
feab6501 MS |
502 | pr_warning("The real or virtual hardware system does " |
503 | "not provide an ETR interface\n"); | |
d2fec595 | 504 | etr_port0_online = etr_port1_online = 0; |
d54853ef MS |
505 | } |
506 | } | |
507 | ||
ecdcc023 | 508 | static int __init etr_init(void) |
d54853ef MS |
509 | { |
510 | struct etr_aib aib; | |
511 | ||
d2fec595 | 512 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
ecdcc023 | 513 | return 0; |
750887de | 514 | time_init_wq(); |
d54853ef MS |
515 | /* Check if this machine has the steai instruction. */ |
516 | if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) | |
d2fec595 | 517 | etr_steai_available = 1; |
d54853ef | 518 | setup_timer(&etr_timer, etr_timeout, 0UL); |
d54853ef MS |
519 | if (etr_port0_online) { |
520 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
750887de | 521 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
522 | } |
523 | if (etr_port1_online) { | |
524 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
750887de | 525 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 526 | } |
ecdcc023 | 527 | return 0; |
d54853ef MS |
528 | } |
529 | ||
ecdcc023 MS |
530 | arch_initcall(etr_init); |
531 | ||
d54853ef MS |
532 | /* |
533 | * Two sorts of ETR machine checks. The architecture reads: | |
534 | * "When a machine-check niterruption occurs and if a switch-to-local or | |
535 | * ETR-sync-check interrupt request is pending but disabled, this pending | |
536 | * disabled interruption request is indicated and is cleared". | |
537 | * Which means that we can get etr_switch_to_local events from the machine | |
538 | * check handler although the interruption condition is disabled. Lovely.. | |
539 | */ | |
540 | ||
541 | /* | |
542 | * Switch to local machine check. This is called when the last usable | |
543 | * ETR port goes inactive. After switch to local the clock is not in sync. | |
544 | */ | |
29b0a825 | 545 | int etr_switch_to_local(void) |
d54853ef MS |
546 | { |
547 | if (!etr_eacr.sl) | |
29b0a825 | 548 | return 0; |
8283cb43 | 549 | disable_sync_clock(NULL); |
33fea794 MS |
550 | if (!test_and_set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) { |
551 | etr_eacr.es = etr_eacr.sl = 0; | |
552 | etr_setr(&etr_eacr); | |
29b0a825 | 553 | return 1; |
33fea794 | 554 | } |
29b0a825 | 555 | return 0; |
d54853ef MS |
556 | } |
557 | ||
558 | /* | |
559 | * ETR sync check machine check. This is called when the ETR OTE and the | |
560 | * local clock OTE are farther apart than the ETR sync check tolerance. | |
561 | * After a ETR sync check the clock is not in sync. The machine check | |
562 | * is broadcasted to all cpus at the same time. | |
563 | */ | |
29b0a825 | 564 | int etr_sync_check(void) |
d54853ef MS |
565 | { |
566 | if (!etr_eacr.es) | |
29b0a825 | 567 | return 0; |
8283cb43 | 568 | disable_sync_clock(NULL); |
33fea794 MS |
569 | if (!test_and_set_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) { |
570 | etr_eacr.es = 0; | |
571 | etr_setr(&etr_eacr); | |
29b0a825 | 572 | return 1; |
33fea794 | 573 | } |
29b0a825 HC |
574 | return 0; |
575 | } | |
576 | ||
577 | void etr_queue_work(void) | |
578 | { | |
579 | queue_work(time_sync_wq, &etr_work); | |
d54853ef MS |
580 | } |
581 | ||
582 | /* | |
d2fec595 | 583 | * ETR timing alert. There are two causes: |
d54853ef MS |
584 | * 1) port state change, check the usability of the port |
585 | * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the | |
586 | * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) | |
587 | * or ETR-data word 4 (edf4) has changed. | |
588 | */ | |
d2fec595 | 589 | static void etr_timing_alert(struct etr_irq_parm *intparm) |
d54853ef | 590 | { |
d54853ef MS |
591 | if (intparm->pc0) |
592 | /* ETR port 0 state change. */ | |
593 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
594 | if (intparm->pc1) | |
595 | /* ETR port 1 state change. */ | |
596 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
597 | if (intparm->eai) | |
598 | /* | |
599 | * ETR port alert on either port 0, 1 or both. | |
600 | * Both ports are not up-to-date now. | |
601 | */ | |
602 | set_bit(ETR_EVENT_PORT_ALERT, &etr_events); | |
750887de | 603 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
604 | } |
605 | ||
606 | static void etr_timeout(unsigned long dummy) | |
607 | { | |
608 | set_bit(ETR_EVENT_UPDATE, &etr_events); | |
750887de | 609 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
610 | } |
611 | ||
612 | /* | |
613 | * Check if the etr mode is pss. | |
614 | */ | |
615 | static inline int etr_mode_is_pps(struct etr_eacr eacr) | |
616 | { | |
617 | return eacr.es && !eacr.sl; | |
618 | } | |
619 | ||
620 | /* | |
621 | * Check if the etr mode is etr. | |
622 | */ | |
623 | static inline int etr_mode_is_etr(struct etr_eacr eacr) | |
624 | { | |
625 | return eacr.es && eacr.sl; | |
626 | } | |
627 | ||
628 | /* | |
629 | * Check if the port can be used for TOD synchronization. | |
630 | * For PPS mode the port has to receive OTEs. For ETR mode | |
631 | * the port has to receive OTEs, the ETR stepping bit has to | |
632 | * be zero and the validity bits for data frame 1, 2, and 3 | |
633 | * have to be 1. | |
634 | */ | |
635 | static int etr_port_valid(struct etr_aib *aib, int port) | |
636 | { | |
637 | unsigned int psc; | |
638 | ||
639 | /* Check that this port is receiving OTEs. */ | |
640 | if (aib->tsp == 0) | |
641 | return 0; | |
642 | ||
643 | psc = port ? aib->esw.psc1 : aib->esw.psc0; | |
644 | if (psc == etr_lpsc_pps_mode) | |
645 | return 1; | |
646 | if (psc == etr_lpsc_operational_step) | |
647 | return !aib->esw.y && aib->slsw.v1 && | |
648 | aib->slsw.v2 && aib->slsw.v3; | |
649 | return 0; | |
650 | } | |
651 | ||
652 | /* | |
653 | * Check if two ports are on the same network. | |
654 | */ | |
655 | static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) | |
656 | { | |
657 | // FIXME: any other fields we have to compare? | |
658 | return aib1->edf1.net_id == aib2->edf1.net_id; | |
659 | } | |
660 | ||
661 | /* | |
662 | * Wrapper for etr_stei that converts physical port states | |
663 | * to logical port states to be consistent with the output | |
664 | * of stetr (see etr_psc vs. etr_lpsc). | |
665 | */ | |
666 | static void etr_steai_cv(struct etr_aib *aib, unsigned int func) | |
667 | { | |
668 | BUG_ON(etr_steai(aib, func) != 0); | |
669 | /* Convert port state to logical port state. */ | |
670 | if (aib->esw.psc0 == 1) | |
671 | aib->esw.psc0 = 2; | |
672 | else if (aib->esw.psc0 == 0 && aib->esw.p == 0) | |
673 | aib->esw.psc0 = 1; | |
674 | if (aib->esw.psc1 == 1) | |
675 | aib->esw.psc1 = 2; | |
676 | else if (aib->esw.psc1 == 0 && aib->esw.p == 1) | |
677 | aib->esw.psc1 = 1; | |
678 | } | |
679 | ||
680 | /* | |
681 | * Check if the aib a2 is still connected to the same attachment as | |
682 | * aib a1, the etv values differ by one and a2 is valid. | |
683 | */ | |
684 | static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) | |
685 | { | |
686 | int state_a1, state_a2; | |
687 | ||
688 | /* Paranoia check: e0/e1 should better be the same. */ | |
689 | if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || | |
690 | a1->esw.eacr.e1 != a2->esw.eacr.e1) | |
691 | return 0; | |
692 | ||
693 | /* Still connected to the same etr ? */ | |
694 | state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; | |
695 | state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; | |
696 | if (state_a1 == etr_lpsc_operational_step) { | |
697 | if (state_a2 != etr_lpsc_operational_step || | |
698 | a1->edf1.net_id != a2->edf1.net_id || | |
699 | a1->edf1.etr_id != a2->edf1.etr_id || | |
700 | a1->edf1.etr_pn != a2->edf1.etr_pn) | |
701 | return 0; | |
702 | } else if (state_a2 != etr_lpsc_pps_mode) | |
703 | return 0; | |
704 | ||
705 | /* The ETV value of a2 needs to be ETV of a1 + 1. */ | |
706 | if (a1->edf2.etv + 1 != a2->edf2.etv) | |
707 | return 0; | |
708 | ||
709 | if (!etr_port_valid(a2, p)) | |
710 | return 0; | |
711 | ||
712 | return 1; | |
713 | } | |
714 | ||
d2fec595 | 715 | struct clock_sync_data { |
750887de | 716 | atomic_t cpus; |
5a62b192 HC |
717 | int in_sync; |
718 | unsigned long long fixup_cc; | |
750887de HC |
719 | int etr_port; |
720 | struct etr_aib *etr_aib; | |
d2fec595 | 721 | }; |
5a62b192 | 722 | |
750887de | 723 | static void clock_sync_cpu(struct clock_sync_data *sync) |
d54853ef | 724 | { |
750887de | 725 | atomic_dec(&sync->cpus); |
d2fec595 | 726 | enable_sync_clock(); |
d54853ef MS |
727 | /* |
728 | * This looks like a busy wait loop but it isn't. etr_sync_cpus | |
729 | * is called on all other cpus while the TOD clocks is stopped. | |
730 | * __udelay will stop the cpu on an enabled wait psw until the | |
731 | * TOD is running again. | |
732 | */ | |
d2fec595 | 733 | while (sync->in_sync == 0) { |
d54853ef | 734 | __udelay(1); |
6c732de2 HC |
735 | /* |
736 | * A different cpu changes *in_sync. Therefore use | |
737 | * barrier() to force memory access. | |
738 | */ | |
739 | barrier(); | |
740 | } | |
d2fec595 | 741 | if (sync->in_sync != 1) |
d54853ef | 742 | /* Didn't work. Clear per-cpu in sync bit again. */ |
d2fec595 | 743 | disable_sync_clock(NULL); |
d54853ef MS |
744 | /* |
745 | * This round of TOD syncing is done. Set the clock comparator | |
746 | * to the next tick and let the processor continue. | |
747 | */ | |
d2fec595 | 748 | fixup_clock_comparator(sync->fixup_cc); |
d54853ef MS |
749 | } |
750 | ||
d54853ef | 751 | /* |
25985edc | 752 | * Sync the TOD clock using the port referred to by aibp. This port |
d54853ef MS |
753 | * has to be enabled and the other port has to be disabled. The |
754 | * last eacr update has to be more than 1.6 seconds in the past. | |
755 | */ | |
750887de | 756 | static int etr_sync_clock(void *data) |
d54853ef | 757 | { |
750887de | 758 | static int first; |
fdf03650 | 759 | unsigned long long clock, old_clock, clock_delta, delay, delta; |
750887de HC |
760 | struct clock_sync_data *etr_sync; |
761 | struct etr_aib *sync_port, *aib; | |
762 | int port; | |
d54853ef MS |
763 | int rc; |
764 | ||
750887de | 765 | etr_sync = data; |
d54853ef | 766 | |
750887de HC |
767 | if (xchg(&first, 1) == 1) { |
768 | /* Slave */ | |
769 | clock_sync_cpu(etr_sync); | |
770 | return 0; | |
771 | } | |
772 | ||
773 | /* Wait until all other cpus entered the sync function. */ | |
774 | while (atomic_read(&etr_sync->cpus) != 0) | |
775 | cpu_relax(); | |
776 | ||
777 | port = etr_sync->etr_port; | |
778 | aib = etr_sync->etr_aib; | |
779 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
d2fec595 | 780 | enable_sync_clock(); |
d54853ef MS |
781 | |
782 | /* Set clock to next OTE. */ | |
783 | __ctl_set_bit(14, 21); | |
784 | __ctl_set_bit(0, 29); | |
785 | clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; | |
1aae0560 HC |
786 | old_clock = get_tod_clock(); |
787 | if (set_tod_clock(clock) == 0) { | |
d54853ef MS |
788 | __udelay(1); /* Wait for the clock to start. */ |
789 | __ctl_clear_bit(0, 29); | |
790 | __ctl_clear_bit(14, 21); | |
791 | etr_stetr(aib); | |
792 | /* Adjust Linux timing variables. */ | |
793 | delay = (unsigned long long) | |
794 | (aib->edf2.etv - sync_port->edf2.etv) << 32; | |
d2fec595 | 795 | delta = adjust_time(old_clock, clock, delay); |
fdf03650 FZ |
796 | clock_delta = clock - old_clock; |
797 | atomic_notifier_call_chain(&s390_epoch_delta_notifier, 0, | |
798 | &clock_delta); | |
750887de | 799 | etr_sync->fixup_cc = delta; |
5a62b192 | 800 | fixup_clock_comparator(delta); |
d54853ef MS |
801 | /* Verify that the clock is properly set. */ |
802 | if (!etr_aib_follows(sync_port, aib, port)) { | |
803 | /* Didn't work. */ | |
d2fec595 | 804 | disable_sync_clock(NULL); |
750887de | 805 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
806 | rc = -EAGAIN; |
807 | } else { | |
750887de | 808 | etr_sync->in_sync = 1; |
d54853ef MS |
809 | rc = 0; |
810 | } | |
811 | } else { | |
812 | /* Could not set the clock ?!? */ | |
813 | __ctl_clear_bit(0, 29); | |
814 | __ctl_clear_bit(14, 21); | |
d2fec595 | 815 | disable_sync_clock(NULL); |
750887de | 816 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
817 | rc = -EAGAIN; |
818 | } | |
750887de HC |
819 | xchg(&first, 0); |
820 | return rc; | |
821 | } | |
822 | ||
823 | static int etr_sync_clock_stop(struct etr_aib *aib, int port) | |
824 | { | |
825 | struct clock_sync_data etr_sync; | |
826 | struct etr_aib *sync_port; | |
827 | int follows; | |
828 | int rc; | |
829 | ||
830 | /* Check if the current aib is adjacent to the sync port aib. */ | |
831 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
832 | follows = etr_aib_follows(sync_port, aib, port); | |
833 | memcpy(sync_port, aib, sizeof(*aib)); | |
834 | if (!follows) | |
835 | return -EAGAIN; | |
836 | memset(&etr_sync, 0, sizeof(etr_sync)); | |
837 | etr_sync.etr_aib = aib; | |
838 | etr_sync.etr_port = port; | |
839 | get_online_cpus(); | |
840 | atomic_set(&etr_sync.cpus, num_online_cpus() - 1); | |
0f1959f5 | 841 | rc = stop_machine(etr_sync_clock, &etr_sync, cpu_online_mask); |
750887de | 842 | put_online_cpus(); |
d54853ef MS |
843 | return rc; |
844 | } | |
845 | ||
846 | /* | |
847 | * Handle the immediate effects of the different events. | |
848 | * The port change event is used for online/offline changes. | |
849 | */ | |
850 | static struct etr_eacr etr_handle_events(struct etr_eacr eacr) | |
851 | { | |
852 | if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) | |
853 | eacr.es = 0; | |
854 | if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) | |
855 | eacr.es = eacr.sl = 0; | |
856 | if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) | |
857 | etr_port0_uptodate = etr_port1_uptodate = 0; | |
858 | ||
859 | if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { | |
860 | if (eacr.e0) | |
861 | /* | |
862 | * Port change of an enabled port. We have to | |
863 | * assume that this can have caused an stepping | |
864 | * port switch. | |
865 | */ | |
1aae0560 | 866 | etr_tolec = get_tod_clock(); |
d54853ef MS |
867 | eacr.p0 = etr_port0_online; |
868 | if (!eacr.p0) | |
869 | eacr.e0 = 0; | |
870 | etr_port0_uptodate = 0; | |
871 | } | |
872 | if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { | |
873 | if (eacr.e1) | |
874 | /* | |
875 | * Port change of an enabled port. We have to | |
876 | * assume that this can have caused an stepping | |
877 | * port switch. | |
878 | */ | |
1aae0560 | 879 | etr_tolec = get_tod_clock(); |
d54853ef MS |
880 | eacr.p1 = etr_port1_online; |
881 | if (!eacr.p1) | |
882 | eacr.e1 = 0; | |
883 | etr_port1_uptodate = 0; | |
884 | } | |
885 | clear_bit(ETR_EVENT_UPDATE, &etr_events); | |
886 | return eacr; | |
887 | } | |
888 | ||
889 | /* | |
890 | * Set up a timer that expires after the etr_tolec + 1.6 seconds if | |
891 | * one of the ports needs an update. | |
892 | */ | |
893 | static void etr_set_tolec_timeout(unsigned long long now) | |
894 | { | |
895 | unsigned long micros; | |
896 | ||
897 | if ((!etr_eacr.p0 || etr_port0_uptodate) && | |
898 | (!etr_eacr.p1 || etr_port1_uptodate)) | |
899 | return; | |
900 | micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; | |
901 | micros = (micros > 1600000) ? 0 : 1600000 - micros; | |
902 | mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); | |
903 | } | |
904 | ||
905 | /* | |
906 | * Set up a time that expires after 1/2 second. | |
907 | */ | |
908 | static void etr_set_sync_timeout(void) | |
909 | { | |
910 | mod_timer(&etr_timer, jiffies + HZ/2); | |
911 | } | |
912 | ||
913 | /* | |
914 | * Update the aib information for one or both ports. | |
915 | */ | |
916 | static struct etr_eacr etr_handle_update(struct etr_aib *aib, | |
917 | struct etr_eacr eacr) | |
918 | { | |
919 | /* With both ports disabled the aib information is useless. */ | |
920 | if (!eacr.e0 && !eacr.e1) | |
921 | return eacr; | |
922 | ||
ecdcc023 | 923 | /* Update port0 or port1 with aib stored in etr_work_fn. */ |
d54853ef MS |
924 | if (aib->esw.q == 0) { |
925 | /* Information for port 0 stored. */ | |
926 | if (eacr.p0 && !etr_port0_uptodate) { | |
927 | etr_port0 = *aib; | |
928 | if (etr_port0_online) | |
929 | etr_port0_uptodate = 1; | |
930 | } | |
931 | } else { | |
932 | /* Information for port 1 stored. */ | |
933 | if (eacr.p1 && !etr_port1_uptodate) { | |
934 | etr_port1 = *aib; | |
935 | if (etr_port0_online) | |
936 | etr_port1_uptodate = 1; | |
937 | } | |
938 | } | |
939 | ||
940 | /* | |
941 | * Do not try to get the alternate port aib if the clock | |
942 | * is not in sync yet. | |
943 | */ | |
33fea794 | 944 | if (!eacr.es || !check_sync_clock()) |
d54853ef MS |
945 | return eacr; |
946 | ||
947 | /* | |
948 | * If steai is available we can get the information about | |
949 | * the other port immediately. If only stetr is available the | |
950 | * data-port bit toggle has to be used. | |
951 | */ | |
d2fec595 | 952 | if (etr_steai_available) { |
d54853ef MS |
953 | if (eacr.p0 && !etr_port0_uptodate) { |
954 | etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); | |
955 | etr_port0_uptodate = 1; | |
956 | } | |
957 | if (eacr.p1 && !etr_port1_uptodate) { | |
958 | etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); | |
959 | etr_port1_uptodate = 1; | |
960 | } | |
961 | } else { | |
962 | /* | |
963 | * One port was updated above, if the other | |
964 | * port is not uptodate toggle dp bit. | |
965 | */ | |
966 | if ((eacr.p0 && !etr_port0_uptodate) || | |
967 | (eacr.p1 && !etr_port1_uptodate)) | |
968 | eacr.dp ^= 1; | |
969 | else | |
970 | eacr.dp = 0; | |
971 | } | |
972 | return eacr; | |
973 | } | |
974 | ||
975 | /* | |
976 | * Write new etr control register if it differs from the current one. | |
977 | * Return 1 if etr_tolec has been updated as well. | |
978 | */ | |
979 | static void etr_update_eacr(struct etr_eacr eacr) | |
980 | { | |
981 | int dp_changed; | |
982 | ||
983 | if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) | |
984 | /* No change, return. */ | |
985 | return; | |
986 | /* | |
987 | * The disable of an active port of the change of the data port | |
988 | * bit can/will cause a change in the data port. | |
989 | */ | |
990 | dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || | |
991 | (etr_eacr.dp ^ eacr.dp) != 0; | |
992 | etr_eacr = eacr; | |
993 | etr_setr(&etr_eacr); | |
994 | if (dp_changed) | |
1aae0560 | 995 | etr_tolec = get_tod_clock(); |
d54853ef MS |
996 | } |
997 | ||
998 | /* | |
750887de | 999 | * ETR work. In this function you'll find the main logic. In |
d54853ef MS |
1000 | * particular this is the only function that calls etr_update_eacr(), |
1001 | * it "controls" the etr control register. | |
1002 | */ | |
ecdcc023 | 1003 | static void etr_work_fn(struct work_struct *work) |
d54853ef MS |
1004 | { |
1005 | unsigned long long now; | |
1006 | struct etr_eacr eacr; | |
1007 | struct etr_aib aib; | |
1008 | int sync_port; | |
1009 | ||
0b3016b7 MS |
1010 | /* prevent multiple execution. */ |
1011 | mutex_lock(&etr_work_mutex); | |
1012 | ||
d54853ef MS |
1013 | /* Create working copy of etr_eacr. */ |
1014 | eacr = etr_eacr; | |
1015 | ||
1016 | /* Check for the different events and their immediate effects. */ | |
1017 | eacr = etr_handle_events(eacr); | |
1018 | ||
1019 | /* Check if ETR is supposed to be active. */ | |
1020 | eacr.ea = eacr.p0 || eacr.p1; | |
1021 | if (!eacr.ea) { | |
1022 | /* Both ports offline. Reset everything. */ | |
1023 | eacr.dp = eacr.es = eacr.sl = 0; | |
1a781a77 | 1024 | on_each_cpu(disable_sync_clock, NULL, 1); |
d54853ef MS |
1025 | del_timer_sync(&etr_timer); |
1026 | etr_update_eacr(eacr); | |
0b3016b7 | 1027 | goto out_unlock; |
d54853ef MS |
1028 | } |
1029 | ||
1030 | /* Store aib to get the current ETR status word. */ | |
1031 | BUG_ON(etr_stetr(&aib) != 0); | |
1032 | etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ | |
1aae0560 | 1033 | now = get_tod_clock(); |
d54853ef MS |
1034 | |
1035 | /* | |
1036 | * Update the port information if the last stepping port change | |
1037 | * or data port change is older than 1.6 seconds. | |
1038 | */ | |
1039 | if (now >= etr_tolec + (1600000 << 12)) | |
1040 | eacr = etr_handle_update(&aib, eacr); | |
1041 | ||
1042 | /* | |
25985edc | 1043 | * Select ports to enable. The preferred synchronization mode is PPS. |
d54853ef MS |
1044 | * If a port can be enabled depends on a number of things: |
1045 | * 1) The port needs to be online and uptodate. A port is not | |
1046 | * disabled just because it is not uptodate, but it is only | |
1047 | * enabled if it is uptodate. | |
1048 | * 2) The port needs to have the same mode (pps / etr). | |
1049 | * 3) The port needs to be usable -> etr_port_valid() == 1 | |
1050 | * 4) To enable the second port the clock needs to be in sync. | |
1051 | * 5) If both ports are useable and are ETR ports, the network id | |
1052 | * has to be the same. | |
1053 | * The eacr.sl bit is used to indicate etr mode vs. pps mode. | |
1054 | */ | |
1055 | if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { | |
1056 | eacr.sl = 0; | |
1057 | eacr.e0 = 1; | |
1058 | if (!etr_mode_is_pps(etr_eacr)) | |
1059 | eacr.es = 0; | |
1060 | if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) | |
1061 | eacr.e1 = 0; | |
1062 | // FIXME: uptodate checks ? | |
1063 | else if (etr_port0_uptodate && etr_port1_uptodate) | |
1064 | eacr.e1 = 1; | |
1065 | sync_port = (etr_port0_uptodate && | |
1066 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1067 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { |
1068 | eacr.sl = 0; | |
1069 | eacr.e0 = 0; | |
1070 | eacr.e1 = 1; | |
1071 | if (!etr_mode_is_pps(etr_eacr)) | |
1072 | eacr.es = 0; | |
1073 | sync_port = (etr_port1_uptodate && | |
1074 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1075 | } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { |
1076 | eacr.sl = 1; | |
1077 | eacr.e0 = 1; | |
1078 | if (!etr_mode_is_etr(etr_eacr)) | |
1079 | eacr.es = 0; | |
1080 | if (!eacr.es || !eacr.p1 || | |
1081 | aib.esw.psc1 != etr_lpsc_operational_alt) | |
1082 | eacr.e1 = 0; | |
1083 | else if (etr_port0_uptodate && etr_port1_uptodate && | |
1084 | etr_compare_network(&etr_port0, &etr_port1)) | |
1085 | eacr.e1 = 1; | |
1086 | sync_port = (etr_port0_uptodate && | |
1087 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1088 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { |
1089 | eacr.sl = 1; | |
1090 | eacr.e0 = 0; | |
1091 | eacr.e1 = 1; | |
1092 | if (!etr_mode_is_etr(etr_eacr)) | |
1093 | eacr.es = 0; | |
1094 | sync_port = (etr_port1_uptodate && | |
1095 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1096 | } else { |
1097 | /* Both ports not usable. */ | |
1098 | eacr.es = eacr.sl = 0; | |
1099 | sync_port = -1; | |
d54853ef MS |
1100 | } |
1101 | ||
1102 | /* | |
1103 | * If the clock is in sync just update the eacr and return. | |
1104 | * If there is no valid sync port wait for a port update. | |
1105 | */ | |
33fea794 | 1106 | if ((eacr.es && check_sync_clock()) || sync_port < 0) { |
d54853ef MS |
1107 | etr_update_eacr(eacr); |
1108 | etr_set_tolec_timeout(now); | |
0b3016b7 | 1109 | goto out_unlock; |
d54853ef MS |
1110 | } |
1111 | ||
1112 | /* | |
1113 | * Prepare control register for clock syncing | |
1114 | * (reset data port bit, set sync check control. | |
1115 | */ | |
1116 | eacr.dp = 0; | |
1117 | eacr.es = 1; | |
1118 | ||
1119 | /* | |
1120 | * Update eacr and try to synchronize the clock. If the update | |
1121 | * of eacr caused a stepping port switch (or if we have to | |
25985edc | 1122 | * assume that a stepping port switch has occurred) or the |
d54853ef MS |
1123 | * clock syncing failed, reset the sync check control bit |
1124 | * and set up a timer to try again after 0.5 seconds | |
1125 | */ | |
1126 | etr_update_eacr(eacr); | |
1127 | if (now < etr_tolec + (1600000 << 12) || | |
750887de | 1128 | etr_sync_clock_stop(&aib, sync_port) != 0) { |
d54853ef MS |
1129 | /* Sync failed. Try again in 1/2 second. */ |
1130 | eacr.es = 0; | |
1131 | etr_update_eacr(eacr); | |
1132 | etr_set_sync_timeout(); | |
1133 | } else | |
1134 | etr_set_tolec_timeout(now); | |
0b3016b7 MS |
1135 | out_unlock: |
1136 | mutex_unlock(&etr_work_mutex); | |
d54853ef MS |
1137 | } |
1138 | ||
1139 | /* | |
1140 | * Sysfs interface functions | |
1141 | */ | |
3fbacffb KS |
1142 | static struct bus_type etr_subsys = { |
1143 | .name = "etr", | |
1144 | .dev_name = "etr", | |
d54853ef MS |
1145 | }; |
1146 | ||
3fbacffb | 1147 | static struct device etr_port0_dev = { |
d54853ef | 1148 | .id = 0, |
3fbacffb | 1149 | .bus = &etr_subsys, |
d54853ef MS |
1150 | }; |
1151 | ||
3fbacffb | 1152 | static struct device etr_port1_dev = { |
d54853ef | 1153 | .id = 1, |
3fbacffb | 1154 | .bus = &etr_subsys, |
d54853ef MS |
1155 | }; |
1156 | ||
1157 | /* | |
3fbacffb | 1158 | * ETR subsys attributes |
d54853ef | 1159 | */ |
3fbacffb KS |
1160 | static ssize_t etr_stepping_port_show(struct device *dev, |
1161 | struct device_attribute *attr, | |
c9be0a36 | 1162 | char *buf) |
d54853ef MS |
1163 | { |
1164 | return sprintf(buf, "%i\n", etr_port0.esw.p); | |
1165 | } | |
1166 | ||
3fbacffb | 1167 | static DEVICE_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); |
d54853ef | 1168 | |
3fbacffb KS |
1169 | static ssize_t etr_stepping_mode_show(struct device *dev, |
1170 | struct device_attribute *attr, | |
c9be0a36 | 1171 | char *buf) |
d54853ef MS |
1172 | { |
1173 | char *mode_str; | |
1174 | ||
1175 | if (etr_mode_is_pps(etr_eacr)) | |
1176 | mode_str = "pps"; | |
1177 | else if (etr_mode_is_etr(etr_eacr)) | |
1178 | mode_str = "etr"; | |
1179 | else | |
1180 | mode_str = "local"; | |
1181 | return sprintf(buf, "%s\n", mode_str); | |
1182 | } | |
1183 | ||
3fbacffb | 1184 | static DEVICE_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); |
d54853ef MS |
1185 | |
1186 | /* | |
1187 | * ETR port attributes | |
1188 | */ | |
3fbacffb | 1189 | static inline struct etr_aib *etr_aib_from_dev(struct device *dev) |
d54853ef MS |
1190 | { |
1191 | if (dev == &etr_port0_dev) | |
1192 | return etr_port0_online ? &etr_port0 : NULL; | |
1193 | else | |
1194 | return etr_port1_online ? &etr_port1 : NULL; | |
1195 | } | |
1196 | ||
3fbacffb KS |
1197 | static ssize_t etr_online_show(struct device *dev, |
1198 | struct device_attribute *attr, | |
4a0b2b4d | 1199 | char *buf) |
d54853ef MS |
1200 | { |
1201 | unsigned int online; | |
1202 | ||
1203 | online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; | |
1204 | return sprintf(buf, "%i\n", online); | |
1205 | } | |
1206 | ||
3fbacffb KS |
1207 | static ssize_t etr_online_store(struct device *dev, |
1208 | struct device_attribute *attr, | |
4a0b2b4d | 1209 | const char *buf, size_t count) |
d54853ef MS |
1210 | { |
1211 | unsigned int value; | |
1212 | ||
1213 | value = simple_strtoul(buf, NULL, 0); | |
1214 | if (value != 0 && value != 1) | |
1215 | return -EINVAL; | |
d2fec595 MS |
1216 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
1217 | return -EOPNOTSUPP; | |
8283cb43 | 1218 | mutex_lock(&clock_sync_mutex); |
d54853ef MS |
1219 | if (dev == &etr_port0_dev) { |
1220 | if (etr_port0_online == value) | |
8283cb43 | 1221 | goto out; /* Nothing to do. */ |
d54853ef | 1222 | etr_port0_online = value; |
8283cb43 MS |
1223 | if (etr_port0_online && etr_port1_online) |
1224 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
1225 | else | |
1226 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d54853ef | 1227 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); |
750887de | 1228 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
1229 | } else { |
1230 | if (etr_port1_online == value) | |
8283cb43 | 1231 | goto out; /* Nothing to do. */ |
d54853ef | 1232 | etr_port1_online = value; |
8283cb43 MS |
1233 | if (etr_port0_online && etr_port1_online) |
1234 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
1235 | else | |
1236 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d54853ef | 1237 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); |
750887de | 1238 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 1239 | } |
8283cb43 MS |
1240 | out: |
1241 | mutex_unlock(&clock_sync_mutex); | |
d54853ef MS |
1242 | return count; |
1243 | } | |
1244 | ||
3fbacffb | 1245 | static DEVICE_ATTR(online, 0600, etr_online_show, etr_online_store); |
d54853ef | 1246 | |
3fbacffb KS |
1247 | static ssize_t etr_stepping_control_show(struct device *dev, |
1248 | struct device_attribute *attr, | |
4a0b2b4d | 1249 | char *buf) |
d54853ef MS |
1250 | { |
1251 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1252 | etr_eacr.e0 : etr_eacr.e1); | |
1253 | } | |
1254 | ||
3fbacffb | 1255 | static DEVICE_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); |
d54853ef | 1256 | |
3fbacffb KS |
1257 | static ssize_t etr_mode_code_show(struct device *dev, |
1258 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1259 | { |
1260 | if (!etr_port0_online && !etr_port1_online) | |
1261 | /* Status word is not uptodate if both ports are offline. */ | |
1262 | return -ENODATA; | |
1263 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1264 | etr_port0.esw.psc0 : etr_port0.esw.psc1); | |
1265 | } | |
1266 | ||
3fbacffb | 1267 | static DEVICE_ATTR(state_code, 0400, etr_mode_code_show, NULL); |
d54853ef | 1268 | |
3fbacffb KS |
1269 | static ssize_t etr_untuned_show(struct device *dev, |
1270 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1271 | { |
1272 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1273 | ||
1274 | if (!aib || !aib->slsw.v1) | |
1275 | return -ENODATA; | |
1276 | return sprintf(buf, "%i\n", aib->edf1.u); | |
1277 | } | |
1278 | ||
3fbacffb | 1279 | static DEVICE_ATTR(untuned, 0400, etr_untuned_show, NULL); |
d54853ef | 1280 | |
3fbacffb KS |
1281 | static ssize_t etr_network_id_show(struct device *dev, |
1282 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1283 | { |
1284 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1285 | ||
1286 | if (!aib || !aib->slsw.v1) | |
1287 | return -ENODATA; | |
1288 | return sprintf(buf, "%i\n", aib->edf1.net_id); | |
1289 | } | |
1290 | ||
3fbacffb | 1291 | static DEVICE_ATTR(network, 0400, etr_network_id_show, NULL); |
d54853ef | 1292 | |
3fbacffb KS |
1293 | static ssize_t etr_id_show(struct device *dev, |
1294 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1295 | { |
1296 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1297 | ||
1298 | if (!aib || !aib->slsw.v1) | |
1299 | return -ENODATA; | |
1300 | return sprintf(buf, "%i\n", aib->edf1.etr_id); | |
1301 | } | |
1302 | ||
3fbacffb | 1303 | static DEVICE_ATTR(id, 0400, etr_id_show, NULL); |
d54853ef | 1304 | |
3fbacffb KS |
1305 | static ssize_t etr_port_number_show(struct device *dev, |
1306 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1307 | { |
1308 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1309 | ||
1310 | if (!aib || !aib->slsw.v1) | |
1311 | return -ENODATA; | |
1312 | return sprintf(buf, "%i\n", aib->edf1.etr_pn); | |
1313 | } | |
1314 | ||
3fbacffb | 1315 | static DEVICE_ATTR(port, 0400, etr_port_number_show, NULL); |
d54853ef | 1316 | |
3fbacffb KS |
1317 | static ssize_t etr_coupled_show(struct device *dev, |
1318 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1319 | { |
1320 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1321 | ||
1322 | if (!aib || !aib->slsw.v3) | |
1323 | return -ENODATA; | |
1324 | return sprintf(buf, "%i\n", aib->edf3.c); | |
1325 | } | |
1326 | ||
3fbacffb | 1327 | static DEVICE_ATTR(coupled, 0400, etr_coupled_show, NULL); |
d54853ef | 1328 | |
3fbacffb KS |
1329 | static ssize_t etr_local_time_show(struct device *dev, |
1330 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1331 | { |
1332 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1333 | ||
1334 | if (!aib || !aib->slsw.v3) | |
1335 | return -ENODATA; | |
1336 | return sprintf(buf, "%i\n", aib->edf3.blto); | |
1337 | } | |
1338 | ||
3fbacffb | 1339 | static DEVICE_ATTR(local_time, 0400, etr_local_time_show, NULL); |
d54853ef | 1340 | |
3fbacffb KS |
1341 | static ssize_t etr_utc_offset_show(struct device *dev, |
1342 | struct device_attribute *attr, char *buf) | |
d54853ef MS |
1343 | { |
1344 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1345 | ||
1346 | if (!aib || !aib->slsw.v3) | |
1347 | return -ENODATA; | |
1348 | return sprintf(buf, "%i\n", aib->edf3.buo); | |
1349 | } | |
1350 | ||
3fbacffb | 1351 | static DEVICE_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); |
d54853ef | 1352 | |
3fbacffb KS |
1353 | static struct device_attribute *etr_port_attributes[] = { |
1354 | &dev_attr_online, | |
1355 | &dev_attr_stepping_control, | |
1356 | &dev_attr_state_code, | |
1357 | &dev_attr_untuned, | |
1358 | &dev_attr_network, | |
1359 | &dev_attr_id, | |
1360 | &dev_attr_port, | |
1361 | &dev_attr_coupled, | |
1362 | &dev_attr_local_time, | |
1363 | &dev_attr_utc_offset, | |
d54853ef MS |
1364 | NULL |
1365 | }; | |
1366 | ||
3fbacffb | 1367 | static int __init etr_register_port(struct device *dev) |
d54853ef | 1368 | { |
3fbacffb | 1369 | struct device_attribute **attr; |
d54853ef MS |
1370 | int rc; |
1371 | ||
3fbacffb | 1372 | rc = device_register(dev); |
d54853ef MS |
1373 | if (rc) |
1374 | goto out; | |
1375 | for (attr = etr_port_attributes; *attr; attr++) { | |
3fbacffb | 1376 | rc = device_create_file(dev, *attr); |
d54853ef MS |
1377 | if (rc) |
1378 | goto out_unreg; | |
1379 | } | |
1380 | return 0; | |
1381 | out_unreg: | |
1382 | for (; attr >= etr_port_attributes; attr--) | |
3fbacffb KS |
1383 | device_remove_file(dev, *attr); |
1384 | device_unregister(dev); | |
d54853ef MS |
1385 | out: |
1386 | return rc; | |
1387 | } | |
1388 | ||
3fbacffb | 1389 | static void __init etr_unregister_port(struct device *dev) |
d54853ef | 1390 | { |
3fbacffb | 1391 | struct device_attribute **attr; |
d54853ef MS |
1392 | |
1393 | for (attr = etr_port_attributes; *attr; attr++) | |
3fbacffb KS |
1394 | device_remove_file(dev, *attr); |
1395 | device_unregister(dev); | |
d54853ef MS |
1396 | } |
1397 | ||
1398 | static int __init etr_init_sysfs(void) | |
1399 | { | |
1400 | int rc; | |
1401 | ||
3fbacffb | 1402 | rc = subsys_system_register(&etr_subsys, NULL); |
d54853ef MS |
1403 | if (rc) |
1404 | goto out; | |
3fbacffb | 1405 | rc = device_create_file(etr_subsys.dev_root, &dev_attr_stepping_port); |
d54853ef | 1406 | if (rc) |
3fbacffb KS |
1407 | goto out_unreg_subsys; |
1408 | rc = device_create_file(etr_subsys.dev_root, &dev_attr_stepping_mode); | |
d54853ef MS |
1409 | if (rc) |
1410 | goto out_remove_stepping_port; | |
1411 | rc = etr_register_port(&etr_port0_dev); | |
1412 | if (rc) | |
1413 | goto out_remove_stepping_mode; | |
1414 | rc = etr_register_port(&etr_port1_dev); | |
1415 | if (rc) | |
1416 | goto out_remove_port0; | |
1417 | return 0; | |
1418 | ||
1419 | out_remove_port0: | |
1420 | etr_unregister_port(&etr_port0_dev); | |
1421 | out_remove_stepping_mode: | |
3fbacffb | 1422 | device_remove_file(etr_subsys.dev_root, &dev_attr_stepping_mode); |
d54853ef | 1423 | out_remove_stepping_port: |
3fbacffb KS |
1424 | device_remove_file(etr_subsys.dev_root, &dev_attr_stepping_port); |
1425 | out_unreg_subsys: | |
1426 | bus_unregister(&etr_subsys); | |
d54853ef MS |
1427 | out: |
1428 | return rc; | |
1da177e4 LT |
1429 | } |
1430 | ||
d54853ef | 1431 | device_initcall(etr_init_sysfs); |
d2fec595 MS |
1432 | |
1433 | /* | |
1434 | * Server Time Protocol (STP) code. | |
1435 | */ | |
1436 | static int stp_online; | |
1437 | static struct stp_sstpi stp_info; | |
1438 | static void *stp_page; | |
1439 | ||
1440 | static void stp_work_fn(struct work_struct *work); | |
0b3016b7 | 1441 | static DEFINE_MUTEX(stp_work_mutex); |
d2fec595 | 1442 | static DECLARE_WORK(stp_work, stp_work_fn); |
04362301 | 1443 | static struct timer_list stp_timer; |
d2fec595 MS |
1444 | |
1445 | static int __init early_parse_stp(char *p) | |
1446 | { | |
1447 | if (strncmp(p, "off", 3) == 0) | |
1448 | stp_online = 0; | |
1449 | else if (strncmp(p, "on", 2) == 0) | |
1450 | stp_online = 1; | |
1451 | return 0; | |
1452 | } | |
1453 | early_param("stp", early_parse_stp); | |
1454 | ||
1455 | /* | |
1456 | * Reset STP attachment. | |
1457 | */ | |
8f847003 | 1458 | static void __init stp_reset(void) |
d2fec595 MS |
1459 | { |
1460 | int rc; | |
1461 | ||
d7d1104f | 1462 | stp_page = (void *) get_zeroed_page(GFP_ATOMIC); |
d2fec595 | 1463 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); |
4a672cfa | 1464 | if (rc == 0) |
d2fec595 MS |
1465 | set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); |
1466 | else if (stp_online) { | |
feab6501 MS |
1467 | pr_warning("The real or virtual hardware system does " |
1468 | "not provide an STP interface\n"); | |
d7d1104f | 1469 | free_page((unsigned long) stp_page); |
d2fec595 MS |
1470 | stp_page = NULL; |
1471 | stp_online = 0; | |
1472 | } | |
1473 | } | |
1474 | ||
04362301 MS |
1475 | static void stp_timeout(unsigned long dummy) |
1476 | { | |
1477 | queue_work(time_sync_wq, &stp_work); | |
1478 | } | |
1479 | ||
d2fec595 MS |
1480 | static int __init stp_init(void) |
1481 | { | |
750887de HC |
1482 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) |
1483 | return 0; | |
04362301 | 1484 | setup_timer(&stp_timer, stp_timeout, 0UL); |
750887de HC |
1485 | time_init_wq(); |
1486 | if (!stp_online) | |
1487 | return 0; | |
1488 | queue_work(time_sync_wq, &stp_work); | |
d2fec595 MS |
1489 | return 0; |
1490 | } | |
1491 | ||
1492 | arch_initcall(stp_init); | |
1493 | ||
1494 | /* | |
1495 | * STP timing alert. There are three causes: | |
1496 | * 1) timing status change | |
1497 | * 2) link availability change | |
1498 | * 3) time control parameter change | |
1499 | * In all three cases we are only interested in the clock source state. | |
1500 | * If a STP clock source is now available use it. | |
1501 | */ | |
1502 | static void stp_timing_alert(struct stp_irq_parm *intparm) | |
1503 | { | |
1504 | if (intparm->tsc || intparm->lac || intparm->tcpc) | |
750887de | 1505 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1506 | } |
1507 | ||
1508 | /* | |
1509 | * STP sync check machine check. This is called when the timing state | |
1510 | * changes from the synchronized state to the unsynchronized state. | |
1511 | * After a STP sync check the clock is not in sync. The machine check | |
1512 | * is broadcasted to all cpus at the same time. | |
1513 | */ | |
29b0a825 | 1514 | int stp_sync_check(void) |
d2fec595 | 1515 | { |
d2fec595 | 1516 | disable_sync_clock(NULL); |
29b0a825 | 1517 | return 1; |
d2fec595 MS |
1518 | } |
1519 | ||
1520 | /* | |
1521 | * STP island condition machine check. This is called when an attached | |
1522 | * server attempts to communicate over an STP link and the servers | |
1523 | * have matching CTN ids and have a valid stratum-1 configuration | |
1524 | * but the configurations do not match. | |
1525 | */ | |
29b0a825 | 1526 | int stp_island_check(void) |
d2fec595 | 1527 | { |
d2fec595 | 1528 | disable_sync_clock(NULL); |
29b0a825 | 1529 | return 1; |
d2fec595 MS |
1530 | } |
1531 | ||
29b0a825 HC |
1532 | void stp_queue_work(void) |
1533 | { | |
1534 | queue_work(time_sync_wq, &stp_work); | |
1535 | } | |
750887de HC |
1536 | |
1537 | static int stp_sync_clock(void *data) | |
d2fec595 | 1538 | { |
750887de | 1539 | static int first; |
fdf03650 | 1540 | unsigned long long old_clock, delta, new_clock, clock_delta; |
750887de | 1541 | struct clock_sync_data *stp_sync; |
d2fec595 MS |
1542 | int rc; |
1543 | ||
750887de | 1544 | stp_sync = data; |
d2fec595 | 1545 | |
750887de HC |
1546 | if (xchg(&first, 1) == 1) { |
1547 | /* Slave */ | |
1548 | clock_sync_cpu(stp_sync); | |
1549 | return 0; | |
1550 | } | |
d2fec595 | 1551 | |
750887de HC |
1552 | /* Wait until all other cpus entered the sync function. */ |
1553 | while (atomic_read(&stp_sync->cpus) != 0) | |
1554 | cpu_relax(); | |
d2fec595 | 1555 | |
d2fec595 MS |
1556 | enable_sync_clock(); |
1557 | ||
d2fec595 MS |
1558 | rc = 0; |
1559 | if (stp_info.todoff[0] || stp_info.todoff[1] || | |
1560 | stp_info.todoff[2] || stp_info.todoff[3] || | |
1561 | stp_info.tmd != 2) { | |
1aae0560 | 1562 | old_clock = get_tod_clock(); |
d2fec595 MS |
1563 | rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0); |
1564 | if (rc == 0) { | |
fdf03650 FZ |
1565 | new_clock = get_tod_clock(); |
1566 | delta = adjust_time(old_clock, new_clock, 0); | |
1567 | clock_delta = new_clock - old_clock; | |
1568 | atomic_notifier_call_chain(&s390_epoch_delta_notifier, | |
1569 | 0, &clock_delta); | |
d2fec595 MS |
1570 | fixup_clock_comparator(delta); |
1571 | rc = chsc_sstpi(stp_page, &stp_info, | |
1572 | sizeof(struct stp_sstpi)); | |
1573 | if (rc == 0 && stp_info.tmd != 2) | |
1574 | rc = -EAGAIN; | |
1575 | } | |
1576 | } | |
1577 | if (rc) { | |
1578 | disable_sync_clock(NULL); | |
750887de | 1579 | stp_sync->in_sync = -EAGAIN; |
d2fec595 | 1580 | } else |
750887de HC |
1581 | stp_sync->in_sync = 1; |
1582 | xchg(&first, 0); | |
1583 | return 0; | |
1584 | } | |
d2fec595 | 1585 | |
750887de HC |
1586 | /* |
1587 | * STP work. Check for the STP state and take over the clock | |
1588 | * synchronization if the STP clock source is usable. | |
1589 | */ | |
1590 | static void stp_work_fn(struct work_struct *work) | |
1591 | { | |
1592 | struct clock_sync_data stp_sync; | |
1593 | int rc; | |
1594 | ||
0b3016b7 MS |
1595 | /* prevent multiple execution. */ |
1596 | mutex_lock(&stp_work_mutex); | |
1597 | ||
750887de HC |
1598 | if (!stp_online) { |
1599 | chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); | |
04362301 | 1600 | del_timer_sync(&stp_timer); |
0b3016b7 | 1601 | goto out_unlock; |
750887de HC |
1602 | } |
1603 | ||
1604 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0); | |
1605 | if (rc) | |
0b3016b7 | 1606 | goto out_unlock; |
750887de HC |
1607 | |
1608 | rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi)); | |
1609 | if (rc || stp_info.c == 0) | |
0b3016b7 | 1610 | goto out_unlock; |
750887de | 1611 | |
8283cb43 MS |
1612 | /* Skip synchronization if the clock is already in sync. */ |
1613 | if (check_sync_clock()) | |
1614 | goto out_unlock; | |
1615 | ||
750887de HC |
1616 | memset(&stp_sync, 0, sizeof(stp_sync)); |
1617 | get_online_cpus(); | |
1618 | atomic_set(&stp_sync.cpus, num_online_cpus() - 1); | |
0f1959f5 | 1619 | stop_machine(stp_sync_clock, &stp_sync, cpu_online_mask); |
750887de | 1620 | put_online_cpus(); |
0b3016b7 | 1621 | |
04362301 MS |
1622 | if (!check_sync_clock()) |
1623 | /* | |
1624 | * There is a usable clock but the synchonization failed. | |
1625 | * Retry after a second. | |
1626 | */ | |
1627 | mod_timer(&stp_timer, jiffies + HZ); | |
1628 | ||
0b3016b7 MS |
1629 | out_unlock: |
1630 | mutex_unlock(&stp_work_mutex); | |
d2fec595 MS |
1631 | } |
1632 | ||
1633 | /* | |
3fbacffb | 1634 | * STP subsys sysfs interface functions |
d2fec595 | 1635 | */ |
3fbacffb KS |
1636 | static struct bus_type stp_subsys = { |
1637 | .name = "stp", | |
1638 | .dev_name = "stp", | |
d2fec595 MS |
1639 | }; |
1640 | ||
3fbacffb KS |
1641 | static ssize_t stp_ctn_id_show(struct device *dev, |
1642 | struct device_attribute *attr, | |
c9be0a36 | 1643 | char *buf) |
d2fec595 MS |
1644 | { |
1645 | if (!stp_online) | |
1646 | return -ENODATA; | |
1647 | return sprintf(buf, "%016llx\n", | |
1648 | *(unsigned long long *) stp_info.ctnid); | |
1649 | } | |
1650 | ||
3fbacffb | 1651 | static DEVICE_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL); |
d2fec595 | 1652 | |
3fbacffb KS |
1653 | static ssize_t stp_ctn_type_show(struct device *dev, |
1654 | struct device_attribute *attr, | |
c9be0a36 | 1655 | char *buf) |
d2fec595 MS |
1656 | { |
1657 | if (!stp_online) | |
1658 | return -ENODATA; | |
1659 | return sprintf(buf, "%i\n", stp_info.ctn); | |
1660 | } | |
1661 | ||
3fbacffb | 1662 | static DEVICE_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL); |
d2fec595 | 1663 | |
3fbacffb KS |
1664 | static ssize_t stp_dst_offset_show(struct device *dev, |
1665 | struct device_attribute *attr, | |
c9be0a36 | 1666 | char *buf) |
d2fec595 MS |
1667 | { |
1668 | if (!stp_online || !(stp_info.vbits & 0x2000)) | |
1669 | return -ENODATA; | |
1670 | return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto); | |
1671 | } | |
1672 | ||
3fbacffb | 1673 | static DEVICE_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL); |
d2fec595 | 1674 | |
3fbacffb KS |
1675 | static ssize_t stp_leap_seconds_show(struct device *dev, |
1676 | struct device_attribute *attr, | |
c9be0a36 | 1677 | char *buf) |
d2fec595 MS |
1678 | { |
1679 | if (!stp_online || !(stp_info.vbits & 0x8000)) | |
1680 | return -ENODATA; | |
1681 | return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps); | |
1682 | } | |
1683 | ||
3fbacffb | 1684 | static DEVICE_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL); |
d2fec595 | 1685 | |
3fbacffb KS |
1686 | static ssize_t stp_stratum_show(struct device *dev, |
1687 | struct device_attribute *attr, | |
c9be0a36 | 1688 | char *buf) |
d2fec595 MS |
1689 | { |
1690 | if (!stp_online) | |
1691 | return -ENODATA; | |
1692 | return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum); | |
1693 | } | |
1694 | ||
3fbacffb | 1695 | static DEVICE_ATTR(stratum, 0400, stp_stratum_show, NULL); |
d2fec595 | 1696 | |
3fbacffb KS |
1697 | static ssize_t stp_time_offset_show(struct device *dev, |
1698 | struct device_attribute *attr, | |
c9be0a36 | 1699 | char *buf) |
d2fec595 MS |
1700 | { |
1701 | if (!stp_online || !(stp_info.vbits & 0x0800)) | |
1702 | return -ENODATA; | |
1703 | return sprintf(buf, "%i\n", (int) stp_info.tto); | |
1704 | } | |
1705 | ||
3fbacffb | 1706 | static DEVICE_ATTR(time_offset, 0400, stp_time_offset_show, NULL); |
d2fec595 | 1707 | |
3fbacffb KS |
1708 | static ssize_t stp_time_zone_offset_show(struct device *dev, |
1709 | struct device_attribute *attr, | |
c9be0a36 | 1710 | char *buf) |
d2fec595 MS |
1711 | { |
1712 | if (!stp_online || !(stp_info.vbits & 0x4000)) | |
1713 | return -ENODATA; | |
1714 | return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo); | |
1715 | } | |
1716 | ||
3fbacffb | 1717 | static DEVICE_ATTR(time_zone_offset, 0400, |
d2fec595 MS |
1718 | stp_time_zone_offset_show, NULL); |
1719 | ||
3fbacffb KS |
1720 | static ssize_t stp_timing_mode_show(struct device *dev, |
1721 | struct device_attribute *attr, | |
c9be0a36 | 1722 | char *buf) |
d2fec595 MS |
1723 | { |
1724 | if (!stp_online) | |
1725 | return -ENODATA; | |
1726 | return sprintf(buf, "%i\n", stp_info.tmd); | |
1727 | } | |
1728 | ||
3fbacffb | 1729 | static DEVICE_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL); |
d2fec595 | 1730 | |
3fbacffb KS |
1731 | static ssize_t stp_timing_state_show(struct device *dev, |
1732 | struct device_attribute *attr, | |
c9be0a36 | 1733 | char *buf) |
d2fec595 MS |
1734 | { |
1735 | if (!stp_online) | |
1736 | return -ENODATA; | |
1737 | return sprintf(buf, "%i\n", stp_info.tst); | |
1738 | } | |
1739 | ||
3fbacffb | 1740 | static DEVICE_ATTR(timing_state, 0400, stp_timing_state_show, NULL); |
d2fec595 | 1741 | |
3fbacffb KS |
1742 | static ssize_t stp_online_show(struct device *dev, |
1743 | struct device_attribute *attr, | |
c9be0a36 | 1744 | char *buf) |
d2fec595 MS |
1745 | { |
1746 | return sprintf(buf, "%i\n", stp_online); | |
1747 | } | |
1748 | ||
3fbacffb KS |
1749 | static ssize_t stp_online_store(struct device *dev, |
1750 | struct device_attribute *attr, | |
d2fec595 MS |
1751 | const char *buf, size_t count) |
1752 | { | |
1753 | unsigned int value; | |
1754 | ||
1755 | value = simple_strtoul(buf, NULL, 0); | |
1756 | if (value != 0 && value != 1) | |
1757 | return -EINVAL; | |
1758 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
1759 | return -EOPNOTSUPP; | |
8283cb43 | 1760 | mutex_lock(&clock_sync_mutex); |
d2fec595 | 1761 | stp_online = value; |
8283cb43 MS |
1762 | if (stp_online) |
1763 | set_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
1764 | else | |
1765 | clear_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
750887de | 1766 | queue_work(time_sync_wq, &stp_work); |
8283cb43 | 1767 | mutex_unlock(&clock_sync_mutex); |
d2fec595 MS |
1768 | return count; |
1769 | } | |
1770 | ||
1771 | /* | |
3fbacffb KS |
1772 | * Can't use DEVICE_ATTR because the attribute should be named |
1773 | * stp/online but dev_attr_online already exists in this file .. | |
d2fec595 | 1774 | */ |
3fbacffb | 1775 | static struct device_attribute dev_attr_stp_online = { |
d2fec595 MS |
1776 | .attr = { .name = "online", .mode = 0600 }, |
1777 | .show = stp_online_show, | |
1778 | .store = stp_online_store, | |
1779 | }; | |
1780 | ||
3fbacffb KS |
1781 | static struct device_attribute *stp_attributes[] = { |
1782 | &dev_attr_ctn_id, | |
1783 | &dev_attr_ctn_type, | |
1784 | &dev_attr_dst_offset, | |
1785 | &dev_attr_leap_seconds, | |
1786 | &dev_attr_stp_online, | |
1787 | &dev_attr_stratum, | |
1788 | &dev_attr_time_offset, | |
1789 | &dev_attr_time_zone_offset, | |
1790 | &dev_attr_timing_mode, | |
1791 | &dev_attr_timing_state, | |
d2fec595 MS |
1792 | NULL |
1793 | }; | |
1794 | ||
1795 | static int __init stp_init_sysfs(void) | |
1796 | { | |
3fbacffb | 1797 | struct device_attribute **attr; |
d2fec595 MS |
1798 | int rc; |
1799 | ||
3fbacffb | 1800 | rc = subsys_system_register(&stp_subsys, NULL); |
d2fec595 MS |
1801 | if (rc) |
1802 | goto out; | |
1803 | for (attr = stp_attributes; *attr; attr++) { | |
3fbacffb | 1804 | rc = device_create_file(stp_subsys.dev_root, *attr); |
d2fec595 MS |
1805 | if (rc) |
1806 | goto out_unreg; | |
1807 | } | |
1808 | return 0; | |
1809 | out_unreg: | |
1810 | for (; attr >= stp_attributes; attr--) | |
3fbacffb KS |
1811 | device_remove_file(stp_subsys.dev_root, *attr); |
1812 | bus_unregister(&stp_subsys); | |
d2fec595 MS |
1813 | out: |
1814 | return rc; | |
1815 | } | |
1816 | ||
1817 | device_initcall(stp_init_sysfs); |