[S390] convert cpacf printks to pr_xxx macros.
[deliverable/linux.git] / arch / s390 / kernel / time.c
CommitLineData
1da177e4
LT
1/*
2 * arch/s390/kernel/time.c
3 * Time of day based timer functions.
4 *
5 * S390 version
d2fec595 6 * Copyright IBM Corp. 1999, 2008
1da177e4
LT
7 * Author(s): Hartmut Penner (hp@de.ibm.com),
8 * Martin Schwidefsky (schwidefsky@de.ibm.com),
9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 *
11 * Derived from "arch/i386/kernel/time.c"
12 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
13 */
14
1da177e4
LT
15#include <linux/errno.h>
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/param.h>
20#include <linux/string.h>
21#include <linux/mm.h>
22#include <linux/interrupt.h>
750887de
HC
23#include <linux/cpu.h>
24#include <linux/stop_machine.h>
1da177e4 25#include <linux/time.h>
3367b994 26#include <linux/sysdev.h>
1da177e4
LT
27#include <linux/delay.h>
28#include <linux/init.h>
29#include <linux/smp.h>
30#include <linux/types.h>
31#include <linux/profile.h>
32#include <linux/timex.h>
33#include <linux/notifier.h>
dc64bef5 34#include <linux/clocksource.h>
5a62b192 35#include <linux/clockchips.h>
d2fec595 36#include <linux/bootmem.h>
1da177e4
LT
37#include <asm/uaccess.h>
38#include <asm/delay.h>
39#include <asm/s390_ext.h>
40#include <asm/div64.h>
b020632e 41#include <asm/vdso.h>
1da177e4 42#include <asm/irq.h>
5a489b98 43#include <asm/irq_regs.h>
1da177e4 44#include <asm/timer.h>
d54853ef 45#include <asm/etr.h>
a806170e 46#include <asm/cio.h>
1da177e4
LT
47
48/* change this if you have some constant time drift */
49#define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
50#define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
51
d54853ef
MS
52/* The value of the TOD clock for 1.1.1970. */
53#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
54
1da177e4
LT
55/*
56 * Create a small time difference between the timer interrupts
57 * on the different cpus to avoid lock contention.
58 */
59#define CPU_DEVIATION (smp_processor_id() << 12)
60
61#define TICK_SIZE tick
62
1da177e4 63static ext_int_info_t ext_int_info_cc;
d54853ef 64static ext_int_info_t ext_int_etr_cc;
8107d829 65static u64 sched_clock_base_cc;
5a62b192
HC
66
67static DEFINE_PER_CPU(struct clock_event_device, comparators);
1da177e4 68
1da177e4
LT
69/*
70 * Scheduler clock - returns current time in nanosec units.
71 */
72unsigned long long sched_clock(void)
73{
8107d829 74 return ((get_clock_xt() - sched_clock_base_cc) * 125) >> 9;
1da177e4
LT
75}
76
32f65f27
JG
77/*
78 * Monotonic_clock - returns # of nanoseconds passed since time_init()
79 */
80unsigned long long monotonic_clock(void)
81{
82 return sched_clock();
83}
84EXPORT_SYMBOL(monotonic_clock);
85
1da177e4
LT
86void tod_to_timeval(__u64 todval, struct timespec *xtime)
87{
88 unsigned long long sec;
89
90 sec = todval >> 12;
91 do_div(sec, 1000000);
92 xtime->tv_sec = sec;
93 todval -= (sec * 1000000) << 12;
94 xtime->tv_nsec = ((todval * 1000) >> 12);
95}
96
1da177e4 97#ifdef CONFIG_PROFILING
5a489b98 98#define s390_do_profile() profile_tick(CPU_PROFILING)
1da177e4 99#else
5a489b98 100#define s390_do_profile() do { ; } while(0)
1da177e4
LT
101#endif /* CONFIG_PROFILING */
102
5a62b192 103void clock_comparator_work(void)
1da177e4 104{
5a62b192 105 struct clock_event_device *cd;
1da177e4 106
5a62b192
HC
107 S390_lowcore.clock_comparator = -1ULL;
108 set_clock_comparator(S390_lowcore.clock_comparator);
109 cd = &__get_cpu_var(comparators);
110 cd->event_handler(cd);
5a489b98 111 s390_do_profile();
1da177e4
LT
112}
113
1da177e4 114/*
5a62b192 115 * Fixup the clock comparator.
1da177e4 116 */
5a62b192 117static void fixup_clock_comparator(unsigned long long delta)
1da177e4 118{
5a62b192
HC
119 /* If nobody is waiting there's nothing to fix. */
120 if (S390_lowcore.clock_comparator == -1ULL)
1da177e4 121 return;
5a62b192
HC
122 S390_lowcore.clock_comparator += delta;
123 set_clock_comparator(S390_lowcore.clock_comparator);
1da177e4
LT
124}
125
5a62b192
HC
126static int s390_next_event(unsigned long delta,
127 struct clock_event_device *evt)
1da177e4 128{
5a62b192
HC
129 S390_lowcore.clock_comparator = get_clock() + delta;
130 set_clock_comparator(S390_lowcore.clock_comparator);
131 return 0;
1da177e4
LT
132}
133
5a62b192
HC
134static void s390_set_mode(enum clock_event_mode mode,
135 struct clock_event_device *evt)
1da177e4 136{
d54853ef
MS
137}
138
139/*
140 * Set up lowcore and control register of the current cpu to
141 * enable TOD clock and clock comparator interrupts.
1da177e4
LT
142 */
143void init_cpu_timer(void)
144{
5a62b192
HC
145 struct clock_event_device *cd;
146 int cpu;
147
148 S390_lowcore.clock_comparator = -1ULL;
149 set_clock_comparator(S390_lowcore.clock_comparator);
150
151 cpu = smp_processor_id();
152 cd = &per_cpu(comparators, cpu);
153 cd->name = "comparator";
154 cd->features = CLOCK_EVT_FEAT_ONESHOT;
155 cd->mult = 16777;
156 cd->shift = 12;
157 cd->min_delta_ns = 1;
158 cd->max_delta_ns = LONG_MAX;
159 cd->rating = 400;
160 cd->cpumask = cpumask_of_cpu(cpu);
161 cd->set_next_event = s390_next_event;
162 cd->set_mode = s390_set_mode;
163
164 clockevents_register_device(cd);
d54853ef
MS
165
166 /* Enable clock comparator timer interrupt. */
167 __ctl_set_bit(0,11);
168
d2fec595 169 /* Always allow the timing alert external interrupt. */
d54853ef
MS
170 __ctl_set_bit(0, 4);
171}
172
173static void clock_comparator_interrupt(__u16 code)
174{
d3d238c7
HC
175 if (S390_lowcore.clock_comparator == -1ULL)
176 set_clock_comparator(S390_lowcore.clock_comparator);
d54853ef
MS
177}
178
d2fec595
MS
179static void etr_timing_alert(struct etr_irq_parm *);
180static void stp_timing_alert(struct stp_irq_parm *);
181
182static void timing_alert_interrupt(__u16 code)
183{
184 if (S390_lowcore.ext_params & 0x00c40000)
185 etr_timing_alert((struct etr_irq_parm *)
186 &S390_lowcore.ext_params);
187 if (S390_lowcore.ext_params & 0x00038000)
188 stp_timing_alert((struct stp_irq_parm *)
189 &S390_lowcore.ext_params);
190}
191
d54853ef 192static void etr_reset(void);
d2fec595 193static void stp_reset(void);
d54853ef
MS
194
195/*
196 * Get the TOD clock running.
197 */
198static u64 __init reset_tod_clock(void)
199{
200 u64 time;
201
202 etr_reset();
d2fec595 203 stp_reset();
d54853ef
MS
204 if (store_clock(&time) == 0)
205 return time;
206 /* TOD clock not running. Set the clock to Unix Epoch. */
207 if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0)
208 panic("TOD clock not operational.");
1da177e4 209
d54853ef 210 return TOD_UNIX_EPOCH;
1da177e4
LT
211}
212
dc64bef5
MS
213static cycle_t read_tod_clock(void)
214{
215 return get_clock();
216}
217
218static struct clocksource clocksource_tod = {
219 .name = "tod",
d2cb0e6e 220 .rating = 400,
dc64bef5
MS
221 .read = read_tod_clock,
222 .mask = -1ULL,
223 .mult = 1000,
224 .shift = 12,
cc02d809 225 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
dc64bef5
MS
226};
227
228
b020632e
MS
229void update_vsyscall(struct timespec *wall_time, struct clocksource *clock)
230{
231 if (clock != &clocksource_tod)
232 return;
233
234 /* Make userspace gettimeofday spin until we're done. */
235 ++vdso_data->tb_update_count;
236 smp_wmb();
237 vdso_data->xtime_tod_stamp = clock->cycle_last;
238 vdso_data->xtime_clock_sec = xtime.tv_sec;
239 vdso_data->xtime_clock_nsec = xtime.tv_nsec;
240 vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec;
241 vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec;
242 smp_wmb();
243 ++vdso_data->tb_update_count;
244}
245
246extern struct timezone sys_tz;
247
248void update_vsyscall_tz(void)
249{
250 /* Make userspace gettimeofday spin until we're done. */
251 ++vdso_data->tb_update_count;
252 smp_wmb();
253 vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
254 vdso_data->tz_dsttime = sys_tz.tz_dsttime;
255 smp_wmb();
256 ++vdso_data->tb_update_count;
257}
258
1da177e4
LT
259/*
260 * Initialize the TOD clock and the CPU timer of
261 * the boot cpu.
262 */
263void __init time_init(void)
264{
8107d829 265 sched_clock_base_cc = reset_tod_clock();
1da177e4
LT
266
267 /* set xtime */
8107d829 268 tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, &xtime);
1da177e4
LT
269 set_normalized_timespec(&wall_to_monotonic,
270 -xtime.tv_sec, -xtime.tv_nsec);
271
272 /* request the clock comparator external interrupt */
d54853ef
MS
273 if (register_early_external_interrupt(0x1004,
274 clock_comparator_interrupt,
1da177e4
LT
275 &ext_int_info_cc) != 0)
276 panic("Couldn't request external interrupt 0x1004");
277
dc64bef5
MS
278 if (clocksource_register(&clocksource_tod) != 0)
279 panic("Could not register TOD clock source");
280
d2fec595
MS
281 /* request the timing alert external interrupt */
282 if (register_early_external_interrupt(0x1406,
283 timing_alert_interrupt,
d54853ef
MS
284 &ext_int_etr_cc) != 0)
285 panic("Couldn't request external interrupt 0x1406");
286
287 /* Enable TOD clock interrupts on the boot cpu. */
288 init_cpu_timer();
c185b783 289 /* Enable cpu timer interrupts on the boot cpu. */
1da177e4 290 vtime_init();
d54853ef
MS
291}
292
d2fec595
MS
293/*
294 * The time is "clock". old is what we think the time is.
295 * Adjust the value by a multiple of jiffies and add the delta to ntp.
296 * "delay" is an approximation how long the synchronization took. If
297 * the time correction is positive, then "delay" is subtracted from
298 * the time difference and only the remaining part is passed to ntp.
299 */
300static unsigned long long adjust_time(unsigned long long old,
301 unsigned long long clock,
302 unsigned long long delay)
303{
304 unsigned long long delta, ticks;
305 struct timex adjust;
306
307 if (clock > old) {
308 /* It is later than we thought. */
309 delta = ticks = clock - old;
310 delta = ticks = (delta < delay) ? 0 : delta - delay;
311 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
312 adjust.offset = ticks * (1000000 / HZ);
313 } else {
314 /* It is earlier than we thought. */
315 delta = ticks = old - clock;
316 delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
317 delta = -delta;
318 adjust.offset = -ticks * (1000000 / HZ);
319 }
8107d829 320 sched_clock_base_cc += delta;
d2fec595
MS
321 if (adjust.offset != 0) {
322 printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n",
323 adjust.offset);
324 adjust.modes = ADJ_OFFSET_SINGLESHOT;
325 do_adjtimex(&adjust);
326 }
327 return delta;
328}
329
330static DEFINE_PER_CPU(atomic_t, clock_sync_word);
331static unsigned long clock_sync_flags;
332
333#define CLOCK_SYNC_HAS_ETR 0
334#define CLOCK_SYNC_HAS_STP 1
335#define CLOCK_SYNC_ETR 2
336#define CLOCK_SYNC_STP 3
337
338/*
339 * The synchronous get_clock function. It will write the current clock
340 * value to the clock pointer and return 0 if the clock is in sync with
341 * the external time source. If the clock mode is local it will return
342 * -ENOSYS and -EAGAIN if the clock is not in sync with the external
343 * reference.
344 */
345int get_sync_clock(unsigned long long *clock)
346{
347 atomic_t *sw_ptr;
348 unsigned int sw0, sw1;
349
350 sw_ptr = &get_cpu_var(clock_sync_word);
351 sw0 = atomic_read(sw_ptr);
352 *clock = get_clock();
353 sw1 = atomic_read(sw_ptr);
354 put_cpu_var(clock_sync_sync);
355 if (sw0 == sw1 && (sw0 & 0x80000000U))
356 /* Success: time is in sync. */
357 return 0;
358 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
359 !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
360 return -ENOSYS;
361 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
362 !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
363 return -EACCES;
364 return -EAGAIN;
365}
366EXPORT_SYMBOL(get_sync_clock);
367
368/*
369 * Make get_sync_clock return -EAGAIN.
370 */
371static void disable_sync_clock(void *dummy)
372{
373 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
374 /*
375 * Clear the in-sync bit 2^31. All get_sync_clock calls will
376 * fail until the sync bit is turned back on. In addition
377 * increase the "sequence" counter to avoid the race of an
378 * etr event and the complete recovery against get_sync_clock.
379 */
380 atomic_clear_mask(0x80000000, sw_ptr);
381 atomic_inc(sw_ptr);
382}
383
384/*
385 * Make get_sync_clock return 0 again.
386 * Needs to be called from a context disabled for preemption.
387 */
388static void enable_sync_clock(void)
389{
390 atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
391 atomic_set_mask(0x80000000, sw_ptr);
392}
393
750887de
HC
394/* Single threaded workqueue used for etr and stp sync events */
395static struct workqueue_struct *time_sync_wq;
396
397static void __init time_init_wq(void)
398{
399 if (!time_sync_wq)
400 time_sync_wq = create_singlethread_workqueue("timesync");
401}
402
d54853ef
MS
403/*
404 * External Time Reference (ETR) code.
405 */
406static int etr_port0_online;
407static int etr_port1_online;
d2fec595 408static int etr_steai_available;
d54853ef
MS
409
410static int __init early_parse_etr(char *p)
411{
412 if (strncmp(p, "off", 3) == 0)
413 etr_port0_online = etr_port1_online = 0;
414 else if (strncmp(p, "port0", 5) == 0)
415 etr_port0_online = 1;
416 else if (strncmp(p, "port1", 5) == 0)
417 etr_port1_online = 1;
418 else if (strncmp(p, "on", 2) == 0)
419 etr_port0_online = etr_port1_online = 1;
420 return 0;
421}
422early_param("etr", early_parse_etr);
423
424enum etr_event {
425 ETR_EVENT_PORT0_CHANGE,
426 ETR_EVENT_PORT1_CHANGE,
427 ETR_EVENT_PORT_ALERT,
428 ETR_EVENT_SYNC_CHECK,
429 ETR_EVENT_SWITCH_LOCAL,
430 ETR_EVENT_UPDATE,
431};
432
d54853ef
MS
433/*
434 * Valid bit combinations of the eacr register are (x = don't care):
435 * e0 e1 dp p0 p1 ea es sl
436 * 0 0 x 0 0 0 0 0 initial, disabled state
437 * 0 0 x 0 1 1 0 0 port 1 online
438 * 0 0 x 1 0 1 0 0 port 0 online
439 * 0 0 x 1 1 1 0 0 both ports online
440 * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
441 * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
442 * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
443 * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
444 * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
445 * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
446 * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
447 * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
448 * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
449 * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
450 * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
451 * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
452 * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
453 * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
454 * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
455 * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
456 */
457static struct etr_eacr etr_eacr;
458static u64 etr_tolec; /* time of last eacr update */
d54853ef
MS
459static struct etr_aib etr_port0;
460static int etr_port0_uptodate;
461static struct etr_aib etr_port1;
462static int etr_port1_uptodate;
463static unsigned long etr_events;
464static struct timer_list etr_timer;
d54853ef
MS
465
466static void etr_timeout(unsigned long dummy);
ecdcc023 467static void etr_work_fn(struct work_struct *work);
0b3016b7 468static DEFINE_MUTEX(etr_work_mutex);
ecdcc023 469static DECLARE_WORK(etr_work, etr_work_fn);
d54853ef 470
d54853ef
MS
471/*
472 * Reset ETR attachment.
473 */
474static void etr_reset(void)
475{
476 etr_eacr = (struct etr_eacr) {
477 .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
478 .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
479 .es = 0, .sl = 0 };
d2fec595 480 if (etr_setr(&etr_eacr) == 0) {
d54853ef 481 etr_tolec = get_clock();
d2fec595
MS
482 set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
483 } else if (etr_port0_online || etr_port1_online) {
484 printk(KERN_WARNING "Running on non ETR capable "
485 "machine, only local mode available.\n");
486 etr_port0_online = etr_port1_online = 0;
d54853ef
MS
487 }
488}
489
ecdcc023 490static int __init etr_init(void)
d54853ef
MS
491{
492 struct etr_aib aib;
493
d2fec595 494 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
ecdcc023 495 return 0;
750887de 496 time_init_wq();
d54853ef
MS
497 /* Check if this machine has the steai instruction. */
498 if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
d2fec595 499 etr_steai_available = 1;
d54853ef 500 setup_timer(&etr_timer, etr_timeout, 0UL);
d54853ef
MS
501 if (etr_port0_online) {
502 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 503 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
504 }
505 if (etr_port1_online) {
506 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 507 queue_work(time_sync_wq, &etr_work);
d54853ef 508 }
ecdcc023 509 return 0;
d54853ef
MS
510}
511
ecdcc023
MS
512arch_initcall(etr_init);
513
d54853ef
MS
514/*
515 * Two sorts of ETR machine checks. The architecture reads:
516 * "When a machine-check niterruption occurs and if a switch-to-local or
517 * ETR-sync-check interrupt request is pending but disabled, this pending
518 * disabled interruption request is indicated and is cleared".
519 * Which means that we can get etr_switch_to_local events from the machine
520 * check handler although the interruption condition is disabled. Lovely..
521 */
522
523/*
524 * Switch to local machine check. This is called when the last usable
525 * ETR port goes inactive. After switch to local the clock is not in sync.
526 */
527void etr_switch_to_local(void)
528{
529 if (!etr_eacr.sl)
530 return;
d2fec595
MS
531 if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
532 disable_sync_clock(NULL);
d54853ef 533 set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
750887de 534 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
535}
536
537/*
538 * ETR sync check machine check. This is called when the ETR OTE and the
539 * local clock OTE are farther apart than the ETR sync check tolerance.
540 * After a ETR sync check the clock is not in sync. The machine check
541 * is broadcasted to all cpus at the same time.
542 */
543void etr_sync_check(void)
544{
545 if (!etr_eacr.es)
546 return;
d2fec595
MS
547 if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
548 disable_sync_clock(NULL);
d54853ef 549 set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
750887de 550 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
551}
552
553/*
d2fec595 554 * ETR timing alert. There are two causes:
d54853ef
MS
555 * 1) port state change, check the usability of the port
556 * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
557 * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
558 * or ETR-data word 4 (edf4) has changed.
559 */
d2fec595 560static void etr_timing_alert(struct etr_irq_parm *intparm)
d54853ef 561{
d54853ef
MS
562 if (intparm->pc0)
563 /* ETR port 0 state change. */
564 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
565 if (intparm->pc1)
566 /* ETR port 1 state change. */
567 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
568 if (intparm->eai)
569 /*
570 * ETR port alert on either port 0, 1 or both.
571 * Both ports are not up-to-date now.
572 */
573 set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
750887de 574 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
575}
576
577static void etr_timeout(unsigned long dummy)
578{
579 set_bit(ETR_EVENT_UPDATE, &etr_events);
750887de 580 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
581}
582
583/*
584 * Check if the etr mode is pss.
585 */
586static inline int etr_mode_is_pps(struct etr_eacr eacr)
587{
588 return eacr.es && !eacr.sl;
589}
590
591/*
592 * Check if the etr mode is etr.
593 */
594static inline int etr_mode_is_etr(struct etr_eacr eacr)
595{
596 return eacr.es && eacr.sl;
597}
598
599/*
600 * Check if the port can be used for TOD synchronization.
601 * For PPS mode the port has to receive OTEs. For ETR mode
602 * the port has to receive OTEs, the ETR stepping bit has to
603 * be zero and the validity bits for data frame 1, 2, and 3
604 * have to be 1.
605 */
606static int etr_port_valid(struct etr_aib *aib, int port)
607{
608 unsigned int psc;
609
610 /* Check that this port is receiving OTEs. */
611 if (aib->tsp == 0)
612 return 0;
613
614 psc = port ? aib->esw.psc1 : aib->esw.psc0;
615 if (psc == etr_lpsc_pps_mode)
616 return 1;
617 if (psc == etr_lpsc_operational_step)
618 return !aib->esw.y && aib->slsw.v1 &&
619 aib->slsw.v2 && aib->slsw.v3;
620 return 0;
621}
622
623/*
624 * Check if two ports are on the same network.
625 */
626static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
627{
628 // FIXME: any other fields we have to compare?
629 return aib1->edf1.net_id == aib2->edf1.net_id;
630}
631
632/*
633 * Wrapper for etr_stei that converts physical port states
634 * to logical port states to be consistent with the output
635 * of stetr (see etr_psc vs. etr_lpsc).
636 */
637static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
638{
639 BUG_ON(etr_steai(aib, func) != 0);
640 /* Convert port state to logical port state. */
641 if (aib->esw.psc0 == 1)
642 aib->esw.psc0 = 2;
643 else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
644 aib->esw.psc0 = 1;
645 if (aib->esw.psc1 == 1)
646 aib->esw.psc1 = 2;
647 else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
648 aib->esw.psc1 = 1;
649}
650
651/*
652 * Check if the aib a2 is still connected to the same attachment as
653 * aib a1, the etv values differ by one and a2 is valid.
654 */
655static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
656{
657 int state_a1, state_a2;
658
659 /* Paranoia check: e0/e1 should better be the same. */
660 if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
661 a1->esw.eacr.e1 != a2->esw.eacr.e1)
662 return 0;
663
664 /* Still connected to the same etr ? */
665 state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
666 state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
667 if (state_a1 == etr_lpsc_operational_step) {
668 if (state_a2 != etr_lpsc_operational_step ||
669 a1->edf1.net_id != a2->edf1.net_id ||
670 a1->edf1.etr_id != a2->edf1.etr_id ||
671 a1->edf1.etr_pn != a2->edf1.etr_pn)
672 return 0;
673 } else if (state_a2 != etr_lpsc_pps_mode)
674 return 0;
675
676 /* The ETV value of a2 needs to be ETV of a1 + 1. */
677 if (a1->edf2.etv + 1 != a2->edf2.etv)
678 return 0;
679
680 if (!etr_port_valid(a2, p))
681 return 0;
682
683 return 1;
684}
685
d2fec595 686struct clock_sync_data {
750887de 687 atomic_t cpus;
5a62b192
HC
688 int in_sync;
689 unsigned long long fixup_cc;
750887de
HC
690 int etr_port;
691 struct etr_aib *etr_aib;
d2fec595 692};
5a62b192 693
750887de 694static void clock_sync_cpu(struct clock_sync_data *sync)
d54853ef 695{
750887de 696 atomic_dec(&sync->cpus);
d2fec595 697 enable_sync_clock();
d54853ef
MS
698 /*
699 * This looks like a busy wait loop but it isn't. etr_sync_cpus
700 * is called on all other cpus while the TOD clocks is stopped.
701 * __udelay will stop the cpu on an enabled wait psw until the
702 * TOD is running again.
703 */
d2fec595 704 while (sync->in_sync == 0) {
d54853ef 705 __udelay(1);
6c732de2
HC
706 /*
707 * A different cpu changes *in_sync. Therefore use
708 * barrier() to force memory access.
709 */
710 barrier();
711 }
d2fec595 712 if (sync->in_sync != 1)
d54853ef 713 /* Didn't work. Clear per-cpu in sync bit again. */
d2fec595 714 disable_sync_clock(NULL);
d54853ef
MS
715 /*
716 * This round of TOD syncing is done. Set the clock comparator
717 * to the next tick and let the processor continue.
718 */
d2fec595 719 fixup_clock_comparator(sync->fixup_cc);
d54853ef
MS
720}
721
d54853ef
MS
722/*
723 * Sync the TOD clock using the port refered to by aibp. This port
724 * has to be enabled and the other port has to be disabled. The
725 * last eacr update has to be more than 1.6 seconds in the past.
726 */
750887de 727static int etr_sync_clock(void *data)
d54853ef 728{
750887de 729 static int first;
5a62b192 730 unsigned long long clock, old_clock, delay, delta;
750887de
HC
731 struct clock_sync_data *etr_sync;
732 struct etr_aib *sync_port, *aib;
733 int port;
d54853ef
MS
734 int rc;
735
750887de 736 etr_sync = data;
d54853ef 737
750887de
HC
738 if (xchg(&first, 1) == 1) {
739 /* Slave */
740 clock_sync_cpu(etr_sync);
741 return 0;
742 }
743
744 /* Wait until all other cpus entered the sync function. */
745 while (atomic_read(&etr_sync->cpus) != 0)
746 cpu_relax();
747
748 port = etr_sync->etr_port;
749 aib = etr_sync->etr_aib;
750 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
d2fec595 751 enable_sync_clock();
d54853ef
MS
752
753 /* Set clock to next OTE. */
754 __ctl_set_bit(14, 21);
755 __ctl_set_bit(0, 29);
756 clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
5a62b192 757 old_clock = get_clock();
d54853ef
MS
758 if (set_clock(clock) == 0) {
759 __udelay(1); /* Wait for the clock to start. */
760 __ctl_clear_bit(0, 29);
761 __ctl_clear_bit(14, 21);
762 etr_stetr(aib);
763 /* Adjust Linux timing variables. */
764 delay = (unsigned long long)
765 (aib->edf2.etv - sync_port->edf2.etv) << 32;
d2fec595 766 delta = adjust_time(old_clock, clock, delay);
750887de 767 etr_sync->fixup_cc = delta;
5a62b192 768 fixup_clock_comparator(delta);
d54853ef
MS
769 /* Verify that the clock is properly set. */
770 if (!etr_aib_follows(sync_port, aib, port)) {
771 /* Didn't work. */
d2fec595 772 disable_sync_clock(NULL);
750887de 773 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
774 rc = -EAGAIN;
775 } else {
750887de 776 etr_sync->in_sync = 1;
d54853ef
MS
777 rc = 0;
778 }
779 } else {
780 /* Could not set the clock ?!? */
781 __ctl_clear_bit(0, 29);
782 __ctl_clear_bit(14, 21);
d2fec595 783 disable_sync_clock(NULL);
750887de 784 etr_sync->in_sync = -EAGAIN;
d54853ef
MS
785 rc = -EAGAIN;
786 }
750887de
HC
787 xchg(&first, 0);
788 return rc;
789}
790
791static int etr_sync_clock_stop(struct etr_aib *aib, int port)
792{
793 struct clock_sync_data etr_sync;
794 struct etr_aib *sync_port;
795 int follows;
796 int rc;
797
798 /* Check if the current aib is adjacent to the sync port aib. */
799 sync_port = (port == 0) ? &etr_port0 : &etr_port1;
800 follows = etr_aib_follows(sync_port, aib, port);
801 memcpy(sync_port, aib, sizeof(*aib));
802 if (!follows)
803 return -EAGAIN;
804 memset(&etr_sync, 0, sizeof(etr_sync));
805 etr_sync.etr_aib = aib;
806 etr_sync.etr_port = port;
807 get_online_cpus();
808 atomic_set(&etr_sync.cpus, num_online_cpus() - 1);
809 rc = stop_machine(etr_sync_clock, &etr_sync, &cpu_online_map);
810 put_online_cpus();
d54853ef
MS
811 return rc;
812}
813
814/*
815 * Handle the immediate effects of the different events.
816 * The port change event is used for online/offline changes.
817 */
818static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
819{
820 if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
821 eacr.es = 0;
822 if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
823 eacr.es = eacr.sl = 0;
824 if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
825 etr_port0_uptodate = etr_port1_uptodate = 0;
826
827 if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
828 if (eacr.e0)
829 /*
830 * Port change of an enabled port. We have to
831 * assume that this can have caused an stepping
832 * port switch.
833 */
834 etr_tolec = get_clock();
835 eacr.p0 = etr_port0_online;
836 if (!eacr.p0)
837 eacr.e0 = 0;
838 etr_port0_uptodate = 0;
839 }
840 if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
841 if (eacr.e1)
842 /*
843 * Port change of an enabled port. We have to
844 * assume that this can have caused an stepping
845 * port switch.
846 */
847 etr_tolec = get_clock();
848 eacr.p1 = etr_port1_online;
849 if (!eacr.p1)
850 eacr.e1 = 0;
851 etr_port1_uptodate = 0;
852 }
853 clear_bit(ETR_EVENT_UPDATE, &etr_events);
854 return eacr;
855}
856
857/*
858 * Set up a timer that expires after the etr_tolec + 1.6 seconds if
859 * one of the ports needs an update.
860 */
861static void etr_set_tolec_timeout(unsigned long long now)
862{
863 unsigned long micros;
864
865 if ((!etr_eacr.p0 || etr_port0_uptodate) &&
866 (!etr_eacr.p1 || etr_port1_uptodate))
867 return;
868 micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
869 micros = (micros > 1600000) ? 0 : 1600000 - micros;
870 mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
871}
872
873/*
874 * Set up a time that expires after 1/2 second.
875 */
876static void etr_set_sync_timeout(void)
877{
878 mod_timer(&etr_timer, jiffies + HZ/2);
879}
880
881/*
882 * Update the aib information for one or both ports.
883 */
884static struct etr_eacr etr_handle_update(struct etr_aib *aib,
885 struct etr_eacr eacr)
886{
887 /* With both ports disabled the aib information is useless. */
888 if (!eacr.e0 && !eacr.e1)
889 return eacr;
890
ecdcc023 891 /* Update port0 or port1 with aib stored in etr_work_fn. */
d54853ef
MS
892 if (aib->esw.q == 0) {
893 /* Information for port 0 stored. */
894 if (eacr.p0 && !etr_port0_uptodate) {
895 etr_port0 = *aib;
896 if (etr_port0_online)
897 etr_port0_uptodate = 1;
898 }
899 } else {
900 /* Information for port 1 stored. */
901 if (eacr.p1 && !etr_port1_uptodate) {
902 etr_port1 = *aib;
903 if (etr_port0_online)
904 etr_port1_uptodate = 1;
905 }
906 }
907
908 /*
909 * Do not try to get the alternate port aib if the clock
910 * is not in sync yet.
911 */
d2fec595 912 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags) && !eacr.es)
d54853ef
MS
913 return eacr;
914
915 /*
916 * If steai is available we can get the information about
917 * the other port immediately. If only stetr is available the
918 * data-port bit toggle has to be used.
919 */
d2fec595 920 if (etr_steai_available) {
d54853ef
MS
921 if (eacr.p0 && !etr_port0_uptodate) {
922 etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
923 etr_port0_uptodate = 1;
924 }
925 if (eacr.p1 && !etr_port1_uptodate) {
926 etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
927 etr_port1_uptodate = 1;
928 }
929 } else {
930 /*
931 * One port was updated above, if the other
932 * port is not uptodate toggle dp bit.
933 */
934 if ((eacr.p0 && !etr_port0_uptodate) ||
935 (eacr.p1 && !etr_port1_uptodate))
936 eacr.dp ^= 1;
937 else
938 eacr.dp = 0;
939 }
940 return eacr;
941}
942
943/*
944 * Write new etr control register if it differs from the current one.
945 * Return 1 if etr_tolec has been updated as well.
946 */
947static void etr_update_eacr(struct etr_eacr eacr)
948{
949 int dp_changed;
950
951 if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
952 /* No change, return. */
953 return;
954 /*
955 * The disable of an active port of the change of the data port
956 * bit can/will cause a change in the data port.
957 */
958 dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
959 (etr_eacr.dp ^ eacr.dp) != 0;
960 etr_eacr = eacr;
961 etr_setr(&etr_eacr);
962 if (dp_changed)
963 etr_tolec = get_clock();
964}
965
966/*
750887de 967 * ETR work. In this function you'll find the main logic. In
d54853ef
MS
968 * particular this is the only function that calls etr_update_eacr(),
969 * it "controls" the etr control register.
970 */
ecdcc023 971static void etr_work_fn(struct work_struct *work)
d54853ef
MS
972{
973 unsigned long long now;
974 struct etr_eacr eacr;
975 struct etr_aib aib;
976 int sync_port;
977
0b3016b7
MS
978 /* prevent multiple execution. */
979 mutex_lock(&etr_work_mutex);
980
d54853ef
MS
981 /* Create working copy of etr_eacr. */
982 eacr = etr_eacr;
983
984 /* Check for the different events and their immediate effects. */
985 eacr = etr_handle_events(eacr);
986
987 /* Check if ETR is supposed to be active. */
988 eacr.ea = eacr.p0 || eacr.p1;
989 if (!eacr.ea) {
990 /* Both ports offline. Reset everything. */
991 eacr.dp = eacr.es = eacr.sl = 0;
1a781a77 992 on_each_cpu(disable_sync_clock, NULL, 1);
d54853ef
MS
993 del_timer_sync(&etr_timer);
994 etr_update_eacr(eacr);
d2fec595 995 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
0b3016b7 996 goto out_unlock;
d54853ef
MS
997 }
998
999 /* Store aib to get the current ETR status word. */
1000 BUG_ON(etr_stetr(&aib) != 0);
1001 etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
1002 now = get_clock();
1003
1004 /*
1005 * Update the port information if the last stepping port change
1006 * or data port change is older than 1.6 seconds.
1007 */
1008 if (now >= etr_tolec + (1600000 << 12))
1009 eacr = etr_handle_update(&aib, eacr);
1010
1011 /*
1012 * Select ports to enable. The prefered synchronization mode is PPS.
1013 * If a port can be enabled depends on a number of things:
1014 * 1) The port needs to be online and uptodate. A port is not
1015 * disabled just because it is not uptodate, but it is only
1016 * enabled if it is uptodate.
1017 * 2) The port needs to have the same mode (pps / etr).
1018 * 3) The port needs to be usable -> etr_port_valid() == 1
1019 * 4) To enable the second port the clock needs to be in sync.
1020 * 5) If both ports are useable and are ETR ports, the network id
1021 * has to be the same.
1022 * The eacr.sl bit is used to indicate etr mode vs. pps mode.
1023 */
1024 if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
1025 eacr.sl = 0;
1026 eacr.e0 = 1;
1027 if (!etr_mode_is_pps(etr_eacr))
1028 eacr.es = 0;
1029 if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
1030 eacr.e1 = 0;
1031 // FIXME: uptodate checks ?
1032 else if (etr_port0_uptodate && etr_port1_uptodate)
1033 eacr.e1 = 1;
1034 sync_port = (etr_port0_uptodate &&
1035 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1036 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
1037 eacr.sl = 0;
1038 eacr.e0 = 0;
1039 eacr.e1 = 1;
1040 if (!etr_mode_is_pps(etr_eacr))
1041 eacr.es = 0;
1042 sync_port = (etr_port1_uptodate &&
1043 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1044 } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
1045 eacr.sl = 1;
1046 eacr.e0 = 1;
1047 if (!etr_mode_is_etr(etr_eacr))
1048 eacr.es = 0;
1049 if (!eacr.es || !eacr.p1 ||
1050 aib.esw.psc1 != etr_lpsc_operational_alt)
1051 eacr.e1 = 0;
1052 else if (etr_port0_uptodate && etr_port1_uptodate &&
1053 etr_compare_network(&etr_port0, &etr_port1))
1054 eacr.e1 = 1;
1055 sync_port = (etr_port0_uptodate &&
1056 etr_port_valid(&etr_port0, 0)) ? 0 : -1;
d54853ef
MS
1057 } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
1058 eacr.sl = 1;
1059 eacr.e0 = 0;
1060 eacr.e1 = 1;
1061 if (!etr_mode_is_etr(etr_eacr))
1062 eacr.es = 0;
1063 sync_port = (etr_port1_uptodate &&
1064 etr_port_valid(&etr_port1, 1)) ? 1 : -1;
d54853ef
MS
1065 } else {
1066 /* Both ports not usable. */
1067 eacr.es = eacr.sl = 0;
1068 sync_port = -1;
d2fec595 1069 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
1070 }
1071
d2fec595
MS
1072 if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
1073 eacr.es = 0;
1074
d54853ef
MS
1075 /*
1076 * If the clock is in sync just update the eacr and return.
1077 * If there is no valid sync port wait for a port update.
1078 */
d2fec595
MS
1079 if (test_bit(CLOCK_SYNC_STP, &clock_sync_flags) ||
1080 eacr.es || sync_port < 0) {
d54853ef
MS
1081 etr_update_eacr(eacr);
1082 etr_set_tolec_timeout(now);
0b3016b7 1083 goto out_unlock;
d54853ef
MS
1084 }
1085
1086 /*
1087 * Prepare control register for clock syncing
1088 * (reset data port bit, set sync check control.
1089 */
1090 eacr.dp = 0;
1091 eacr.es = 1;
1092
1093 /*
1094 * Update eacr and try to synchronize the clock. If the update
1095 * of eacr caused a stepping port switch (or if we have to
1096 * assume that a stepping port switch has occured) or the
1097 * clock syncing failed, reset the sync check control bit
1098 * and set up a timer to try again after 0.5 seconds
1099 */
1100 etr_update_eacr(eacr);
d2fec595 1101 set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef 1102 if (now < etr_tolec + (1600000 << 12) ||
750887de 1103 etr_sync_clock_stop(&aib, sync_port) != 0) {
d54853ef
MS
1104 /* Sync failed. Try again in 1/2 second. */
1105 eacr.es = 0;
1106 etr_update_eacr(eacr);
d2fec595 1107 clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
d54853ef
MS
1108 etr_set_sync_timeout();
1109 } else
1110 etr_set_tolec_timeout(now);
0b3016b7
MS
1111out_unlock:
1112 mutex_unlock(&etr_work_mutex);
d54853ef
MS
1113}
1114
1115/*
1116 * Sysfs interface functions
1117 */
1118static struct sysdev_class etr_sysclass = {
af5ca3f4 1119 .name = "etr",
d54853ef
MS
1120};
1121
1122static struct sys_device etr_port0_dev = {
1123 .id = 0,
1124 .cls = &etr_sysclass,
1125};
1126
1127static struct sys_device etr_port1_dev = {
1128 .id = 1,
1129 .cls = &etr_sysclass,
1130};
1131
1132/*
1133 * ETR class attributes
1134 */
1135static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf)
1136{
1137 return sprintf(buf, "%i\n", etr_port0.esw.p);
1138}
1139
1140static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
1141
1142static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf)
1143{
1144 char *mode_str;
1145
1146 if (etr_mode_is_pps(etr_eacr))
1147 mode_str = "pps";
1148 else if (etr_mode_is_etr(etr_eacr))
1149 mode_str = "etr";
1150 else
1151 mode_str = "local";
1152 return sprintf(buf, "%s\n", mode_str);
1153}
1154
1155static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
1156
1157/*
1158 * ETR port attributes
1159 */
1160static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
1161{
1162 if (dev == &etr_port0_dev)
1163 return etr_port0_online ? &etr_port0 : NULL;
1164 else
1165 return etr_port1_online ? &etr_port1 : NULL;
1166}
1167
4a0b2b4d
AK
1168static ssize_t etr_online_show(struct sys_device *dev,
1169 struct sysdev_attribute *attr,
1170 char *buf)
d54853ef
MS
1171{
1172 unsigned int online;
1173
1174 online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
1175 return sprintf(buf, "%i\n", online);
1176}
1177
1178static ssize_t etr_online_store(struct sys_device *dev,
4a0b2b4d
AK
1179 struct sysdev_attribute *attr,
1180 const char *buf, size_t count)
d54853ef
MS
1181{
1182 unsigned int value;
1183
1184 value = simple_strtoul(buf, NULL, 0);
1185 if (value != 0 && value != 1)
1186 return -EINVAL;
d2fec595
MS
1187 if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
1188 return -EOPNOTSUPP;
d54853ef
MS
1189 if (dev == &etr_port0_dev) {
1190 if (etr_port0_online == value)
1191 return count; /* Nothing to do. */
1192 etr_port0_online = value;
1193 set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
750887de 1194 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
1195 } else {
1196 if (etr_port1_online == value)
1197 return count; /* Nothing to do. */
1198 etr_port1_online = value;
1199 set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
750887de 1200 queue_work(time_sync_wq, &etr_work);
d54853ef
MS
1201 }
1202 return count;
1203}
1204
1205static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
1206
4a0b2b4d
AK
1207static ssize_t etr_stepping_control_show(struct sys_device *dev,
1208 struct sysdev_attribute *attr,
1209 char *buf)
d54853ef
MS
1210{
1211 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1212 etr_eacr.e0 : etr_eacr.e1);
1213}
1214
1215static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
1216
4a0b2b4d
AK
1217static ssize_t etr_mode_code_show(struct sys_device *dev,
1218 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1219{
1220 if (!etr_port0_online && !etr_port1_online)
1221 /* Status word is not uptodate if both ports are offline. */
1222 return -ENODATA;
1223 return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
1224 etr_port0.esw.psc0 : etr_port0.esw.psc1);
1225}
1226
1227static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
1228
4a0b2b4d
AK
1229static ssize_t etr_untuned_show(struct sys_device *dev,
1230 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1231{
1232 struct etr_aib *aib = etr_aib_from_dev(dev);
1233
1234 if (!aib || !aib->slsw.v1)
1235 return -ENODATA;
1236 return sprintf(buf, "%i\n", aib->edf1.u);
1237}
1238
1239static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
1240
4a0b2b4d
AK
1241static ssize_t etr_network_id_show(struct sys_device *dev,
1242 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1243{
1244 struct etr_aib *aib = etr_aib_from_dev(dev);
1245
1246 if (!aib || !aib->slsw.v1)
1247 return -ENODATA;
1248 return sprintf(buf, "%i\n", aib->edf1.net_id);
1249}
1250
1251static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
1252
4a0b2b4d
AK
1253static ssize_t etr_id_show(struct sys_device *dev,
1254 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1255{
1256 struct etr_aib *aib = etr_aib_from_dev(dev);
1257
1258 if (!aib || !aib->slsw.v1)
1259 return -ENODATA;
1260 return sprintf(buf, "%i\n", aib->edf1.etr_id);
1261}
1262
1263static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
1264
4a0b2b4d
AK
1265static ssize_t etr_port_number_show(struct sys_device *dev,
1266 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1267{
1268 struct etr_aib *aib = etr_aib_from_dev(dev);
1269
1270 if (!aib || !aib->slsw.v1)
1271 return -ENODATA;
1272 return sprintf(buf, "%i\n", aib->edf1.etr_pn);
1273}
1274
1275static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
1276
4a0b2b4d
AK
1277static ssize_t etr_coupled_show(struct sys_device *dev,
1278 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1279{
1280 struct etr_aib *aib = etr_aib_from_dev(dev);
1281
1282 if (!aib || !aib->slsw.v3)
1283 return -ENODATA;
1284 return sprintf(buf, "%i\n", aib->edf3.c);
1285}
1286
1287static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
1288
4a0b2b4d
AK
1289static ssize_t etr_local_time_show(struct sys_device *dev,
1290 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1291{
1292 struct etr_aib *aib = etr_aib_from_dev(dev);
1293
1294 if (!aib || !aib->slsw.v3)
1295 return -ENODATA;
1296 return sprintf(buf, "%i\n", aib->edf3.blto);
1297}
1298
1299static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
1300
4a0b2b4d
AK
1301static ssize_t etr_utc_offset_show(struct sys_device *dev,
1302 struct sysdev_attribute *attr, char *buf)
d54853ef
MS
1303{
1304 struct etr_aib *aib = etr_aib_from_dev(dev);
1305
1306 if (!aib || !aib->slsw.v3)
1307 return -ENODATA;
1308 return sprintf(buf, "%i\n", aib->edf3.buo);
1309}
1310
1311static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
1312
1313static struct sysdev_attribute *etr_port_attributes[] = {
1314 &attr_online,
1315 &attr_stepping_control,
1316 &attr_state_code,
1317 &attr_untuned,
1318 &attr_network,
1319 &attr_id,
1320 &attr_port,
1321 &attr_coupled,
1322 &attr_local_time,
1323 &attr_utc_offset,
1324 NULL
1325};
1326
1327static int __init etr_register_port(struct sys_device *dev)
1328{
1329 struct sysdev_attribute **attr;
1330 int rc;
1331
1332 rc = sysdev_register(dev);
1333 if (rc)
1334 goto out;
1335 for (attr = etr_port_attributes; *attr; attr++) {
1336 rc = sysdev_create_file(dev, *attr);
1337 if (rc)
1338 goto out_unreg;
1339 }
1340 return 0;
1341out_unreg:
1342 for (; attr >= etr_port_attributes; attr--)
1343 sysdev_remove_file(dev, *attr);
1344 sysdev_unregister(dev);
1345out:
1346 return rc;
1347}
1348
1349static void __init etr_unregister_port(struct sys_device *dev)
1350{
1351 struct sysdev_attribute **attr;
1352
1353 for (attr = etr_port_attributes; *attr; attr++)
1354 sysdev_remove_file(dev, *attr);
1355 sysdev_unregister(dev);
1356}
1357
1358static int __init etr_init_sysfs(void)
1359{
1360 int rc;
1361
1362 rc = sysdev_class_register(&etr_sysclass);
1363 if (rc)
1364 goto out;
1365 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
1366 if (rc)
1367 goto out_unreg_class;
1368 rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
1369 if (rc)
1370 goto out_remove_stepping_port;
1371 rc = etr_register_port(&etr_port0_dev);
1372 if (rc)
1373 goto out_remove_stepping_mode;
1374 rc = etr_register_port(&etr_port1_dev);
1375 if (rc)
1376 goto out_remove_port0;
1377 return 0;
1378
1379out_remove_port0:
1380 etr_unregister_port(&etr_port0_dev);
1381out_remove_stepping_mode:
1382 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
1383out_remove_stepping_port:
1384 sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
1385out_unreg_class:
1386 sysdev_class_unregister(&etr_sysclass);
1387out:
1388 return rc;
1da177e4
LT
1389}
1390
d54853ef 1391device_initcall(etr_init_sysfs);
d2fec595
MS
1392
1393/*
1394 * Server Time Protocol (STP) code.
1395 */
1396static int stp_online;
1397static struct stp_sstpi stp_info;
1398static void *stp_page;
1399
1400static void stp_work_fn(struct work_struct *work);
0b3016b7 1401static DEFINE_MUTEX(stp_work_mutex);
d2fec595
MS
1402static DECLARE_WORK(stp_work, stp_work_fn);
1403
1404static int __init early_parse_stp(char *p)
1405{
1406 if (strncmp(p, "off", 3) == 0)
1407 stp_online = 0;
1408 else if (strncmp(p, "on", 2) == 0)
1409 stp_online = 1;
1410 return 0;
1411}
1412early_param("stp", early_parse_stp);
1413
1414/*
1415 * Reset STP attachment.
1416 */
8f847003 1417static void __init stp_reset(void)
d2fec595
MS
1418{
1419 int rc;
1420
1421 stp_page = alloc_bootmem_pages(PAGE_SIZE);
1422 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
4a672cfa 1423 if (rc == 0)
d2fec595
MS
1424 set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
1425 else if (stp_online) {
1426 printk(KERN_WARNING "Running on non STP capable machine.\n");
1427 free_bootmem((unsigned long) stp_page, PAGE_SIZE);
1428 stp_page = NULL;
1429 stp_online = 0;
1430 }
1431}
1432
1433static int __init stp_init(void)
1434{
750887de
HC
1435 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1436 return 0;
1437 time_init_wq();
1438 if (!stp_online)
1439 return 0;
1440 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1441 return 0;
1442}
1443
1444arch_initcall(stp_init);
1445
1446/*
1447 * STP timing alert. There are three causes:
1448 * 1) timing status change
1449 * 2) link availability change
1450 * 3) time control parameter change
1451 * In all three cases we are only interested in the clock source state.
1452 * If a STP clock source is now available use it.
1453 */
1454static void stp_timing_alert(struct stp_irq_parm *intparm)
1455{
1456 if (intparm->tsc || intparm->lac || intparm->tcpc)
750887de 1457 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1458}
1459
1460/*
1461 * STP sync check machine check. This is called when the timing state
1462 * changes from the synchronized state to the unsynchronized state.
1463 * After a STP sync check the clock is not in sync. The machine check
1464 * is broadcasted to all cpus at the same time.
1465 */
1466void stp_sync_check(void)
1467{
1468 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
1469 return;
1470 disable_sync_clock(NULL);
750887de 1471 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1472}
1473
1474/*
1475 * STP island condition machine check. This is called when an attached
1476 * server attempts to communicate over an STP link and the servers
1477 * have matching CTN ids and have a valid stratum-1 configuration
1478 * but the configurations do not match.
1479 */
1480void stp_island_check(void)
1481{
1482 if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
1483 return;
1484 disable_sync_clock(NULL);
750887de 1485 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1486}
1487
750887de
HC
1488
1489static int stp_sync_clock(void *data)
d2fec595 1490{
750887de 1491 static int first;
d2fec595 1492 unsigned long long old_clock, delta;
750887de 1493 struct clock_sync_data *stp_sync;
d2fec595
MS
1494 int rc;
1495
750887de 1496 stp_sync = data;
d2fec595 1497
750887de
HC
1498 if (xchg(&first, 1) == 1) {
1499 /* Slave */
1500 clock_sync_cpu(stp_sync);
1501 return 0;
1502 }
d2fec595 1503
750887de
HC
1504 /* Wait until all other cpus entered the sync function. */
1505 while (atomic_read(&stp_sync->cpus) != 0)
1506 cpu_relax();
d2fec595 1507
d2fec595
MS
1508 enable_sync_clock();
1509
1510 set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1511 if (test_and_clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
750887de 1512 queue_work(time_sync_wq, &etr_work);
d2fec595
MS
1513
1514 rc = 0;
1515 if (stp_info.todoff[0] || stp_info.todoff[1] ||
1516 stp_info.todoff[2] || stp_info.todoff[3] ||
1517 stp_info.tmd != 2) {
1518 old_clock = get_clock();
1519 rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
1520 if (rc == 0) {
1521 delta = adjust_time(old_clock, get_clock(), 0);
1522 fixup_clock_comparator(delta);
1523 rc = chsc_sstpi(stp_page, &stp_info,
1524 sizeof(struct stp_sstpi));
1525 if (rc == 0 && stp_info.tmd != 2)
1526 rc = -EAGAIN;
1527 }
1528 }
1529 if (rc) {
1530 disable_sync_clock(NULL);
750887de 1531 stp_sync->in_sync = -EAGAIN;
d2fec595
MS
1532 clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
1533 if (etr_port0_online || etr_port1_online)
750887de 1534 queue_work(time_sync_wq, &etr_work);
d2fec595 1535 } else
750887de
HC
1536 stp_sync->in_sync = 1;
1537 xchg(&first, 0);
1538 return 0;
1539}
d2fec595 1540
750887de
HC
1541/*
1542 * STP work. Check for the STP state and take over the clock
1543 * synchronization if the STP clock source is usable.
1544 */
1545static void stp_work_fn(struct work_struct *work)
1546{
1547 struct clock_sync_data stp_sync;
1548 int rc;
1549
0b3016b7
MS
1550 /* prevent multiple execution. */
1551 mutex_lock(&stp_work_mutex);
1552
750887de
HC
1553 if (!stp_online) {
1554 chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
0b3016b7 1555 goto out_unlock;
750887de
HC
1556 }
1557
1558 rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
1559 if (rc)
0b3016b7 1560 goto out_unlock;
750887de
HC
1561
1562 rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
1563 if (rc || stp_info.c == 0)
0b3016b7 1564 goto out_unlock;
750887de
HC
1565
1566 memset(&stp_sync, 0, sizeof(stp_sync));
1567 get_online_cpus();
1568 atomic_set(&stp_sync.cpus, num_online_cpus() - 1);
1569 stop_machine(stp_sync_clock, &stp_sync, &cpu_online_map);
1570 put_online_cpus();
0b3016b7
MS
1571
1572out_unlock:
1573 mutex_unlock(&stp_work_mutex);
d2fec595
MS
1574}
1575
1576/*
1577 * STP class sysfs interface functions
1578 */
1579static struct sysdev_class stp_sysclass = {
1580 .name = "stp",
1581};
1582
1583static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf)
1584{
1585 if (!stp_online)
1586 return -ENODATA;
1587 return sprintf(buf, "%016llx\n",
1588 *(unsigned long long *) stp_info.ctnid);
1589}
1590
1591static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
1592
1593static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf)
1594{
1595 if (!stp_online)
1596 return -ENODATA;
1597 return sprintf(buf, "%i\n", stp_info.ctn);
1598}
1599
1600static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
1601
1602static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf)
1603{
1604 if (!stp_online || !(stp_info.vbits & 0x2000))
1605 return -ENODATA;
1606 return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
1607}
1608
1609static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
1610
1611static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf)
1612{
1613 if (!stp_online || !(stp_info.vbits & 0x8000))
1614 return -ENODATA;
1615 return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
1616}
1617
1618static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
1619
1620static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf)
1621{
1622 if (!stp_online)
1623 return -ENODATA;
1624 return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
1625}
1626
1627static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL);
1628
1629static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf)
1630{
1631 if (!stp_online || !(stp_info.vbits & 0x0800))
1632 return -ENODATA;
1633 return sprintf(buf, "%i\n", (int) stp_info.tto);
1634}
1635
1636static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
1637
1638static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf)
1639{
1640 if (!stp_online || !(stp_info.vbits & 0x4000))
1641 return -ENODATA;
1642 return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
1643}
1644
1645static SYSDEV_CLASS_ATTR(time_zone_offset, 0400,
1646 stp_time_zone_offset_show, NULL);
1647
1648static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf)
1649{
1650 if (!stp_online)
1651 return -ENODATA;
1652 return sprintf(buf, "%i\n", stp_info.tmd);
1653}
1654
1655static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
1656
1657static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf)
1658{
1659 if (!stp_online)
1660 return -ENODATA;
1661 return sprintf(buf, "%i\n", stp_info.tst);
1662}
1663
1664static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
1665
1666static ssize_t stp_online_show(struct sysdev_class *class, char *buf)
1667{
1668 return sprintf(buf, "%i\n", stp_online);
1669}
1670
1671static ssize_t stp_online_store(struct sysdev_class *class,
1672 const char *buf, size_t count)
1673{
1674 unsigned int value;
1675
1676 value = simple_strtoul(buf, NULL, 0);
1677 if (value != 0 && value != 1)
1678 return -EINVAL;
1679 if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
1680 return -EOPNOTSUPP;
1681 stp_online = value;
750887de 1682 queue_work(time_sync_wq, &stp_work);
d2fec595
MS
1683 return count;
1684}
1685
1686/*
1687 * Can't use SYSDEV_CLASS_ATTR because the attribute should be named
1688 * stp/online but attr_online already exists in this file ..
1689 */
1690static struct sysdev_class_attribute attr_stp_online = {
1691 .attr = { .name = "online", .mode = 0600 },
1692 .show = stp_online_show,
1693 .store = stp_online_store,
1694};
1695
1696static struct sysdev_class_attribute *stp_attributes[] = {
1697 &attr_ctn_id,
1698 &attr_ctn_type,
1699 &attr_dst_offset,
1700 &attr_leap_seconds,
1701 &attr_stp_online,
1702 &attr_stratum,
1703 &attr_time_offset,
1704 &attr_time_zone_offset,
1705 &attr_timing_mode,
1706 &attr_timing_state,
1707 NULL
1708};
1709
1710static int __init stp_init_sysfs(void)
1711{
1712 struct sysdev_class_attribute **attr;
1713 int rc;
1714
1715 rc = sysdev_class_register(&stp_sysclass);
1716 if (rc)
1717 goto out;
1718 for (attr = stp_attributes; *attr; attr++) {
1719 rc = sysdev_class_create_file(&stp_sysclass, *attr);
1720 if (rc)
1721 goto out_unreg;
1722 }
1723 return 0;
1724out_unreg:
1725 for (; attr >= stp_attributes; attr--)
1726 sysdev_class_remove_file(&stp_sysclass, *attr);
1727 sysdev_class_unregister(&stp_sysclass);
1728out:
1729 return rc;
1730}
1731
1732device_initcall(stp_init_sysfs);
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