Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/time.c | |
3 | * Time of day based timer functions. | |
4 | * | |
5 | * S390 version | |
d2fec595 | 6 | * Copyright IBM Corp. 1999, 2008 |
1da177e4 LT |
7 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
8 | * Martin Schwidefsky (schwidefsky@de.ibm.com), | |
9 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) | |
10 | * | |
11 | * Derived from "arch/i386/kernel/time.c" | |
12 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
13 | */ | |
14 | ||
feab6501 MS |
15 | #define KMSG_COMPONENT "time" |
16 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
17 | ||
1da177e4 LT |
18 | #include <linux/errno.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/param.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/mm.h> | |
25 | #include <linux/interrupt.h> | |
750887de HC |
26 | #include <linux/cpu.h> |
27 | #include <linux/stop_machine.h> | |
1da177e4 | 28 | #include <linux/time.h> |
3367b994 | 29 | #include <linux/sysdev.h> |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/init.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/types.h> | |
34 | #include <linux/profile.h> | |
35 | #include <linux/timex.h> | |
36 | #include <linux/notifier.h> | |
dc64bef5 | 37 | #include <linux/clocksource.h> |
5a62b192 | 38 | #include <linux/clockchips.h> |
d2fec595 | 39 | #include <linux/bootmem.h> |
1da177e4 LT |
40 | #include <asm/uaccess.h> |
41 | #include <asm/delay.h> | |
42 | #include <asm/s390_ext.h> | |
43 | #include <asm/div64.h> | |
b020632e | 44 | #include <asm/vdso.h> |
1da177e4 | 45 | #include <asm/irq.h> |
5a489b98 | 46 | #include <asm/irq_regs.h> |
1da177e4 | 47 | #include <asm/timer.h> |
d54853ef | 48 | #include <asm/etr.h> |
a806170e | 49 | #include <asm/cio.h> |
1da177e4 LT |
50 | |
51 | /* change this if you have some constant time drift */ | |
52 | #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) | |
53 | #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) | |
54 | ||
d54853ef MS |
55 | /* The value of the TOD clock for 1.1.1970. */ |
56 | #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL | |
57 | ||
1da177e4 LT |
58 | /* |
59 | * Create a small time difference between the timer interrupts | |
60 | * on the different cpus to avoid lock contention. | |
61 | */ | |
62 | #define CPU_DEVIATION (smp_processor_id() << 12) | |
63 | ||
64 | #define TICK_SIZE tick | |
65 | ||
1da177e4 | 66 | static ext_int_info_t ext_int_info_cc; |
d54853ef | 67 | static ext_int_info_t ext_int_etr_cc; |
8107d829 | 68 | static u64 sched_clock_base_cc; |
5a62b192 HC |
69 | |
70 | static DEFINE_PER_CPU(struct clock_event_device, comparators); | |
1da177e4 | 71 | |
1da177e4 LT |
72 | /* |
73 | * Scheduler clock - returns current time in nanosec units. | |
74 | */ | |
75 | unsigned long long sched_clock(void) | |
76 | { | |
8107d829 | 77 | return ((get_clock_xt() - sched_clock_base_cc) * 125) >> 9; |
1da177e4 LT |
78 | } |
79 | ||
32f65f27 JG |
80 | /* |
81 | * Monotonic_clock - returns # of nanoseconds passed since time_init() | |
82 | */ | |
83 | unsigned long long monotonic_clock(void) | |
84 | { | |
85 | return sched_clock(); | |
86 | } | |
87 | EXPORT_SYMBOL(monotonic_clock); | |
88 | ||
1da177e4 LT |
89 | void tod_to_timeval(__u64 todval, struct timespec *xtime) |
90 | { | |
91 | unsigned long long sec; | |
92 | ||
93 | sec = todval >> 12; | |
94 | do_div(sec, 1000000); | |
95 | xtime->tv_sec = sec; | |
96 | todval -= (sec * 1000000) << 12; | |
97 | xtime->tv_nsec = ((todval * 1000) >> 12); | |
98 | } | |
99 | ||
1da177e4 | 100 | #ifdef CONFIG_PROFILING |
5a489b98 | 101 | #define s390_do_profile() profile_tick(CPU_PROFILING) |
1da177e4 | 102 | #else |
5a489b98 | 103 | #define s390_do_profile() do { ; } while(0) |
1da177e4 LT |
104 | #endif /* CONFIG_PROFILING */ |
105 | ||
5a62b192 | 106 | void clock_comparator_work(void) |
1da177e4 | 107 | { |
5a62b192 | 108 | struct clock_event_device *cd; |
1da177e4 | 109 | |
5a62b192 HC |
110 | S390_lowcore.clock_comparator = -1ULL; |
111 | set_clock_comparator(S390_lowcore.clock_comparator); | |
112 | cd = &__get_cpu_var(comparators); | |
113 | cd->event_handler(cd); | |
5a489b98 | 114 | s390_do_profile(); |
1da177e4 LT |
115 | } |
116 | ||
1da177e4 | 117 | /* |
5a62b192 | 118 | * Fixup the clock comparator. |
1da177e4 | 119 | */ |
5a62b192 | 120 | static void fixup_clock_comparator(unsigned long long delta) |
1da177e4 | 121 | { |
5a62b192 HC |
122 | /* If nobody is waiting there's nothing to fix. */ |
123 | if (S390_lowcore.clock_comparator == -1ULL) | |
1da177e4 | 124 | return; |
5a62b192 HC |
125 | S390_lowcore.clock_comparator += delta; |
126 | set_clock_comparator(S390_lowcore.clock_comparator); | |
1da177e4 LT |
127 | } |
128 | ||
5a62b192 HC |
129 | static int s390_next_event(unsigned long delta, |
130 | struct clock_event_device *evt) | |
1da177e4 | 131 | { |
5a62b192 HC |
132 | S390_lowcore.clock_comparator = get_clock() + delta; |
133 | set_clock_comparator(S390_lowcore.clock_comparator); | |
134 | return 0; | |
1da177e4 LT |
135 | } |
136 | ||
5a62b192 HC |
137 | static void s390_set_mode(enum clock_event_mode mode, |
138 | struct clock_event_device *evt) | |
1da177e4 | 139 | { |
d54853ef MS |
140 | } |
141 | ||
142 | /* | |
143 | * Set up lowcore and control register of the current cpu to | |
144 | * enable TOD clock and clock comparator interrupts. | |
1da177e4 LT |
145 | */ |
146 | void init_cpu_timer(void) | |
147 | { | |
5a62b192 HC |
148 | struct clock_event_device *cd; |
149 | int cpu; | |
150 | ||
151 | S390_lowcore.clock_comparator = -1ULL; | |
152 | set_clock_comparator(S390_lowcore.clock_comparator); | |
153 | ||
154 | cpu = smp_processor_id(); | |
155 | cd = &per_cpu(comparators, cpu); | |
156 | cd->name = "comparator"; | |
157 | cd->features = CLOCK_EVT_FEAT_ONESHOT; | |
158 | cd->mult = 16777; | |
159 | cd->shift = 12; | |
160 | cd->min_delta_ns = 1; | |
161 | cd->max_delta_ns = LONG_MAX; | |
162 | cd->rating = 400; | |
320ab2b0 | 163 | cd->cpumask = cpumask_of(cpu); |
5a62b192 HC |
164 | cd->set_next_event = s390_next_event; |
165 | cd->set_mode = s390_set_mode; | |
166 | ||
167 | clockevents_register_device(cd); | |
d54853ef MS |
168 | |
169 | /* Enable clock comparator timer interrupt. */ | |
170 | __ctl_set_bit(0,11); | |
171 | ||
d2fec595 | 172 | /* Always allow the timing alert external interrupt. */ |
d54853ef MS |
173 | __ctl_set_bit(0, 4); |
174 | } | |
175 | ||
176 | static void clock_comparator_interrupt(__u16 code) | |
177 | { | |
d3d238c7 HC |
178 | if (S390_lowcore.clock_comparator == -1ULL) |
179 | set_clock_comparator(S390_lowcore.clock_comparator); | |
d54853ef MS |
180 | } |
181 | ||
d2fec595 MS |
182 | static void etr_timing_alert(struct etr_irq_parm *); |
183 | static void stp_timing_alert(struct stp_irq_parm *); | |
184 | ||
185 | static void timing_alert_interrupt(__u16 code) | |
186 | { | |
187 | if (S390_lowcore.ext_params & 0x00c40000) | |
188 | etr_timing_alert((struct etr_irq_parm *) | |
189 | &S390_lowcore.ext_params); | |
190 | if (S390_lowcore.ext_params & 0x00038000) | |
191 | stp_timing_alert((struct stp_irq_parm *) | |
192 | &S390_lowcore.ext_params); | |
193 | } | |
194 | ||
d54853ef | 195 | static void etr_reset(void); |
d2fec595 | 196 | static void stp_reset(void); |
d54853ef MS |
197 | |
198 | /* | |
199 | * Get the TOD clock running. | |
200 | */ | |
201 | static u64 __init reset_tod_clock(void) | |
202 | { | |
203 | u64 time; | |
204 | ||
205 | etr_reset(); | |
d2fec595 | 206 | stp_reset(); |
d54853ef MS |
207 | if (store_clock(&time) == 0) |
208 | return time; | |
209 | /* TOD clock not running. Set the clock to Unix Epoch. */ | |
210 | if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0) | |
211 | panic("TOD clock not operational."); | |
1da177e4 | 212 | |
d54853ef | 213 | return TOD_UNIX_EPOCH; |
1da177e4 LT |
214 | } |
215 | ||
dc64bef5 MS |
216 | static cycle_t read_tod_clock(void) |
217 | { | |
218 | return get_clock(); | |
219 | } | |
220 | ||
221 | static struct clocksource clocksource_tod = { | |
222 | .name = "tod", | |
d2cb0e6e | 223 | .rating = 400, |
dc64bef5 MS |
224 | .read = read_tod_clock, |
225 | .mask = -1ULL, | |
226 | .mult = 1000, | |
227 | .shift = 12, | |
cc02d809 | 228 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
dc64bef5 MS |
229 | }; |
230 | ||
231 | ||
b020632e MS |
232 | void update_vsyscall(struct timespec *wall_time, struct clocksource *clock) |
233 | { | |
234 | if (clock != &clocksource_tod) | |
235 | return; | |
236 | ||
237 | /* Make userspace gettimeofday spin until we're done. */ | |
238 | ++vdso_data->tb_update_count; | |
239 | smp_wmb(); | |
240 | vdso_data->xtime_tod_stamp = clock->cycle_last; | |
241 | vdso_data->xtime_clock_sec = xtime.tv_sec; | |
242 | vdso_data->xtime_clock_nsec = xtime.tv_nsec; | |
243 | vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec; | |
244 | vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec; | |
245 | smp_wmb(); | |
246 | ++vdso_data->tb_update_count; | |
247 | } | |
248 | ||
249 | extern struct timezone sys_tz; | |
250 | ||
251 | void update_vsyscall_tz(void) | |
252 | { | |
253 | /* Make userspace gettimeofday spin until we're done. */ | |
254 | ++vdso_data->tb_update_count; | |
255 | smp_wmb(); | |
256 | vdso_data->tz_minuteswest = sys_tz.tz_minuteswest; | |
257 | vdso_data->tz_dsttime = sys_tz.tz_dsttime; | |
258 | smp_wmb(); | |
259 | ++vdso_data->tb_update_count; | |
260 | } | |
261 | ||
1da177e4 LT |
262 | /* |
263 | * Initialize the TOD clock and the CPU timer of | |
264 | * the boot cpu. | |
265 | */ | |
266 | void __init time_init(void) | |
267 | { | |
8107d829 | 268 | sched_clock_base_cc = reset_tod_clock(); |
1da177e4 LT |
269 | |
270 | /* set xtime */ | |
8107d829 | 271 | tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, &xtime); |
1da177e4 LT |
272 | set_normalized_timespec(&wall_to_monotonic, |
273 | -xtime.tv_sec, -xtime.tv_nsec); | |
274 | ||
275 | /* request the clock comparator external interrupt */ | |
d54853ef MS |
276 | if (register_early_external_interrupt(0x1004, |
277 | clock_comparator_interrupt, | |
1da177e4 LT |
278 | &ext_int_info_cc) != 0) |
279 | panic("Couldn't request external interrupt 0x1004"); | |
280 | ||
dc64bef5 MS |
281 | if (clocksource_register(&clocksource_tod) != 0) |
282 | panic("Could not register TOD clock source"); | |
283 | ||
d2fec595 MS |
284 | /* request the timing alert external interrupt */ |
285 | if (register_early_external_interrupt(0x1406, | |
286 | timing_alert_interrupt, | |
d54853ef MS |
287 | &ext_int_etr_cc) != 0) |
288 | panic("Couldn't request external interrupt 0x1406"); | |
289 | ||
290 | /* Enable TOD clock interrupts on the boot cpu. */ | |
291 | init_cpu_timer(); | |
c185b783 | 292 | /* Enable cpu timer interrupts on the boot cpu. */ |
1da177e4 | 293 | vtime_init(); |
d54853ef MS |
294 | } |
295 | ||
d2fec595 MS |
296 | /* |
297 | * The time is "clock". old is what we think the time is. | |
298 | * Adjust the value by a multiple of jiffies and add the delta to ntp. | |
299 | * "delay" is an approximation how long the synchronization took. If | |
300 | * the time correction is positive, then "delay" is subtracted from | |
301 | * the time difference and only the remaining part is passed to ntp. | |
302 | */ | |
303 | static unsigned long long adjust_time(unsigned long long old, | |
304 | unsigned long long clock, | |
305 | unsigned long long delay) | |
306 | { | |
307 | unsigned long long delta, ticks; | |
308 | struct timex adjust; | |
309 | ||
310 | if (clock > old) { | |
311 | /* It is later than we thought. */ | |
312 | delta = ticks = clock - old; | |
313 | delta = ticks = (delta < delay) ? 0 : delta - delay; | |
314 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
315 | adjust.offset = ticks * (1000000 / HZ); | |
316 | } else { | |
317 | /* It is earlier than we thought. */ | |
318 | delta = ticks = old - clock; | |
319 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
320 | delta = -delta; | |
321 | adjust.offset = -ticks * (1000000 / HZ); | |
322 | } | |
8107d829 | 323 | sched_clock_base_cc += delta; |
d2fec595 | 324 | if (adjust.offset != 0) { |
feab6501 MS |
325 | pr_notice("The ETR interface has adjusted the clock " |
326 | "by %li microseconds\n", adjust.offset); | |
d2fec595 MS |
327 | adjust.modes = ADJ_OFFSET_SINGLESHOT; |
328 | do_adjtimex(&adjust); | |
329 | } | |
330 | return delta; | |
331 | } | |
332 | ||
333 | static DEFINE_PER_CPU(atomic_t, clock_sync_word); | |
334 | static unsigned long clock_sync_flags; | |
335 | ||
336 | #define CLOCK_SYNC_HAS_ETR 0 | |
337 | #define CLOCK_SYNC_HAS_STP 1 | |
338 | #define CLOCK_SYNC_ETR 2 | |
339 | #define CLOCK_SYNC_STP 3 | |
340 | ||
341 | /* | |
342 | * The synchronous get_clock function. It will write the current clock | |
343 | * value to the clock pointer and return 0 if the clock is in sync with | |
344 | * the external time source. If the clock mode is local it will return | |
345 | * -ENOSYS and -EAGAIN if the clock is not in sync with the external | |
346 | * reference. | |
347 | */ | |
348 | int get_sync_clock(unsigned long long *clock) | |
349 | { | |
350 | atomic_t *sw_ptr; | |
351 | unsigned int sw0, sw1; | |
352 | ||
353 | sw_ptr = &get_cpu_var(clock_sync_word); | |
354 | sw0 = atomic_read(sw_ptr); | |
355 | *clock = get_clock(); | |
356 | sw1 = atomic_read(sw_ptr); | |
357 | put_cpu_var(clock_sync_sync); | |
358 | if (sw0 == sw1 && (sw0 & 0x80000000U)) | |
359 | /* Success: time is in sync. */ | |
360 | return 0; | |
361 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) && | |
362 | !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
363 | return -ENOSYS; | |
364 | if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) && | |
365 | !test_bit(CLOCK_SYNC_STP, &clock_sync_flags)) | |
366 | return -EACCES; | |
367 | return -EAGAIN; | |
368 | } | |
369 | EXPORT_SYMBOL(get_sync_clock); | |
370 | ||
371 | /* | |
372 | * Make get_sync_clock return -EAGAIN. | |
373 | */ | |
374 | static void disable_sync_clock(void *dummy) | |
375 | { | |
376 | atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word); | |
377 | /* | |
378 | * Clear the in-sync bit 2^31. All get_sync_clock calls will | |
379 | * fail until the sync bit is turned back on. In addition | |
380 | * increase the "sequence" counter to avoid the race of an | |
381 | * etr event and the complete recovery against get_sync_clock. | |
382 | */ | |
383 | atomic_clear_mask(0x80000000, sw_ptr); | |
384 | atomic_inc(sw_ptr); | |
385 | } | |
386 | ||
387 | /* | |
388 | * Make get_sync_clock return 0 again. | |
389 | * Needs to be called from a context disabled for preemption. | |
390 | */ | |
391 | static void enable_sync_clock(void) | |
392 | { | |
393 | atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word); | |
394 | atomic_set_mask(0x80000000, sw_ptr); | |
395 | } | |
396 | ||
750887de HC |
397 | /* Single threaded workqueue used for etr and stp sync events */ |
398 | static struct workqueue_struct *time_sync_wq; | |
399 | ||
400 | static void __init time_init_wq(void) | |
401 | { | |
179cb81a HC |
402 | if (time_sync_wq) |
403 | return; | |
404 | time_sync_wq = create_singlethread_workqueue("timesync"); | |
405 | stop_machine_create(); | |
750887de HC |
406 | } |
407 | ||
d54853ef MS |
408 | /* |
409 | * External Time Reference (ETR) code. | |
410 | */ | |
411 | static int etr_port0_online; | |
412 | static int etr_port1_online; | |
d2fec595 | 413 | static int etr_steai_available; |
d54853ef MS |
414 | |
415 | static int __init early_parse_etr(char *p) | |
416 | { | |
417 | if (strncmp(p, "off", 3) == 0) | |
418 | etr_port0_online = etr_port1_online = 0; | |
419 | else if (strncmp(p, "port0", 5) == 0) | |
420 | etr_port0_online = 1; | |
421 | else if (strncmp(p, "port1", 5) == 0) | |
422 | etr_port1_online = 1; | |
423 | else if (strncmp(p, "on", 2) == 0) | |
424 | etr_port0_online = etr_port1_online = 1; | |
425 | return 0; | |
426 | } | |
427 | early_param("etr", early_parse_etr); | |
428 | ||
429 | enum etr_event { | |
430 | ETR_EVENT_PORT0_CHANGE, | |
431 | ETR_EVENT_PORT1_CHANGE, | |
432 | ETR_EVENT_PORT_ALERT, | |
433 | ETR_EVENT_SYNC_CHECK, | |
434 | ETR_EVENT_SWITCH_LOCAL, | |
435 | ETR_EVENT_UPDATE, | |
436 | }; | |
437 | ||
d54853ef MS |
438 | /* |
439 | * Valid bit combinations of the eacr register are (x = don't care): | |
440 | * e0 e1 dp p0 p1 ea es sl | |
441 | * 0 0 x 0 0 0 0 0 initial, disabled state | |
442 | * 0 0 x 0 1 1 0 0 port 1 online | |
443 | * 0 0 x 1 0 1 0 0 port 0 online | |
444 | * 0 0 x 1 1 1 0 0 both ports online | |
445 | * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode | |
446 | * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode | |
447 | * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync | |
448 | * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync | |
449 | * 0 1 x 1 1 1 0 0 both ports online, port 1 usable | |
450 | * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync | |
451 | * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync | |
452 | * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode | |
453 | * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode | |
454 | * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync | |
455 | * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync | |
456 | * 1 0 x 1 1 1 0 0 both ports online, port 0 usable | |
457 | * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync | |
458 | * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync | |
459 | * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync | |
460 | * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync | |
461 | */ | |
462 | static struct etr_eacr etr_eacr; | |
463 | static u64 etr_tolec; /* time of last eacr update */ | |
d54853ef MS |
464 | static struct etr_aib etr_port0; |
465 | static int etr_port0_uptodate; | |
466 | static struct etr_aib etr_port1; | |
467 | static int etr_port1_uptodate; | |
468 | static unsigned long etr_events; | |
469 | static struct timer_list etr_timer; | |
d54853ef MS |
470 | |
471 | static void etr_timeout(unsigned long dummy); | |
ecdcc023 | 472 | static void etr_work_fn(struct work_struct *work); |
0b3016b7 | 473 | static DEFINE_MUTEX(etr_work_mutex); |
ecdcc023 | 474 | static DECLARE_WORK(etr_work, etr_work_fn); |
d54853ef | 475 | |
d54853ef MS |
476 | /* |
477 | * Reset ETR attachment. | |
478 | */ | |
479 | static void etr_reset(void) | |
480 | { | |
481 | etr_eacr = (struct etr_eacr) { | |
482 | .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, | |
483 | .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, | |
484 | .es = 0, .sl = 0 }; | |
d2fec595 | 485 | if (etr_setr(&etr_eacr) == 0) { |
d54853ef | 486 | etr_tolec = get_clock(); |
d2fec595 MS |
487 | set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags); |
488 | } else if (etr_port0_online || etr_port1_online) { | |
feab6501 MS |
489 | pr_warning("The real or virtual hardware system does " |
490 | "not provide an ETR interface\n"); | |
d2fec595 | 491 | etr_port0_online = etr_port1_online = 0; |
d54853ef MS |
492 | } |
493 | } | |
494 | ||
ecdcc023 | 495 | static int __init etr_init(void) |
d54853ef MS |
496 | { |
497 | struct etr_aib aib; | |
498 | ||
d2fec595 | 499 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
ecdcc023 | 500 | return 0; |
750887de | 501 | time_init_wq(); |
d54853ef MS |
502 | /* Check if this machine has the steai instruction. */ |
503 | if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) | |
d2fec595 | 504 | etr_steai_available = 1; |
d54853ef | 505 | setup_timer(&etr_timer, etr_timeout, 0UL); |
d54853ef MS |
506 | if (etr_port0_online) { |
507 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
750887de | 508 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
509 | } |
510 | if (etr_port1_online) { | |
511 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
750887de | 512 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 513 | } |
ecdcc023 | 514 | return 0; |
d54853ef MS |
515 | } |
516 | ||
ecdcc023 MS |
517 | arch_initcall(etr_init); |
518 | ||
d54853ef MS |
519 | /* |
520 | * Two sorts of ETR machine checks. The architecture reads: | |
521 | * "When a machine-check niterruption occurs and if a switch-to-local or | |
522 | * ETR-sync-check interrupt request is pending but disabled, this pending | |
523 | * disabled interruption request is indicated and is cleared". | |
524 | * Which means that we can get etr_switch_to_local events from the machine | |
525 | * check handler although the interruption condition is disabled. Lovely.. | |
526 | */ | |
527 | ||
528 | /* | |
529 | * Switch to local machine check. This is called when the last usable | |
530 | * ETR port goes inactive. After switch to local the clock is not in sync. | |
531 | */ | |
532 | void etr_switch_to_local(void) | |
533 | { | |
534 | if (!etr_eacr.sl) | |
535 | return; | |
d2fec595 MS |
536 | if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags)) |
537 | disable_sync_clock(NULL); | |
d54853ef | 538 | set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events); |
750887de | 539 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
540 | } |
541 | ||
542 | /* | |
543 | * ETR sync check machine check. This is called when the ETR OTE and the | |
544 | * local clock OTE are farther apart than the ETR sync check tolerance. | |
545 | * After a ETR sync check the clock is not in sync. The machine check | |
546 | * is broadcasted to all cpus at the same time. | |
547 | */ | |
548 | void etr_sync_check(void) | |
549 | { | |
550 | if (!etr_eacr.es) | |
551 | return; | |
d2fec595 MS |
552 | if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags)) |
553 | disable_sync_clock(NULL); | |
d54853ef | 554 | set_bit(ETR_EVENT_SYNC_CHECK, &etr_events); |
750887de | 555 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
556 | } |
557 | ||
558 | /* | |
d2fec595 | 559 | * ETR timing alert. There are two causes: |
d54853ef MS |
560 | * 1) port state change, check the usability of the port |
561 | * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the | |
562 | * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) | |
563 | * or ETR-data word 4 (edf4) has changed. | |
564 | */ | |
d2fec595 | 565 | static void etr_timing_alert(struct etr_irq_parm *intparm) |
d54853ef | 566 | { |
d54853ef MS |
567 | if (intparm->pc0) |
568 | /* ETR port 0 state change. */ | |
569 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
570 | if (intparm->pc1) | |
571 | /* ETR port 1 state change. */ | |
572 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
573 | if (intparm->eai) | |
574 | /* | |
575 | * ETR port alert on either port 0, 1 or both. | |
576 | * Both ports are not up-to-date now. | |
577 | */ | |
578 | set_bit(ETR_EVENT_PORT_ALERT, &etr_events); | |
750887de | 579 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
580 | } |
581 | ||
582 | static void etr_timeout(unsigned long dummy) | |
583 | { | |
584 | set_bit(ETR_EVENT_UPDATE, &etr_events); | |
750887de | 585 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
586 | } |
587 | ||
588 | /* | |
589 | * Check if the etr mode is pss. | |
590 | */ | |
591 | static inline int etr_mode_is_pps(struct etr_eacr eacr) | |
592 | { | |
593 | return eacr.es && !eacr.sl; | |
594 | } | |
595 | ||
596 | /* | |
597 | * Check if the etr mode is etr. | |
598 | */ | |
599 | static inline int etr_mode_is_etr(struct etr_eacr eacr) | |
600 | { | |
601 | return eacr.es && eacr.sl; | |
602 | } | |
603 | ||
604 | /* | |
605 | * Check if the port can be used for TOD synchronization. | |
606 | * For PPS mode the port has to receive OTEs. For ETR mode | |
607 | * the port has to receive OTEs, the ETR stepping bit has to | |
608 | * be zero and the validity bits for data frame 1, 2, and 3 | |
609 | * have to be 1. | |
610 | */ | |
611 | static int etr_port_valid(struct etr_aib *aib, int port) | |
612 | { | |
613 | unsigned int psc; | |
614 | ||
615 | /* Check that this port is receiving OTEs. */ | |
616 | if (aib->tsp == 0) | |
617 | return 0; | |
618 | ||
619 | psc = port ? aib->esw.psc1 : aib->esw.psc0; | |
620 | if (psc == etr_lpsc_pps_mode) | |
621 | return 1; | |
622 | if (psc == etr_lpsc_operational_step) | |
623 | return !aib->esw.y && aib->slsw.v1 && | |
624 | aib->slsw.v2 && aib->slsw.v3; | |
625 | return 0; | |
626 | } | |
627 | ||
628 | /* | |
629 | * Check if two ports are on the same network. | |
630 | */ | |
631 | static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) | |
632 | { | |
633 | // FIXME: any other fields we have to compare? | |
634 | return aib1->edf1.net_id == aib2->edf1.net_id; | |
635 | } | |
636 | ||
637 | /* | |
638 | * Wrapper for etr_stei that converts physical port states | |
639 | * to logical port states to be consistent with the output | |
640 | * of stetr (see etr_psc vs. etr_lpsc). | |
641 | */ | |
642 | static void etr_steai_cv(struct etr_aib *aib, unsigned int func) | |
643 | { | |
644 | BUG_ON(etr_steai(aib, func) != 0); | |
645 | /* Convert port state to logical port state. */ | |
646 | if (aib->esw.psc0 == 1) | |
647 | aib->esw.psc0 = 2; | |
648 | else if (aib->esw.psc0 == 0 && aib->esw.p == 0) | |
649 | aib->esw.psc0 = 1; | |
650 | if (aib->esw.psc1 == 1) | |
651 | aib->esw.psc1 = 2; | |
652 | else if (aib->esw.psc1 == 0 && aib->esw.p == 1) | |
653 | aib->esw.psc1 = 1; | |
654 | } | |
655 | ||
656 | /* | |
657 | * Check if the aib a2 is still connected to the same attachment as | |
658 | * aib a1, the etv values differ by one and a2 is valid. | |
659 | */ | |
660 | static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) | |
661 | { | |
662 | int state_a1, state_a2; | |
663 | ||
664 | /* Paranoia check: e0/e1 should better be the same. */ | |
665 | if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || | |
666 | a1->esw.eacr.e1 != a2->esw.eacr.e1) | |
667 | return 0; | |
668 | ||
669 | /* Still connected to the same etr ? */ | |
670 | state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; | |
671 | state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; | |
672 | if (state_a1 == etr_lpsc_operational_step) { | |
673 | if (state_a2 != etr_lpsc_operational_step || | |
674 | a1->edf1.net_id != a2->edf1.net_id || | |
675 | a1->edf1.etr_id != a2->edf1.etr_id || | |
676 | a1->edf1.etr_pn != a2->edf1.etr_pn) | |
677 | return 0; | |
678 | } else if (state_a2 != etr_lpsc_pps_mode) | |
679 | return 0; | |
680 | ||
681 | /* The ETV value of a2 needs to be ETV of a1 + 1. */ | |
682 | if (a1->edf2.etv + 1 != a2->edf2.etv) | |
683 | return 0; | |
684 | ||
685 | if (!etr_port_valid(a2, p)) | |
686 | return 0; | |
687 | ||
688 | return 1; | |
689 | } | |
690 | ||
d2fec595 | 691 | struct clock_sync_data { |
750887de | 692 | atomic_t cpus; |
5a62b192 HC |
693 | int in_sync; |
694 | unsigned long long fixup_cc; | |
750887de HC |
695 | int etr_port; |
696 | struct etr_aib *etr_aib; | |
d2fec595 | 697 | }; |
5a62b192 | 698 | |
750887de | 699 | static void clock_sync_cpu(struct clock_sync_data *sync) |
d54853ef | 700 | { |
750887de | 701 | atomic_dec(&sync->cpus); |
d2fec595 | 702 | enable_sync_clock(); |
d54853ef MS |
703 | /* |
704 | * This looks like a busy wait loop but it isn't. etr_sync_cpus | |
705 | * is called on all other cpus while the TOD clocks is stopped. | |
706 | * __udelay will stop the cpu on an enabled wait psw until the | |
707 | * TOD is running again. | |
708 | */ | |
d2fec595 | 709 | while (sync->in_sync == 0) { |
d54853ef | 710 | __udelay(1); |
6c732de2 HC |
711 | /* |
712 | * A different cpu changes *in_sync. Therefore use | |
713 | * barrier() to force memory access. | |
714 | */ | |
715 | barrier(); | |
716 | } | |
d2fec595 | 717 | if (sync->in_sync != 1) |
d54853ef | 718 | /* Didn't work. Clear per-cpu in sync bit again. */ |
d2fec595 | 719 | disable_sync_clock(NULL); |
d54853ef MS |
720 | /* |
721 | * This round of TOD syncing is done. Set the clock comparator | |
722 | * to the next tick and let the processor continue. | |
723 | */ | |
d2fec595 | 724 | fixup_clock_comparator(sync->fixup_cc); |
d54853ef MS |
725 | } |
726 | ||
d54853ef MS |
727 | /* |
728 | * Sync the TOD clock using the port refered to by aibp. This port | |
729 | * has to be enabled and the other port has to be disabled. The | |
730 | * last eacr update has to be more than 1.6 seconds in the past. | |
731 | */ | |
750887de | 732 | static int etr_sync_clock(void *data) |
d54853ef | 733 | { |
750887de | 734 | static int first; |
5a62b192 | 735 | unsigned long long clock, old_clock, delay, delta; |
750887de HC |
736 | struct clock_sync_data *etr_sync; |
737 | struct etr_aib *sync_port, *aib; | |
738 | int port; | |
d54853ef MS |
739 | int rc; |
740 | ||
750887de | 741 | etr_sync = data; |
d54853ef | 742 | |
750887de HC |
743 | if (xchg(&first, 1) == 1) { |
744 | /* Slave */ | |
745 | clock_sync_cpu(etr_sync); | |
746 | return 0; | |
747 | } | |
748 | ||
749 | /* Wait until all other cpus entered the sync function. */ | |
750 | while (atomic_read(&etr_sync->cpus) != 0) | |
751 | cpu_relax(); | |
752 | ||
753 | port = etr_sync->etr_port; | |
754 | aib = etr_sync->etr_aib; | |
755 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
d2fec595 | 756 | enable_sync_clock(); |
d54853ef MS |
757 | |
758 | /* Set clock to next OTE. */ | |
759 | __ctl_set_bit(14, 21); | |
760 | __ctl_set_bit(0, 29); | |
761 | clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; | |
5a62b192 | 762 | old_clock = get_clock(); |
d54853ef MS |
763 | if (set_clock(clock) == 0) { |
764 | __udelay(1); /* Wait for the clock to start. */ | |
765 | __ctl_clear_bit(0, 29); | |
766 | __ctl_clear_bit(14, 21); | |
767 | etr_stetr(aib); | |
768 | /* Adjust Linux timing variables. */ | |
769 | delay = (unsigned long long) | |
770 | (aib->edf2.etv - sync_port->edf2.etv) << 32; | |
d2fec595 | 771 | delta = adjust_time(old_clock, clock, delay); |
750887de | 772 | etr_sync->fixup_cc = delta; |
5a62b192 | 773 | fixup_clock_comparator(delta); |
d54853ef MS |
774 | /* Verify that the clock is properly set. */ |
775 | if (!etr_aib_follows(sync_port, aib, port)) { | |
776 | /* Didn't work. */ | |
d2fec595 | 777 | disable_sync_clock(NULL); |
750887de | 778 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
779 | rc = -EAGAIN; |
780 | } else { | |
750887de | 781 | etr_sync->in_sync = 1; |
d54853ef MS |
782 | rc = 0; |
783 | } | |
784 | } else { | |
785 | /* Could not set the clock ?!? */ | |
786 | __ctl_clear_bit(0, 29); | |
787 | __ctl_clear_bit(14, 21); | |
d2fec595 | 788 | disable_sync_clock(NULL); |
750887de | 789 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
790 | rc = -EAGAIN; |
791 | } | |
750887de HC |
792 | xchg(&first, 0); |
793 | return rc; | |
794 | } | |
795 | ||
796 | static int etr_sync_clock_stop(struct etr_aib *aib, int port) | |
797 | { | |
798 | struct clock_sync_data etr_sync; | |
799 | struct etr_aib *sync_port; | |
800 | int follows; | |
801 | int rc; | |
802 | ||
803 | /* Check if the current aib is adjacent to the sync port aib. */ | |
804 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
805 | follows = etr_aib_follows(sync_port, aib, port); | |
806 | memcpy(sync_port, aib, sizeof(*aib)); | |
807 | if (!follows) | |
808 | return -EAGAIN; | |
809 | memset(&etr_sync, 0, sizeof(etr_sync)); | |
810 | etr_sync.etr_aib = aib; | |
811 | etr_sync.etr_port = port; | |
812 | get_online_cpus(); | |
813 | atomic_set(&etr_sync.cpus, num_online_cpus() - 1); | |
814 | rc = stop_machine(etr_sync_clock, &etr_sync, &cpu_online_map); | |
815 | put_online_cpus(); | |
d54853ef MS |
816 | return rc; |
817 | } | |
818 | ||
819 | /* | |
820 | * Handle the immediate effects of the different events. | |
821 | * The port change event is used for online/offline changes. | |
822 | */ | |
823 | static struct etr_eacr etr_handle_events(struct etr_eacr eacr) | |
824 | { | |
825 | if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) | |
826 | eacr.es = 0; | |
827 | if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) | |
828 | eacr.es = eacr.sl = 0; | |
829 | if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) | |
830 | etr_port0_uptodate = etr_port1_uptodate = 0; | |
831 | ||
832 | if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { | |
833 | if (eacr.e0) | |
834 | /* | |
835 | * Port change of an enabled port. We have to | |
836 | * assume that this can have caused an stepping | |
837 | * port switch. | |
838 | */ | |
839 | etr_tolec = get_clock(); | |
840 | eacr.p0 = etr_port0_online; | |
841 | if (!eacr.p0) | |
842 | eacr.e0 = 0; | |
843 | etr_port0_uptodate = 0; | |
844 | } | |
845 | if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { | |
846 | if (eacr.e1) | |
847 | /* | |
848 | * Port change of an enabled port. We have to | |
849 | * assume that this can have caused an stepping | |
850 | * port switch. | |
851 | */ | |
852 | etr_tolec = get_clock(); | |
853 | eacr.p1 = etr_port1_online; | |
854 | if (!eacr.p1) | |
855 | eacr.e1 = 0; | |
856 | etr_port1_uptodate = 0; | |
857 | } | |
858 | clear_bit(ETR_EVENT_UPDATE, &etr_events); | |
859 | return eacr; | |
860 | } | |
861 | ||
862 | /* | |
863 | * Set up a timer that expires after the etr_tolec + 1.6 seconds if | |
864 | * one of the ports needs an update. | |
865 | */ | |
866 | static void etr_set_tolec_timeout(unsigned long long now) | |
867 | { | |
868 | unsigned long micros; | |
869 | ||
870 | if ((!etr_eacr.p0 || etr_port0_uptodate) && | |
871 | (!etr_eacr.p1 || etr_port1_uptodate)) | |
872 | return; | |
873 | micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; | |
874 | micros = (micros > 1600000) ? 0 : 1600000 - micros; | |
875 | mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); | |
876 | } | |
877 | ||
878 | /* | |
879 | * Set up a time that expires after 1/2 second. | |
880 | */ | |
881 | static void etr_set_sync_timeout(void) | |
882 | { | |
883 | mod_timer(&etr_timer, jiffies + HZ/2); | |
884 | } | |
885 | ||
886 | /* | |
887 | * Update the aib information for one or both ports. | |
888 | */ | |
889 | static struct etr_eacr etr_handle_update(struct etr_aib *aib, | |
890 | struct etr_eacr eacr) | |
891 | { | |
892 | /* With both ports disabled the aib information is useless. */ | |
893 | if (!eacr.e0 && !eacr.e1) | |
894 | return eacr; | |
895 | ||
ecdcc023 | 896 | /* Update port0 or port1 with aib stored in etr_work_fn. */ |
d54853ef MS |
897 | if (aib->esw.q == 0) { |
898 | /* Information for port 0 stored. */ | |
899 | if (eacr.p0 && !etr_port0_uptodate) { | |
900 | etr_port0 = *aib; | |
901 | if (etr_port0_online) | |
902 | etr_port0_uptodate = 1; | |
903 | } | |
904 | } else { | |
905 | /* Information for port 1 stored. */ | |
906 | if (eacr.p1 && !etr_port1_uptodate) { | |
907 | etr_port1 = *aib; | |
908 | if (etr_port0_online) | |
909 | etr_port1_uptodate = 1; | |
910 | } | |
911 | } | |
912 | ||
913 | /* | |
914 | * Do not try to get the alternate port aib if the clock | |
915 | * is not in sync yet. | |
916 | */ | |
d2fec595 | 917 | if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags) && !eacr.es) |
d54853ef MS |
918 | return eacr; |
919 | ||
920 | /* | |
921 | * If steai is available we can get the information about | |
922 | * the other port immediately. If only stetr is available the | |
923 | * data-port bit toggle has to be used. | |
924 | */ | |
d2fec595 | 925 | if (etr_steai_available) { |
d54853ef MS |
926 | if (eacr.p0 && !etr_port0_uptodate) { |
927 | etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); | |
928 | etr_port0_uptodate = 1; | |
929 | } | |
930 | if (eacr.p1 && !etr_port1_uptodate) { | |
931 | etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); | |
932 | etr_port1_uptodate = 1; | |
933 | } | |
934 | } else { | |
935 | /* | |
936 | * One port was updated above, if the other | |
937 | * port is not uptodate toggle dp bit. | |
938 | */ | |
939 | if ((eacr.p0 && !etr_port0_uptodate) || | |
940 | (eacr.p1 && !etr_port1_uptodate)) | |
941 | eacr.dp ^= 1; | |
942 | else | |
943 | eacr.dp = 0; | |
944 | } | |
945 | return eacr; | |
946 | } | |
947 | ||
948 | /* | |
949 | * Write new etr control register if it differs from the current one. | |
950 | * Return 1 if etr_tolec has been updated as well. | |
951 | */ | |
952 | static void etr_update_eacr(struct etr_eacr eacr) | |
953 | { | |
954 | int dp_changed; | |
955 | ||
956 | if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) | |
957 | /* No change, return. */ | |
958 | return; | |
959 | /* | |
960 | * The disable of an active port of the change of the data port | |
961 | * bit can/will cause a change in the data port. | |
962 | */ | |
963 | dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || | |
964 | (etr_eacr.dp ^ eacr.dp) != 0; | |
965 | etr_eacr = eacr; | |
966 | etr_setr(&etr_eacr); | |
967 | if (dp_changed) | |
968 | etr_tolec = get_clock(); | |
969 | } | |
970 | ||
971 | /* | |
750887de | 972 | * ETR work. In this function you'll find the main logic. In |
d54853ef MS |
973 | * particular this is the only function that calls etr_update_eacr(), |
974 | * it "controls" the etr control register. | |
975 | */ | |
ecdcc023 | 976 | static void etr_work_fn(struct work_struct *work) |
d54853ef MS |
977 | { |
978 | unsigned long long now; | |
979 | struct etr_eacr eacr; | |
980 | struct etr_aib aib; | |
981 | int sync_port; | |
982 | ||
0b3016b7 MS |
983 | /* prevent multiple execution. */ |
984 | mutex_lock(&etr_work_mutex); | |
985 | ||
d54853ef MS |
986 | /* Create working copy of etr_eacr. */ |
987 | eacr = etr_eacr; | |
988 | ||
989 | /* Check for the different events and their immediate effects. */ | |
990 | eacr = etr_handle_events(eacr); | |
991 | ||
992 | /* Check if ETR is supposed to be active. */ | |
993 | eacr.ea = eacr.p0 || eacr.p1; | |
994 | if (!eacr.ea) { | |
995 | /* Both ports offline. Reset everything. */ | |
996 | eacr.dp = eacr.es = eacr.sl = 0; | |
1a781a77 | 997 | on_each_cpu(disable_sync_clock, NULL, 1); |
d54853ef MS |
998 | del_timer_sync(&etr_timer); |
999 | etr_update_eacr(eacr); | |
d2fec595 | 1000 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); |
0b3016b7 | 1001 | goto out_unlock; |
d54853ef MS |
1002 | } |
1003 | ||
1004 | /* Store aib to get the current ETR status word. */ | |
1005 | BUG_ON(etr_stetr(&aib) != 0); | |
1006 | etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ | |
1007 | now = get_clock(); | |
1008 | ||
1009 | /* | |
1010 | * Update the port information if the last stepping port change | |
1011 | * or data port change is older than 1.6 seconds. | |
1012 | */ | |
1013 | if (now >= etr_tolec + (1600000 << 12)) | |
1014 | eacr = etr_handle_update(&aib, eacr); | |
1015 | ||
1016 | /* | |
1017 | * Select ports to enable. The prefered synchronization mode is PPS. | |
1018 | * If a port can be enabled depends on a number of things: | |
1019 | * 1) The port needs to be online and uptodate. A port is not | |
1020 | * disabled just because it is not uptodate, but it is only | |
1021 | * enabled if it is uptodate. | |
1022 | * 2) The port needs to have the same mode (pps / etr). | |
1023 | * 3) The port needs to be usable -> etr_port_valid() == 1 | |
1024 | * 4) To enable the second port the clock needs to be in sync. | |
1025 | * 5) If both ports are useable and are ETR ports, the network id | |
1026 | * has to be the same. | |
1027 | * The eacr.sl bit is used to indicate etr mode vs. pps mode. | |
1028 | */ | |
1029 | if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { | |
1030 | eacr.sl = 0; | |
1031 | eacr.e0 = 1; | |
1032 | if (!etr_mode_is_pps(etr_eacr)) | |
1033 | eacr.es = 0; | |
1034 | if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) | |
1035 | eacr.e1 = 0; | |
1036 | // FIXME: uptodate checks ? | |
1037 | else if (etr_port0_uptodate && etr_port1_uptodate) | |
1038 | eacr.e1 = 1; | |
1039 | sync_port = (etr_port0_uptodate && | |
1040 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1041 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { |
1042 | eacr.sl = 0; | |
1043 | eacr.e0 = 0; | |
1044 | eacr.e1 = 1; | |
1045 | if (!etr_mode_is_pps(etr_eacr)) | |
1046 | eacr.es = 0; | |
1047 | sync_port = (etr_port1_uptodate && | |
1048 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1049 | } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { |
1050 | eacr.sl = 1; | |
1051 | eacr.e0 = 1; | |
1052 | if (!etr_mode_is_etr(etr_eacr)) | |
1053 | eacr.es = 0; | |
1054 | if (!eacr.es || !eacr.p1 || | |
1055 | aib.esw.psc1 != etr_lpsc_operational_alt) | |
1056 | eacr.e1 = 0; | |
1057 | else if (etr_port0_uptodate && etr_port1_uptodate && | |
1058 | etr_compare_network(&etr_port0, &etr_port1)) | |
1059 | eacr.e1 = 1; | |
1060 | sync_port = (etr_port0_uptodate && | |
1061 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1062 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { |
1063 | eacr.sl = 1; | |
1064 | eacr.e0 = 0; | |
1065 | eacr.e1 = 1; | |
1066 | if (!etr_mode_is_etr(etr_eacr)) | |
1067 | eacr.es = 0; | |
1068 | sync_port = (etr_port1_uptodate && | |
1069 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1070 | } else { |
1071 | /* Both ports not usable. */ | |
1072 | eacr.es = eacr.sl = 0; | |
1073 | sync_port = -1; | |
d2fec595 | 1074 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); |
d54853ef MS |
1075 | } |
1076 | ||
d2fec595 MS |
1077 | if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags)) |
1078 | eacr.es = 0; | |
1079 | ||
d54853ef MS |
1080 | /* |
1081 | * If the clock is in sync just update the eacr and return. | |
1082 | * If there is no valid sync port wait for a port update. | |
1083 | */ | |
d2fec595 MS |
1084 | if (test_bit(CLOCK_SYNC_STP, &clock_sync_flags) || |
1085 | eacr.es || sync_port < 0) { | |
d54853ef MS |
1086 | etr_update_eacr(eacr); |
1087 | etr_set_tolec_timeout(now); | |
0b3016b7 | 1088 | goto out_unlock; |
d54853ef MS |
1089 | } |
1090 | ||
1091 | /* | |
1092 | * Prepare control register for clock syncing | |
1093 | * (reset data port bit, set sync check control. | |
1094 | */ | |
1095 | eacr.dp = 0; | |
1096 | eacr.es = 1; | |
1097 | ||
1098 | /* | |
1099 | * Update eacr and try to synchronize the clock. If the update | |
1100 | * of eacr caused a stepping port switch (or if we have to | |
1101 | * assume that a stepping port switch has occured) or the | |
1102 | * clock syncing failed, reset the sync check control bit | |
1103 | * and set up a timer to try again after 0.5 seconds | |
1104 | */ | |
1105 | etr_update_eacr(eacr); | |
d2fec595 | 1106 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); |
d54853ef | 1107 | if (now < etr_tolec + (1600000 << 12) || |
750887de | 1108 | etr_sync_clock_stop(&aib, sync_port) != 0) { |
d54853ef MS |
1109 | /* Sync failed. Try again in 1/2 second. */ |
1110 | eacr.es = 0; | |
1111 | etr_update_eacr(eacr); | |
d2fec595 | 1112 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); |
d54853ef MS |
1113 | etr_set_sync_timeout(); |
1114 | } else | |
1115 | etr_set_tolec_timeout(now); | |
0b3016b7 MS |
1116 | out_unlock: |
1117 | mutex_unlock(&etr_work_mutex); | |
d54853ef MS |
1118 | } |
1119 | ||
1120 | /* | |
1121 | * Sysfs interface functions | |
1122 | */ | |
1123 | static struct sysdev_class etr_sysclass = { | |
af5ca3f4 | 1124 | .name = "etr", |
d54853ef MS |
1125 | }; |
1126 | ||
1127 | static struct sys_device etr_port0_dev = { | |
1128 | .id = 0, | |
1129 | .cls = &etr_sysclass, | |
1130 | }; | |
1131 | ||
1132 | static struct sys_device etr_port1_dev = { | |
1133 | .id = 1, | |
1134 | .cls = &etr_sysclass, | |
1135 | }; | |
1136 | ||
1137 | /* | |
1138 | * ETR class attributes | |
1139 | */ | |
1140 | static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf) | |
1141 | { | |
1142 | return sprintf(buf, "%i\n", etr_port0.esw.p); | |
1143 | } | |
1144 | ||
1145 | static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); | |
1146 | ||
1147 | static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf) | |
1148 | { | |
1149 | char *mode_str; | |
1150 | ||
1151 | if (etr_mode_is_pps(etr_eacr)) | |
1152 | mode_str = "pps"; | |
1153 | else if (etr_mode_is_etr(etr_eacr)) | |
1154 | mode_str = "etr"; | |
1155 | else | |
1156 | mode_str = "local"; | |
1157 | return sprintf(buf, "%s\n", mode_str); | |
1158 | } | |
1159 | ||
1160 | static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); | |
1161 | ||
1162 | /* | |
1163 | * ETR port attributes | |
1164 | */ | |
1165 | static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev) | |
1166 | { | |
1167 | if (dev == &etr_port0_dev) | |
1168 | return etr_port0_online ? &etr_port0 : NULL; | |
1169 | else | |
1170 | return etr_port1_online ? &etr_port1 : NULL; | |
1171 | } | |
1172 | ||
4a0b2b4d AK |
1173 | static ssize_t etr_online_show(struct sys_device *dev, |
1174 | struct sysdev_attribute *attr, | |
1175 | char *buf) | |
d54853ef MS |
1176 | { |
1177 | unsigned int online; | |
1178 | ||
1179 | online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; | |
1180 | return sprintf(buf, "%i\n", online); | |
1181 | } | |
1182 | ||
1183 | static ssize_t etr_online_store(struct sys_device *dev, | |
4a0b2b4d AK |
1184 | struct sysdev_attribute *attr, |
1185 | const char *buf, size_t count) | |
d54853ef MS |
1186 | { |
1187 | unsigned int value; | |
1188 | ||
1189 | value = simple_strtoul(buf, NULL, 0); | |
1190 | if (value != 0 && value != 1) | |
1191 | return -EINVAL; | |
d2fec595 MS |
1192 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
1193 | return -EOPNOTSUPP; | |
d54853ef MS |
1194 | if (dev == &etr_port0_dev) { |
1195 | if (etr_port0_online == value) | |
1196 | return count; /* Nothing to do. */ | |
1197 | etr_port0_online = value; | |
1198 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
750887de | 1199 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
1200 | } else { |
1201 | if (etr_port1_online == value) | |
1202 | return count; /* Nothing to do. */ | |
1203 | etr_port1_online = value; | |
1204 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
750887de | 1205 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
1206 | } |
1207 | return count; | |
1208 | } | |
1209 | ||
1210 | static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store); | |
1211 | ||
4a0b2b4d AK |
1212 | static ssize_t etr_stepping_control_show(struct sys_device *dev, |
1213 | struct sysdev_attribute *attr, | |
1214 | char *buf) | |
d54853ef MS |
1215 | { |
1216 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1217 | etr_eacr.e0 : etr_eacr.e1); | |
1218 | } | |
1219 | ||
1220 | static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); | |
1221 | ||
4a0b2b4d AK |
1222 | static ssize_t etr_mode_code_show(struct sys_device *dev, |
1223 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1224 | { |
1225 | if (!etr_port0_online && !etr_port1_online) | |
1226 | /* Status word is not uptodate if both ports are offline. */ | |
1227 | return -ENODATA; | |
1228 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1229 | etr_port0.esw.psc0 : etr_port0.esw.psc1); | |
1230 | } | |
1231 | ||
1232 | static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL); | |
1233 | ||
4a0b2b4d AK |
1234 | static ssize_t etr_untuned_show(struct sys_device *dev, |
1235 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1236 | { |
1237 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1238 | ||
1239 | if (!aib || !aib->slsw.v1) | |
1240 | return -ENODATA; | |
1241 | return sprintf(buf, "%i\n", aib->edf1.u); | |
1242 | } | |
1243 | ||
1244 | static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL); | |
1245 | ||
4a0b2b4d AK |
1246 | static ssize_t etr_network_id_show(struct sys_device *dev, |
1247 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1248 | { |
1249 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1250 | ||
1251 | if (!aib || !aib->slsw.v1) | |
1252 | return -ENODATA; | |
1253 | return sprintf(buf, "%i\n", aib->edf1.net_id); | |
1254 | } | |
1255 | ||
1256 | static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL); | |
1257 | ||
4a0b2b4d AK |
1258 | static ssize_t etr_id_show(struct sys_device *dev, |
1259 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1260 | { |
1261 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1262 | ||
1263 | if (!aib || !aib->slsw.v1) | |
1264 | return -ENODATA; | |
1265 | return sprintf(buf, "%i\n", aib->edf1.etr_id); | |
1266 | } | |
1267 | ||
1268 | static SYSDEV_ATTR(id, 0400, etr_id_show, NULL); | |
1269 | ||
4a0b2b4d AK |
1270 | static ssize_t etr_port_number_show(struct sys_device *dev, |
1271 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1272 | { |
1273 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1274 | ||
1275 | if (!aib || !aib->slsw.v1) | |
1276 | return -ENODATA; | |
1277 | return sprintf(buf, "%i\n", aib->edf1.etr_pn); | |
1278 | } | |
1279 | ||
1280 | static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL); | |
1281 | ||
4a0b2b4d AK |
1282 | static ssize_t etr_coupled_show(struct sys_device *dev, |
1283 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1284 | { |
1285 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1286 | ||
1287 | if (!aib || !aib->slsw.v3) | |
1288 | return -ENODATA; | |
1289 | return sprintf(buf, "%i\n", aib->edf3.c); | |
1290 | } | |
1291 | ||
1292 | static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL); | |
1293 | ||
4a0b2b4d AK |
1294 | static ssize_t etr_local_time_show(struct sys_device *dev, |
1295 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1296 | { |
1297 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1298 | ||
1299 | if (!aib || !aib->slsw.v3) | |
1300 | return -ENODATA; | |
1301 | return sprintf(buf, "%i\n", aib->edf3.blto); | |
1302 | } | |
1303 | ||
1304 | static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL); | |
1305 | ||
4a0b2b4d AK |
1306 | static ssize_t etr_utc_offset_show(struct sys_device *dev, |
1307 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1308 | { |
1309 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1310 | ||
1311 | if (!aib || !aib->slsw.v3) | |
1312 | return -ENODATA; | |
1313 | return sprintf(buf, "%i\n", aib->edf3.buo); | |
1314 | } | |
1315 | ||
1316 | static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); | |
1317 | ||
1318 | static struct sysdev_attribute *etr_port_attributes[] = { | |
1319 | &attr_online, | |
1320 | &attr_stepping_control, | |
1321 | &attr_state_code, | |
1322 | &attr_untuned, | |
1323 | &attr_network, | |
1324 | &attr_id, | |
1325 | &attr_port, | |
1326 | &attr_coupled, | |
1327 | &attr_local_time, | |
1328 | &attr_utc_offset, | |
1329 | NULL | |
1330 | }; | |
1331 | ||
1332 | static int __init etr_register_port(struct sys_device *dev) | |
1333 | { | |
1334 | struct sysdev_attribute **attr; | |
1335 | int rc; | |
1336 | ||
1337 | rc = sysdev_register(dev); | |
1338 | if (rc) | |
1339 | goto out; | |
1340 | for (attr = etr_port_attributes; *attr; attr++) { | |
1341 | rc = sysdev_create_file(dev, *attr); | |
1342 | if (rc) | |
1343 | goto out_unreg; | |
1344 | } | |
1345 | return 0; | |
1346 | out_unreg: | |
1347 | for (; attr >= etr_port_attributes; attr--) | |
1348 | sysdev_remove_file(dev, *attr); | |
1349 | sysdev_unregister(dev); | |
1350 | out: | |
1351 | return rc; | |
1352 | } | |
1353 | ||
1354 | static void __init etr_unregister_port(struct sys_device *dev) | |
1355 | { | |
1356 | struct sysdev_attribute **attr; | |
1357 | ||
1358 | for (attr = etr_port_attributes; *attr; attr++) | |
1359 | sysdev_remove_file(dev, *attr); | |
1360 | sysdev_unregister(dev); | |
1361 | } | |
1362 | ||
1363 | static int __init etr_init_sysfs(void) | |
1364 | { | |
1365 | int rc; | |
1366 | ||
1367 | rc = sysdev_class_register(&etr_sysclass); | |
1368 | if (rc) | |
1369 | goto out; | |
1370 | rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port); | |
1371 | if (rc) | |
1372 | goto out_unreg_class; | |
1373 | rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode); | |
1374 | if (rc) | |
1375 | goto out_remove_stepping_port; | |
1376 | rc = etr_register_port(&etr_port0_dev); | |
1377 | if (rc) | |
1378 | goto out_remove_stepping_mode; | |
1379 | rc = etr_register_port(&etr_port1_dev); | |
1380 | if (rc) | |
1381 | goto out_remove_port0; | |
1382 | return 0; | |
1383 | ||
1384 | out_remove_port0: | |
1385 | etr_unregister_port(&etr_port0_dev); | |
1386 | out_remove_stepping_mode: | |
1387 | sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode); | |
1388 | out_remove_stepping_port: | |
1389 | sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port); | |
1390 | out_unreg_class: | |
1391 | sysdev_class_unregister(&etr_sysclass); | |
1392 | out: | |
1393 | return rc; | |
1da177e4 LT |
1394 | } |
1395 | ||
d54853ef | 1396 | device_initcall(etr_init_sysfs); |
d2fec595 MS |
1397 | |
1398 | /* | |
1399 | * Server Time Protocol (STP) code. | |
1400 | */ | |
1401 | static int stp_online; | |
1402 | static struct stp_sstpi stp_info; | |
1403 | static void *stp_page; | |
1404 | ||
1405 | static void stp_work_fn(struct work_struct *work); | |
0b3016b7 | 1406 | static DEFINE_MUTEX(stp_work_mutex); |
d2fec595 MS |
1407 | static DECLARE_WORK(stp_work, stp_work_fn); |
1408 | ||
1409 | static int __init early_parse_stp(char *p) | |
1410 | { | |
1411 | if (strncmp(p, "off", 3) == 0) | |
1412 | stp_online = 0; | |
1413 | else if (strncmp(p, "on", 2) == 0) | |
1414 | stp_online = 1; | |
1415 | return 0; | |
1416 | } | |
1417 | early_param("stp", early_parse_stp); | |
1418 | ||
1419 | /* | |
1420 | * Reset STP attachment. | |
1421 | */ | |
8f847003 | 1422 | static void __init stp_reset(void) |
d2fec595 MS |
1423 | { |
1424 | int rc; | |
1425 | ||
1426 | stp_page = alloc_bootmem_pages(PAGE_SIZE); | |
1427 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); | |
4a672cfa | 1428 | if (rc == 0) |
d2fec595 MS |
1429 | set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); |
1430 | else if (stp_online) { | |
feab6501 MS |
1431 | pr_warning("The real or virtual hardware system does " |
1432 | "not provide an STP interface\n"); | |
d2fec595 MS |
1433 | free_bootmem((unsigned long) stp_page, PAGE_SIZE); |
1434 | stp_page = NULL; | |
1435 | stp_online = 0; | |
1436 | } | |
1437 | } | |
1438 | ||
1439 | static int __init stp_init(void) | |
1440 | { | |
750887de HC |
1441 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) |
1442 | return 0; | |
1443 | time_init_wq(); | |
1444 | if (!stp_online) | |
1445 | return 0; | |
1446 | queue_work(time_sync_wq, &stp_work); | |
d2fec595 MS |
1447 | return 0; |
1448 | } | |
1449 | ||
1450 | arch_initcall(stp_init); | |
1451 | ||
1452 | /* | |
1453 | * STP timing alert. There are three causes: | |
1454 | * 1) timing status change | |
1455 | * 2) link availability change | |
1456 | * 3) time control parameter change | |
1457 | * In all three cases we are only interested in the clock source state. | |
1458 | * If a STP clock source is now available use it. | |
1459 | */ | |
1460 | static void stp_timing_alert(struct stp_irq_parm *intparm) | |
1461 | { | |
1462 | if (intparm->tsc || intparm->lac || intparm->tcpc) | |
750887de | 1463 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1464 | } |
1465 | ||
1466 | /* | |
1467 | * STP sync check machine check. This is called when the timing state | |
1468 | * changes from the synchronized state to the unsynchronized state. | |
1469 | * After a STP sync check the clock is not in sync. The machine check | |
1470 | * is broadcasted to all cpus at the same time. | |
1471 | */ | |
1472 | void stp_sync_check(void) | |
1473 | { | |
1474 | if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags)) | |
1475 | return; | |
1476 | disable_sync_clock(NULL); | |
750887de | 1477 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1478 | } |
1479 | ||
1480 | /* | |
1481 | * STP island condition machine check. This is called when an attached | |
1482 | * server attempts to communicate over an STP link and the servers | |
1483 | * have matching CTN ids and have a valid stratum-1 configuration | |
1484 | * but the configurations do not match. | |
1485 | */ | |
1486 | void stp_island_check(void) | |
1487 | { | |
1488 | if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags)) | |
1489 | return; | |
1490 | disable_sync_clock(NULL); | |
750887de | 1491 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1492 | } |
1493 | ||
750887de HC |
1494 | |
1495 | static int stp_sync_clock(void *data) | |
d2fec595 | 1496 | { |
750887de | 1497 | static int first; |
d2fec595 | 1498 | unsigned long long old_clock, delta; |
750887de | 1499 | struct clock_sync_data *stp_sync; |
d2fec595 MS |
1500 | int rc; |
1501 | ||
750887de | 1502 | stp_sync = data; |
d2fec595 | 1503 | |
750887de HC |
1504 | if (xchg(&first, 1) == 1) { |
1505 | /* Slave */ | |
1506 | clock_sync_cpu(stp_sync); | |
1507 | return 0; | |
1508 | } | |
d2fec595 | 1509 | |
750887de HC |
1510 | /* Wait until all other cpus entered the sync function. */ |
1511 | while (atomic_read(&stp_sync->cpus) != 0) | |
1512 | cpu_relax(); | |
d2fec595 | 1513 | |
d2fec595 MS |
1514 | enable_sync_clock(); |
1515 | ||
1516 | set_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
1517 | if (test_and_clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags)) | |
750887de | 1518 | queue_work(time_sync_wq, &etr_work); |
d2fec595 MS |
1519 | |
1520 | rc = 0; | |
1521 | if (stp_info.todoff[0] || stp_info.todoff[1] || | |
1522 | stp_info.todoff[2] || stp_info.todoff[3] || | |
1523 | stp_info.tmd != 2) { | |
1524 | old_clock = get_clock(); | |
1525 | rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0); | |
1526 | if (rc == 0) { | |
1527 | delta = adjust_time(old_clock, get_clock(), 0); | |
1528 | fixup_clock_comparator(delta); | |
1529 | rc = chsc_sstpi(stp_page, &stp_info, | |
1530 | sizeof(struct stp_sstpi)); | |
1531 | if (rc == 0 && stp_info.tmd != 2) | |
1532 | rc = -EAGAIN; | |
1533 | } | |
1534 | } | |
1535 | if (rc) { | |
1536 | disable_sync_clock(NULL); | |
750887de | 1537 | stp_sync->in_sync = -EAGAIN; |
d2fec595 MS |
1538 | clear_bit(CLOCK_SYNC_STP, &clock_sync_flags); |
1539 | if (etr_port0_online || etr_port1_online) | |
750887de | 1540 | queue_work(time_sync_wq, &etr_work); |
d2fec595 | 1541 | } else |
750887de HC |
1542 | stp_sync->in_sync = 1; |
1543 | xchg(&first, 0); | |
1544 | return 0; | |
1545 | } | |
d2fec595 | 1546 | |
750887de HC |
1547 | /* |
1548 | * STP work. Check for the STP state and take over the clock | |
1549 | * synchronization if the STP clock source is usable. | |
1550 | */ | |
1551 | static void stp_work_fn(struct work_struct *work) | |
1552 | { | |
1553 | struct clock_sync_data stp_sync; | |
1554 | int rc; | |
1555 | ||
0b3016b7 MS |
1556 | /* prevent multiple execution. */ |
1557 | mutex_lock(&stp_work_mutex); | |
1558 | ||
750887de HC |
1559 | if (!stp_online) { |
1560 | chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); | |
0b3016b7 | 1561 | goto out_unlock; |
750887de HC |
1562 | } |
1563 | ||
1564 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0); | |
1565 | if (rc) | |
0b3016b7 | 1566 | goto out_unlock; |
750887de HC |
1567 | |
1568 | rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi)); | |
1569 | if (rc || stp_info.c == 0) | |
0b3016b7 | 1570 | goto out_unlock; |
750887de HC |
1571 | |
1572 | memset(&stp_sync, 0, sizeof(stp_sync)); | |
1573 | get_online_cpus(); | |
1574 | atomic_set(&stp_sync.cpus, num_online_cpus() - 1); | |
1575 | stop_machine(stp_sync_clock, &stp_sync, &cpu_online_map); | |
1576 | put_online_cpus(); | |
0b3016b7 MS |
1577 | |
1578 | out_unlock: | |
1579 | mutex_unlock(&stp_work_mutex); | |
d2fec595 MS |
1580 | } |
1581 | ||
1582 | /* | |
1583 | * STP class sysfs interface functions | |
1584 | */ | |
1585 | static struct sysdev_class stp_sysclass = { | |
1586 | .name = "stp", | |
1587 | }; | |
1588 | ||
1589 | static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf) | |
1590 | { | |
1591 | if (!stp_online) | |
1592 | return -ENODATA; | |
1593 | return sprintf(buf, "%016llx\n", | |
1594 | *(unsigned long long *) stp_info.ctnid); | |
1595 | } | |
1596 | ||
1597 | static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL); | |
1598 | ||
1599 | static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf) | |
1600 | { | |
1601 | if (!stp_online) | |
1602 | return -ENODATA; | |
1603 | return sprintf(buf, "%i\n", stp_info.ctn); | |
1604 | } | |
1605 | ||
1606 | static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL); | |
1607 | ||
1608 | static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf) | |
1609 | { | |
1610 | if (!stp_online || !(stp_info.vbits & 0x2000)) | |
1611 | return -ENODATA; | |
1612 | return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto); | |
1613 | } | |
1614 | ||
1615 | static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL); | |
1616 | ||
1617 | static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf) | |
1618 | { | |
1619 | if (!stp_online || !(stp_info.vbits & 0x8000)) | |
1620 | return -ENODATA; | |
1621 | return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps); | |
1622 | } | |
1623 | ||
1624 | static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL); | |
1625 | ||
1626 | static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf) | |
1627 | { | |
1628 | if (!stp_online) | |
1629 | return -ENODATA; | |
1630 | return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum); | |
1631 | } | |
1632 | ||
1633 | static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL); | |
1634 | ||
1635 | static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf) | |
1636 | { | |
1637 | if (!stp_online || !(stp_info.vbits & 0x0800)) | |
1638 | return -ENODATA; | |
1639 | return sprintf(buf, "%i\n", (int) stp_info.tto); | |
1640 | } | |
1641 | ||
1642 | static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL); | |
1643 | ||
1644 | static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf) | |
1645 | { | |
1646 | if (!stp_online || !(stp_info.vbits & 0x4000)) | |
1647 | return -ENODATA; | |
1648 | return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo); | |
1649 | } | |
1650 | ||
1651 | static SYSDEV_CLASS_ATTR(time_zone_offset, 0400, | |
1652 | stp_time_zone_offset_show, NULL); | |
1653 | ||
1654 | static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf) | |
1655 | { | |
1656 | if (!stp_online) | |
1657 | return -ENODATA; | |
1658 | return sprintf(buf, "%i\n", stp_info.tmd); | |
1659 | } | |
1660 | ||
1661 | static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL); | |
1662 | ||
1663 | static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf) | |
1664 | { | |
1665 | if (!stp_online) | |
1666 | return -ENODATA; | |
1667 | return sprintf(buf, "%i\n", stp_info.tst); | |
1668 | } | |
1669 | ||
1670 | static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL); | |
1671 | ||
1672 | static ssize_t stp_online_show(struct sysdev_class *class, char *buf) | |
1673 | { | |
1674 | return sprintf(buf, "%i\n", stp_online); | |
1675 | } | |
1676 | ||
1677 | static ssize_t stp_online_store(struct sysdev_class *class, | |
1678 | const char *buf, size_t count) | |
1679 | { | |
1680 | unsigned int value; | |
1681 | ||
1682 | value = simple_strtoul(buf, NULL, 0); | |
1683 | if (value != 0 && value != 1) | |
1684 | return -EINVAL; | |
1685 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
1686 | return -EOPNOTSUPP; | |
1687 | stp_online = value; | |
750887de | 1688 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1689 | return count; |
1690 | } | |
1691 | ||
1692 | /* | |
1693 | * Can't use SYSDEV_CLASS_ATTR because the attribute should be named | |
1694 | * stp/online but attr_online already exists in this file .. | |
1695 | */ | |
1696 | static struct sysdev_class_attribute attr_stp_online = { | |
1697 | .attr = { .name = "online", .mode = 0600 }, | |
1698 | .show = stp_online_show, | |
1699 | .store = stp_online_store, | |
1700 | }; | |
1701 | ||
1702 | static struct sysdev_class_attribute *stp_attributes[] = { | |
1703 | &attr_ctn_id, | |
1704 | &attr_ctn_type, | |
1705 | &attr_dst_offset, | |
1706 | &attr_leap_seconds, | |
1707 | &attr_stp_online, | |
1708 | &attr_stratum, | |
1709 | &attr_time_offset, | |
1710 | &attr_time_zone_offset, | |
1711 | &attr_timing_mode, | |
1712 | &attr_timing_state, | |
1713 | NULL | |
1714 | }; | |
1715 | ||
1716 | static int __init stp_init_sysfs(void) | |
1717 | { | |
1718 | struct sysdev_class_attribute **attr; | |
1719 | int rc; | |
1720 | ||
1721 | rc = sysdev_class_register(&stp_sysclass); | |
1722 | if (rc) | |
1723 | goto out; | |
1724 | for (attr = stp_attributes; *attr; attr++) { | |
1725 | rc = sysdev_class_create_file(&stp_sysclass, *attr); | |
1726 | if (rc) | |
1727 | goto out_unreg; | |
1728 | } | |
1729 | return 0; | |
1730 | out_unreg: | |
1731 | for (; attr >= stp_attributes; attr--) | |
1732 | sysdev_class_remove_file(&stp_sysclass, *attr); | |
1733 | sysdev_class_unregister(&stp_sysclass); | |
1734 | out: | |
1735 | return rc; | |
1736 | } | |
1737 | ||
1738 | device_initcall(stp_init_sysfs); |