projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
s390/bpf: Adjust ALU64_DIV/MOD to match interpreter change
[deliverable/linux.git] / arch / s390 / net / bpf_jit_comp.c
CommitLineData
c10302ef
MS		 1/*
2 * BPF Jit compiler for s390.
3 *
05462310
MH		 4 * Minimum build requirements:
5 *
6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
9 * - PACK_STACK
10 * - 64BIT
11 *
12 * Copyright IBM Corp. 2012,2015
c10302ef
MS		 13 *
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
05462310 15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
c10302ef 16 */
05462310
MH		 17
18#define KMSG_COMPONENT "bpf_jit"
19#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
20
c10302ef
MS		 21#include <linux/netdevice.h>
22#include <linux/filter.h>
c9a7afa3 23#include <linux/init.h>
c10302ef 24#include <asm/cacheflush.h>
0f20822a 25#include <asm/dis.h>
05462310 26#include "bpf_jit.h"
c10302ef 27
c10302ef
MS		 28int bpf_jit_enable __read_mostly;
29
05462310
MH		 30struct bpf_jit {
31 u32 seen; /* Flags to remember seen eBPF instructions */
32 u32 seen_reg[16]; /* Array to remember which registers are used */
33 u32 *addrs; /* Array with relative instruction addresses */
34 u8 *prg_buf; /* Start of program */
35 int size; /* Size of program and literal pool */
36 int size_prg; /* Size of program */
37 int prg; /* Current position in program */
38 int lit_start; /* Start of literal pool */
39 int lit; /* Current position in literal pool */
40 int base_ip; /* Base address for literal pool */
41 int ret0_ip; /* Address of return 0 */
42 int exit_ip; /* Address of exit */
43};
44
45#define BPF_SIZE_MAX 4096 /* Max size for program */
46
47#define SEEN_SKB 1 /* skb access */
48#define SEEN_MEM 2 /* use mem[] for temporary storage */
49#define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */
50#define SEEN_LITERAL 8 /* code uses literals */
51#define SEEN_FUNC 16 /* calls C functions */
52#define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB)
53
c10302ef 54/*
05462310 55 * s390 registers
c10302ef 56 */
05462310
MH		 57#define REG_W0 (__MAX_BPF_REG+0) /* Work register 1 (even) */
58#define REG_W1 (__MAX_BPF_REG+1) /* Work register 2 (odd) */
59#define REG_SKB_DATA (__MAX_BPF_REG+2) /* SKB data register */
60#define REG_L (__MAX_BPF_REG+3) /* Literal pool register */
61#define REG_15 (__MAX_BPF_REG+4) /* Register 15 */
62#define REG_0 REG_W0 /* Register 0 */
63#define REG_2 BPF_REG_1 /* Register 2 */
64#define REG_14 BPF_REG_0 /* Register 14 */
c10302ef 65
05462310
MH		 66/*
67 * Mapping of BPF registers to s390 registers
68 */
69static const int reg2hex[] = {
70 /* Return code */
71 [BPF_REG_0] = 14,
72 /* Function parameters */
73 [BPF_REG_1] = 2,
74 [BPF_REG_2] = 3,
75 [BPF_REG_3] = 4,
76 [BPF_REG_4] = 5,
77 [BPF_REG_5] = 6,
78 /* Call saved registers */
79 [BPF_REG_6] = 7,
80 [BPF_REG_7] = 8,
81 [BPF_REG_8] = 9,
82 [BPF_REG_9] = 10,
83 /* BPF stack pointer */
84 [BPF_REG_FP] = 13,
85 /* SKB data pointer */
86 [REG_SKB_DATA] = 12,
87 /* Work registers for s390x backend */
88 [REG_W0] = 0,
89 [REG_W1] = 1,
90 [REG_L] = 11,
91 [REG_15] = 15,
c10302ef
MS		 92};
93
05462310
MH		 94static inline u32 reg(u32 dst_reg, u32 src_reg)
95{
96 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
97}
98
99static inline u32 reg_high(u32 reg)
100{
101 return reg2hex[reg] << 4;
102}
103
104static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
105{
106 u32 r1 = reg2hex[b1];
107
108 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
109 jit->seen_reg[r1] = 1;
110}
111
112#define REG_SET_SEEN(b1) \
113({ \
114 reg_set_seen(jit, b1); \
115})
116
117#define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
118
119/*
120 * EMIT macros for code generation
121 */
122
123#define _EMIT2(op) \
124({ \
125 if (jit->prg_buf) \
126 *(u16 *) (jit->prg_buf + jit->prg) = op; \
127 jit->prg += 2; \
128})
c10302ef 129
05462310
MH		 130#define EMIT2(op, b1, b2) \
131({ \
132 _EMIT2(op | reg(b1, b2)); \
133 REG_SET_SEEN(b1); \
134 REG_SET_SEEN(b2); \
c10302ef
MS		 135})
136
05462310
MH		 137#define _EMIT4(op) \
138({ \
139 if (jit->prg_buf) \
140 *(u32 *) (jit->prg_buf + jit->prg) = op; \
141 jit->prg += 4; \
c10302ef
MS		 142})
143
05462310
MH		 144#define EMIT4(op, b1, b2) \
145({ \
146 _EMIT4(op | reg(b1, b2)); \
147 REG_SET_SEEN(b1); \
148 REG_SET_SEEN(b2); \
c10302ef
MS		 149})
150
05462310
MH		 151#define EMIT4_RRF(op, b1, b2, b3) \
152({ \
153 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
154 REG_SET_SEEN(b1); \
155 REG_SET_SEEN(b2); \
156 REG_SET_SEEN(b3); \
c10302ef
MS		 157})
158
05462310
MH		 159#define _EMIT4_DISP(op, disp) \
160({ \
161 unsigned int __disp = (disp) & 0xfff; \
162 _EMIT4(op | __disp); \
c10302ef
MS		 163})
164
05462310
MH		 165#define EMIT4_DISP(op, b1, b2, disp) \
166({ \
167 _EMIT4_DISP(op | reg_high(b1) << 16 | \
168 reg_high(b2) << 8, disp); \
169 REG_SET_SEEN(b1); \
170 REG_SET_SEEN(b2); \
c10302ef
MS		 171})
172
05462310
MH		 173#define EMIT4_IMM(op, b1, imm) \
174({ \
175 unsigned int __imm = (imm) & 0xffff; \
176 _EMIT4(op | reg_high(b1) << 16 | __imm); \
177 REG_SET_SEEN(b1); \
c10302ef
MS		 178})
179
05462310
MH		 180#define EMIT4_PCREL(op, pcrel) \
181({ \
182 long __pcrel = ((pcrel) >> 1) & 0xffff; \
183 _EMIT4(op | __pcrel); \
68d9884d
HC		 184})
185
05462310
MH		 186#define _EMIT6(op1, op2) \
187({ \
188 if (jit->prg_buf) { \
189 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
190 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
191 } \
192 jit->prg += 6; \
c10302ef
MS		 193})
194
05462310
MH		 195#define _EMIT6_DISP(op1, op2, disp) \
196({ \
197 unsigned int __disp = (disp) & 0xfff; \
198 _EMIT6(op1 | __disp, op2); \
c10302ef
MS		 199})
200
05462310
MH		 201#define EMIT6_DISP(op1, op2, b1, b2, b3, disp) \
202({ \
203 _EMIT6_DISP(op1 | reg(b1, b2) << 16 | \
204 reg_high(b3) << 8, op2, disp); \
205 REG_SET_SEEN(b1); \
206 REG_SET_SEEN(b2); \
207 REG_SET_SEEN(b3); \
208})
209
210#define _EMIT6_DISP_LH(op1, op2, disp) \
211({ \
212 unsigned int __disp_h = ((u32)disp) & 0xff000; \
213 unsigned int __disp_l = ((u32)disp) & 0x00fff; \
214 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
215})
216
217#define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
218({ \
219 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
220 reg_high(b3) << 8, op2, disp); \
221 REG_SET_SEEN(b1); \
222 REG_SET_SEEN(b2); \
223 REG_SET_SEEN(b3); \
224})
225
226#define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
227({ \
228 /* Branch instruction needs 6 bytes */ \
229 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
230 _EMIT6(op1 | reg(b1, b2) << 16 | rel, op2 | mask); \
231 REG_SET_SEEN(b1); \
232 REG_SET_SEEN(b2); \
233})
234
235#define _EMIT6_IMM(op, imm) \
236({ \
237 unsigned int __imm = (imm); \
238 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
239})
240
241#define EMIT6_IMM(op, b1, imm) \
242({ \
243 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
244 REG_SET_SEEN(b1); \
245})
246
247#define EMIT_CONST_U32(val) \
248({ \
249 unsigned int ret; \
250 ret = jit->lit - jit->base_ip; \
251 jit->seen |= SEEN_LITERAL; \
252 if (jit->prg_buf) \
253 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
254 jit->lit += 4; \
255 ret; \
256})
257
258#define EMIT_CONST_U64(val) \
259({ \
260 unsigned int ret; \
261 ret = jit->lit - jit->base_ip; \
262 jit->seen |= SEEN_LITERAL; \
263 if (jit->prg_buf) \
264 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
265 jit->lit += 8; \
266 ret; \
267})
268
269#define EMIT_ZERO(b1) \
270({ \
271 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
272 EMIT4(0xb9160000, b1, b1); \
273 REG_SET_SEEN(b1); \
274})
275
276/*
277 * Fill whole space with illegal instructions
278 */
279static void jit_fill_hole(void *area, unsigned int size)
738cbe72 280{
738cbe72
DB		 281 memset(area, 0, size);
282}
283
05462310
MH		 284/*
285 * Save registers from "rs" (register start) to "re" (register end) on stack
286 */
287static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
288{
289 u32 off = 72 + (rs - 6) * 8;
290
291 if (rs == re)
292 /* stg %rs,off(%r15) */
293 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
294 else
295 /* stmg %rs,%re,off(%r15) */
296 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
297}
298
299/*
300 * Restore registers from "rs" (register start) to "re" (register end) on stack
301 */
302static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re)
c10302ef 303{
05462310
MH		 304 u32 off = 72 + (rs - 6) * 8;
305
306 if (jit->seen & SEEN_STACK)
307 off += STK_OFF;
308
309 if (rs == re)
310 /* lg %rs,off(%r15) */
311 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
312 else
313 /* lmg %rs,%re,off(%r15) */
314 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
315}
c10302ef 316
05462310
MH		 317/*
318 * Return first seen register (from start)
319 */
320static int get_start(struct bpf_jit *jit, int start)
321{
322 int i;
323
324 for (i = start; i <= 15; i++) {
325 if (jit->seen_reg[i])
326 return i;
327 }
328 return 0;
329}
330
331/*
332 * Return last seen register (from start) (gap >= 2)
333 */
334static int get_end(struct bpf_jit *jit, int start)
335{
336 int i;
337
338 for (i = start; i < 15; i++) {
339 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
340 return i - 1;
341 }
342 return jit->seen_reg[15] ? 15 : 14;
343}
344
345#define REGS_SAVE 1
346#define REGS_RESTORE 0
347/*
348 * Save and restore clobbered registers (6-15) on stack.
349 * We save/restore registers in chunks with gap >= 2 registers.
350 */
351static void save_restore_regs(struct bpf_jit *jit, int op)
352{
353
354 int re = 6, rs;
355
356 do {
357 rs = get_start(jit, re);
358 if (!rs)
359 break;
360 re = get_end(jit, rs + 1);
361 if (op == REGS_SAVE)
362 save_regs(jit, rs, re);
363 else
364 restore_regs(jit, rs, re);
365 re++;
366 } while (re <= 15);
367}
368
369/*
370 * Emit function prologue
371 *
372 * Save registers and create stack frame if necessary.
373 * See stack frame layout desription in "bpf_jit.h"!
374 */
375static void bpf_jit_prologue(struct bpf_jit *jit)
376{
377 /* Save registers */
378 save_restore_regs(jit, REGS_SAVE);
c10302ef
MS		 379 /* Setup literal pool */
380 if (jit->seen & SEEN_LITERAL) {
381 /* basr %r13,0 */
05462310 382 EMIT2(0x0d00, REG_L, REG_0);
c10302ef
MS		 383 jit->base_ip = jit->prg;
384 }
05462310
MH		 385 /* Setup stack and backchain */
386 if (jit->seen & SEEN_STACK) {
387 /* lgr %bfp,%r15 (BPF frame pointer) */
388 EMIT4(0xb9040000, BPF_REG_FP, REG_15);
389 /* aghi %r15,-STK_OFF */
390 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF);
391 if (jit->seen & SEEN_FUNC)
392 /* stg %bfp,152(%r15) (backchain) */
393 EMIT6_DISP_LH(0xe3000000, 0x0024, BPF_REG_FP, REG_0,
394 REG_15, 152);
395 }
396 /*
397 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S"
398 * we store the SKB header length on the stack and the SKB data
399 * pointer in REG_SKB_DATA.
400 */
401 if (jit->seen & SEEN_SKB) {
402 /* Header length: llgf %w1,<len>(%b1) */
403 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1,
404 offsetof(struct sk_buff, len));
405 /* s %w1,<data_len>(%b1) */
406 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1,
407 offsetof(struct sk_buff, data_len));
408 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */
409 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15,
410 STK_OFF_HLEN);
411 /* lg %skb_data,data_off(%b1) */
412 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0,
413 BPF_REG_1, offsetof(struct sk_buff, data));
c10302ef 414 }
05462310
MH		 415 /* BPF compatibility: clear A (%b7) and X (%b8) registers */
416 if (REG_SEEN(BPF_REG_7))
417 /* lghi %b7,0 */
418 EMIT4_IMM(0xa7090000, BPF_REG_7, 0);
419 if (REG_SEEN(BPF_REG_8))
420 /* lghi %b8,0 */
421 EMIT4_IMM(0xa7090000, BPF_REG_8, 0);
c10302ef
MS		 422}
423
05462310
MH		 424/*
425 * Function epilogue
426 */
c10302ef
MS		 427static void bpf_jit_epilogue(struct bpf_jit *jit)
428{
429 /* Return 0 */
430 if (jit->seen & SEEN_RET0) {
431 jit->ret0_ip = jit->prg;
05462310
MH		 432 /* lghi %b0,0 */
433 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
c10302ef
MS		 434 }
435 jit->exit_ip = jit->prg;
05462310
MH		 436 /* Load exit code: lgr %r2,%b0 */
437 EMIT4(0xb9040000, REG_2, BPF_REG_0);
c10302ef 438 /* Restore registers */
05462310 439 save_restore_regs(jit, REGS_RESTORE);
c10302ef 440 /* br %r14 */
05462310 441 _EMIT2(0x07fe);
c10302ef
MS		 442}
443
444/*
05462310 445 * Compile one eBPF instruction into s390x code
c10302ef 446 */
05462310 447static int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i)
c10302ef 448{
05462310
MH		 449 struct bpf_insn *insn = &fp->insnsi[i];
450 int jmp_off, last, insn_count = 1;
451 unsigned int func_addr, mask;
452 u32 dst_reg = insn->dst_reg;
453 u32 src_reg = insn->src_reg;
454 u32 *addrs = jit->addrs;
455 s32 imm = insn->imm;
456 s16 off = insn->off;
c10302ef 457
05462310
MH		 458 switch (insn->code) {
459 /*
460 * BPF_MOV
461 */
462 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
463 /* llgfr %dst,%src */
464 EMIT4(0xb9160000, dst_reg, src_reg);
465 break;
466 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
467 /* lgr %dst,%src */
468 EMIT4(0xb9040000, dst_reg, src_reg);
469 break;
470 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
471 /* llilf %dst,imm */
472 EMIT6_IMM(0xc00f0000, dst_reg, imm);
473 break;
474 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
475 /* lgfi %dst,imm */
476 EMIT6_IMM(0xc0010000, dst_reg, imm);
477 break;
478 /*
479 * BPF_LD 64
480 */
481 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
482 {
483 /* 16 byte instruction that uses two 'struct bpf_insn' */
484 u64 imm64;
485
486 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
487 /* lg %dst,<d(imm)>(%l) */
488 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
489 EMIT_CONST_U64(imm64));
490 insn_count = 2;
491 break;
492 }
493 /*
494 * BPF_ADD
495 */
496 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
497 /* ar %dst,%src */
498 EMIT2(0x1a00, dst_reg, src_reg);
499 EMIT_ZERO(dst_reg);
500 break;
501 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
502 /* agr %dst,%src */
503 EMIT4(0xb9080000, dst_reg, src_reg);
504 break;
505 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
506 if (!imm)
c10302ef 507 break;
05462310
MH		 508 /* alfi %dst,imm */
509 EMIT6_IMM(0xc20b0000, dst_reg, imm);
510 EMIT_ZERO(dst_reg);
511 break;
512 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
513 if (!imm)
514 break;
515 /* agfi %dst,imm */
516 EMIT6_IMM(0xc2080000, dst_reg, imm);
517 break;
518 /*
519 * BPF_SUB
520 */
521 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
522 /* sr %dst,%src */
523 EMIT2(0x1b00, dst_reg, src_reg);
524 EMIT_ZERO(dst_reg);
c10302ef 525 break;
05462310
MH		 526 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
527 /* sgr %dst,%src */
528 EMIT4(0xb9090000, dst_reg, src_reg);
c10302ef 529 break;
05462310
MH		 530 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
531 if (!imm)
c10302ef 532 break;
05462310
MH		 533 /* alfi %dst,-imm */
534 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
535 EMIT_ZERO(dst_reg);
c10302ef 536 break;
05462310
MH		 537 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
538 if (!imm)
539 break;
540 /* agfi %dst,-imm */
541 EMIT6_IMM(0xc2080000, dst_reg, -imm);
542 break;
543 /*
544 * BPF_MUL
545 */
546 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
547 /* msr %dst,%src */
548 EMIT4(0xb2520000, dst_reg, src_reg);
549 EMIT_ZERO(dst_reg);
550 break;
551 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
552 /* msgr %dst,%src */
553 EMIT4(0xb90c0000, dst_reg, src_reg);
554 break;
555 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
556 if (imm == 1)
557 break;
558 /* msfi %r5,imm */
559 EMIT6_IMM(0xc2010000, dst_reg, imm);
560 EMIT_ZERO(dst_reg);
561 break;
562 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
563 if (imm == 1)
aee636c4 564 break;
05462310
MH		 565 /* msgfi %dst,imm */
566 EMIT6_IMM(0xc2000000, dst_reg, imm);
567 break;
568 /*
569 * BPF_DIV / BPF_MOD
570 */
571 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
572 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
573 {
574 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
575
576 jit->seen |= SEEN_RET0;
577 /* ltr %src,%src (if src == 0 goto fail) */
578 EMIT2(0x1200, src_reg, src_reg);
579 /* jz <ret0> */
580 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
581 /* lhi %w0,0 */
582 EMIT4_IMM(0xa7080000, REG_W0, 0);
583 /* lr %w1,%dst */
584 EMIT2(0x1800, REG_W1, dst_reg);
585 /* dlr %w0,%src */
586 EMIT4(0xb9970000, REG_W0, src_reg);
587 /* llgfr %dst,%rc */
588 EMIT4(0xb9160000, dst_reg, rc_reg);
589 break;
590 }
771aada9
MH		 591 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
592 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
05462310
MH		 593 {
594 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
595
596 jit->seen |= SEEN_RET0;
597 /* ltgr %src,%src (if src == 0 goto fail) */
598 EMIT4(0xb9020000, src_reg, src_reg);
32472745 599 /* jz <ret0> */
05462310
MH		 600 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg);
601 /* lghi %w0,0 */
602 EMIT4_IMM(0xa7090000, REG_W0, 0);
603 /* lgr %w1,%dst */
604 EMIT4(0xb9040000, REG_W1, dst_reg);
05462310 605 /* dlgr %w0,%dst */
771aada9 606 EMIT4(0xb9870000, REG_W0, src_reg);
05462310
MH		 607 /* lgr %dst,%rc */
608 EMIT4(0xb9040000, dst_reg, rc_reg);
609 break;
610 }
611 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
612 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
613 {
614 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
615
616 if (imm == 1) {
617 if (BPF_OP(insn->code) == BPF_MOD)
618 /* lhgi %dst,0 */
619 EMIT4_IMM(0xa7090000, dst_reg, 0);
aee636c4
ED		 620 break;
621 }
05462310
MH		 622 /* lhi %w0,0 */
623 EMIT4_IMM(0xa7080000, REG_W0, 0);
624 /* lr %w1,%dst */
625 EMIT2(0x1800, REG_W1, dst_reg);
626 /* dl %w0,<d(imm)>(%l) */
627 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
628 EMIT_CONST_U32(imm));
629 /* llgfr %dst,%rc */
630 EMIT4(0xb9160000, dst_reg, rc_reg);
631 break;
632 }
771aada9
MH		 633 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
634 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
05462310
MH		 635 {
636 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
637
638 if (imm == 1) {
639 if (BPF_OP(insn->code) == BPF_MOD)
640 /* lhgi %dst,0 */
641 EMIT4_IMM(0xa7090000, dst_reg, 0);
642 break;
643 }
644 /* lghi %w0,0 */
645 EMIT4_IMM(0xa7090000, REG_W0, 0);
646 /* lgr %w1,%dst */
647 EMIT4(0xb9040000, REG_W1, dst_reg);
648 /* dlg %w0,<d(imm)>(%l) */
649 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
771aada9 650 EMIT_CONST_U64(imm));
05462310
MH		 651 /* lgr %dst,%rc */
652 EMIT4(0xb9040000, dst_reg, rc_reg);
653 break;
654 }
655 /*
656 * BPF_AND
657 */
658 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
659 /* nr %dst,%src */
660 EMIT2(0x1400, dst_reg, src_reg);
661 EMIT_ZERO(dst_reg);
662 break;
663 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
664 /* ngr %dst,%src */
665 EMIT4(0xb9800000, dst_reg, src_reg);
666 break;
667 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
668 /* nilf %dst,imm */
669 EMIT6_IMM(0xc00b0000, dst_reg, imm);
670 EMIT_ZERO(dst_reg);
c10302ef 671 break;
05462310
MH		 672 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
673 /* ng %dst,<d(imm)>(%l) */
674 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
675 EMIT_CONST_U64(imm));
c59eed11 676 break;
05462310
MH		 677 /*
678 * BPF_OR
679 */
680 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
681 /* or %dst,%src */
682 EMIT2(0x1600, dst_reg, src_reg);
683 EMIT_ZERO(dst_reg);
684 break;
685 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
686 /* ogr %dst,%src */
687 EMIT4(0xb9810000, dst_reg, src_reg);
688 break;
689 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
690 /* oilf %dst,imm */
691 EMIT6_IMM(0xc00d0000, dst_reg, imm);
692 EMIT_ZERO(dst_reg);
693 break;
694 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
695 /* og %dst,<d(imm)>(%l) */
696 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
697 EMIT_CONST_U64(imm));
698 break;
699 /*
700 * BPF_XOR
701 */
702 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
703 /* xr %dst,%src */
704 EMIT2(0x1700, dst_reg, src_reg);
705 EMIT_ZERO(dst_reg);
706 break;
707 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
708 /* xgr %dst,%src */
709 EMIT4(0xb9820000, dst_reg, src_reg);
710 break;
711 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
712 if (!imm)
916908df 713 break;
05462310
MH		 714 /* xilf %dst,imm */
715 EMIT6_IMM(0xc0070000, dst_reg, imm);
716 EMIT_ZERO(dst_reg);
717 break;
718 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
719 /* xg %dst,<d(imm)>(%l) */
720 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
721 EMIT_CONST_U64(imm));
722 break;
723 /*
724 * BPF_LSH
725 */
726 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
727 /* sll %dst,0(%src) */
728 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
729 EMIT_ZERO(dst_reg);
916908df 730 break;
05462310
MH		 731 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
732 /* sllg %dst,%dst,0(%src) */
733 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
c10302ef 734 break;
05462310
MH		 735 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
736 if (imm == 0)
c10302ef 737 break;
05462310
MH		 738 /* sll %dst,imm(%r0) */
739 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
740 EMIT_ZERO(dst_reg);
c10302ef 741 break;
05462310
MH		 742 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
743 if (imm == 0)
744 break;
745 /* sllg %dst,%dst,imm(%r0) */
746 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
747 break;
748 /*
749 * BPF_RSH
750 */
751 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
752 /* srl %dst,0(%src) */
753 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
754 EMIT_ZERO(dst_reg);
c10302ef 755 break;
05462310
MH		 756 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
757 /* srlg %dst,%dst,0(%src) */
758 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
759 break;
760 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
761 if (imm == 0)
c10302ef 762 break;
05462310
MH		 763 /* srl %dst,imm(%r0) */
764 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
765 EMIT_ZERO(dst_reg);
766 break;
767 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
768 if (imm == 0)
c10302ef 769 break;
05462310
MH		 770 /* srlg %dst,%dst,imm(%r0) */
771 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
c10302ef 772 break;
05462310
MH		 773 /*
774 * BPF_ARSH
775 */
776 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
777 /* srag %dst,%dst,0(%src) */
778 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
779 break;
780 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
781 if (imm == 0)
782 break;
783 /* srag %dst,%dst,imm(%r0) */
784 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
785 break;
786 /*
787 * BPF_NEG
788 */
789 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
790 /* lcr %dst,%dst */
791 EMIT2(0x1300, dst_reg, dst_reg);
792 EMIT_ZERO(dst_reg);
793 break;
794 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
795 /* lcgr %dst,%dst */
796 EMIT4(0xb9130000, dst_reg, dst_reg);
797 break;
798 /*
799 * BPF_FROM_BE/LE
800 */
801 case BPF_ALU | BPF_END | BPF_FROM_BE:
802 /* s390 is big endian, therefore only clear high order bytes */
803 switch (imm) {
804 case 16: /* dst = (u16) cpu_to_be16(dst) */
805 /* llghr %dst,%dst */
806 EMIT4(0xb9850000, dst_reg, dst_reg);
807 break;
808 case 32: /* dst = (u32) cpu_to_be32(dst) */
809 /* llgfr %dst,%dst */
810 EMIT4(0xb9160000, dst_reg, dst_reg);
811 break;
812 case 64: /* dst = (u64) cpu_to_be64(dst) */
813 break;
c10302ef 814 }
c10302ef 815 break;
05462310
MH		 816 case BPF_ALU | BPF_END | BPF_FROM_LE:
817 switch (imm) {
818 case 16: /* dst = (u16) cpu_to_le16(dst) */
819 /* lrvr %dst,%dst */
820 EMIT4(0xb91f0000, dst_reg, dst_reg);
821 /* srl %dst,16(%r0) */
822 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
823 /* llghr %dst,%dst */
824 EMIT4(0xb9850000, dst_reg, dst_reg);
825 break;
826 case 32: /* dst = (u32) cpu_to_le32(dst) */
827 /* lrvr %dst,%dst */
828 EMIT4(0xb91f0000, dst_reg, dst_reg);
829 /* llgfr %dst,%dst */
830 EMIT4(0xb9160000, dst_reg, dst_reg);
831 break;
832 case 64: /* dst = (u64) cpu_to_le64(dst) */
833 /* lrvgr %dst,%dst */
834 EMIT4(0xb90f0000, dst_reg, dst_reg);
c10302ef
MS		 835 break;
836 }
c10302ef 837 break;
05462310
MH		 838 /*
839 * BPF_ST(X)
840 */
841 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
842 /* stcy %src,off(%dst) */
843 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
844 jit->seen |= SEEN_MEM;
845 break;
846 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
847 /* sthy %src,off(%dst) */
848 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
849 jit->seen |= SEEN_MEM;
850 break;
851 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
852 /* sty %src,off(%dst) */
853 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
854 jit->seen |= SEEN_MEM;
855 break;
856 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
857 /* stg %src,off(%dst) */
858 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
859 jit->seen |= SEEN_MEM;
860 break;
861 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
862 /* lhi %w0,imm */
863 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
864 /* stcy %w0,off(dst) */
865 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
866 jit->seen |= SEEN_MEM;
867 break;
868 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
869 /* lhi %w0,imm */
870 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
871 /* sthy %w0,off(dst) */
872 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
c10302ef 873 jit->seen |= SEEN_MEM;
c10302ef 874 break;
05462310
MH		 875 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
876 /* llilf %w0,imm */
877 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
878 /* sty %w0,off(%dst) */
879 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
880 jit->seen |= SEEN_MEM;
881 break;
882 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
883 /* lgfi %w0,imm */
884 EMIT6_IMM(0xc0010000, REG_W0, imm);
885 /* stg %w0,off(%dst) */
886 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
887 jit->seen |= SEEN_MEM;
888 break;
889 /*
890 * BPF_STX XADD (atomic_add)
891 */
892 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
893 /* laal %w0,%src,off(%dst) */
894 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
895 dst_reg, off);
896 jit->seen |= SEEN_MEM;
897 break;
898 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
899 /* laalg %w0,%src,off(%dst) */
900 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
901 dst_reg, off);
902 jit->seen |= SEEN_MEM;
903 break;
904 /*
905 * BPF_LDX
906 */
907 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
908 /* llgc %dst,0(off,%src) */
909 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
910 jit->seen |= SEEN_MEM;
911 break;
912 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
913 /* llgh %dst,0(off,%src) */
914 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
915 jit->seen |= SEEN_MEM;
916 break;
917 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
918 /* llgf %dst,off(%src) */
919 jit->seen |= SEEN_MEM;
920 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
921 break;
922 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
923 /* lg %dst,0(off,%src) */
924 jit->seen |= SEEN_MEM;
925 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
926 break;
927 /*
928 * BPF_JMP / CALL
929 */
930 case BPF_JMP | BPF_CALL:
931 {
932 /*
933 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5)
934 */
935 const u64 func = (u64)__bpf_call_base + imm;
936
937 REG_SET_SEEN(BPF_REG_5);
938 jit->seen |= SEEN_FUNC;
939 /* lg %w1,<d(imm)>(%l) */
940 EMIT6_DISP(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
941 EMIT_CONST_U64(func));
942 /* basr %r14,%w1 */
943 EMIT2(0x0d00, REG_14, REG_W1);
944 /* lgr %b0,%r2: load return value into %b0 */
945 EMIT4(0xb9040000, BPF_REG_0, REG_2);
946 break;
947 }
948 case BPF_JMP | BPF_EXIT: /* return b0 */
949 last = (i == fp->len - 1) ? 1 : 0;
950 if (last && !(jit->seen & SEEN_RET0))
951 break;
c10302ef
MS		 952 /* j <exit> */
953 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
954 break;
05462310
MH		 955 /*
956 * Branch relative (number of skipped instructions) to offset on
957 * condition.
958 *
959 * Condition code to mask mapping:
960 *
961 * CC | Description | Mask
962 * ------------------------------
963 * 0 | Operands equal | 8
964 * 1 | First operand low | 4
965 * 2 | First operand high | 2
966 * 3 | Unused | 1
967 *
968 * For s390x relative branches: ip = ip + off_bytes
969 * For BPF relative branches: insn = insn + off_insns + 1
970 *
971 * For example for s390x with offset 0 we jump to the branch
972 * instruction itself (loop) and for BPF with offset 0 we
973 * branch to the instruction behind the branch.
974 */
975 case BPF_JMP | BPF_JA: /* if (true) */
976 mask = 0xf000; /* j */
977 goto branch_oc;
978 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
979 mask = 0x2000; /* jh */
980 goto branch_ks;
981 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
982 mask = 0xa000; /* jhe */
983 goto branch_ks;
984 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
985 mask = 0x2000; /* jh */
986 goto branch_ku;
987 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
988 mask = 0xa000; /* jhe */
989 goto branch_ku;
990 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
991 mask = 0x7000; /* jne */
992 goto branch_ku;
993 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
994 mask = 0x8000; /* je */
995 goto branch_ku;
996 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
997 mask = 0x7000; /* jnz */
998 /* lgfi %w1,imm (load sign extend imm) */
999 EMIT6_IMM(0xc0010000, REG_W1, imm);
1000 /* ngr %w1,%dst */
1001 EMIT4(0xb9800000, REG_W1, dst_reg);
1002 goto branch_oc;
1003
1004 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1005 mask = 0x2000; /* jh */
1006 goto branch_xs;
1007 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1008 mask = 0xa000; /* jhe */
1009 goto branch_xs;
1010 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1011 mask = 0x2000; /* jh */
1012 goto branch_xu;
1013 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1014 mask = 0xa000; /* jhe */
1015 goto branch_xu;
1016 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1017 mask = 0x7000; /* jne */
1018 goto branch_xu;
1019 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1020 mask = 0x8000; /* je */
1021 goto branch_xu;
1022 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1023 mask = 0x7000; /* jnz */
1024 /* ngrk %w1,%dst,%src */
1025 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg);
1026 goto branch_oc;
1027branch_ks:
1028 /* lgfi %w1,imm (load sign extend imm) */
1029 EMIT6_IMM(0xc0010000, REG_W1, imm);
1030 /* cgrj %dst,%w1,mask,off */
1031 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask);
1032 break;
1033branch_ku:
1034 /* lgfi %w1,imm (load sign extend imm) */
1035 EMIT6_IMM(0xc0010000, REG_W1, imm);
1036 /* clgrj %dst,%w1,mask,off */
1037 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask);
1038 break;
1039branch_xs:
1040 /* cgrj %dst,%src,mask,off */
1041 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask);
1042 break;
1043branch_xu:
1044 /* clgrj %dst,%src,mask,off */
1045 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask);
1046 break;
1047branch_oc:
1048 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1049 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1050 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
5303a0fe 1051 break;
05462310
MH		 1052 /*
1053 * BPF_LD
1054 */
1055 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */
1056 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */
1057 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1058 func_addr = __pa(sk_load_byte_pos);
1059 else
1060 func_addr = __pa(sk_load_byte);
1061 goto call_fn;
1062 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */
1063 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */
1064 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1065 func_addr = __pa(sk_load_half_pos);
1066 else
1067 func_addr = __pa(sk_load_half);
1068 goto call_fn;
1069 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */
1070 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */
1071 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0))
1072 func_addr = __pa(sk_load_word_pos);
1073 else
1074 func_addr = __pa(sk_load_word);
1075 goto call_fn;
1076call_fn:
1077 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC;
1078 REG_SET_SEEN(REG_14); /* Return address of possible func call */
1079
1080 /*
1081 * Implicit input:
1082 * BPF_REG_6 (R7) : skb pointer
1083 * REG_SKB_DATA (R12): skb data pointer
1084 *
1085 * Calculated input:
1086 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb
1087 * BPF_REG_5 (R6) : return address
1088 *
1089 * Output:
1090 * BPF_REG_0 (R14): data read from skb
1091 *
1092 * Scratch registers (BPF_REG_1-5)
1093 */
1094
1095 /* Call function: llilf %w1,func_addr */
1096 EMIT6_IMM(0xc00f0000, REG_W1, func_addr);
1097
1098 /* Offset: lgfi %b2,imm */
1099 EMIT6_IMM(0xc0010000, BPF_REG_2, imm);
1100 if (BPF_MODE(insn->code) == BPF_IND)
1101 /* agfr %b2,%src (%src is s32 here) */
1102 EMIT4(0xb9180000, BPF_REG_2, src_reg);
1103
1104 /* basr %b5,%w1 (%b5 is call saved) */
1105 EMIT2(0x0d00, BPF_REG_5, REG_W1);
1106
1107 /*
1108 * Note: For fast access we jump directly after the
1109 * jnz instruction from bpf_jit.S
1110 */
1111 /* jnz <ret0> */
1112 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg);
c10302ef
MS		 1113 break;
1114 default: /* too complex, give up */
05462310
MH		 1115 pr_err("Unknown opcode %02x\n", insn->code);
1116 return -1;
1117 }
1118 return insn_count;
1119}
1120
1121/*
1122 * Compile eBPF program into s390x code
1123 */
1124static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp)
1125{
1126 int i, insn_count;
1127
1128 jit->lit = jit->lit_start;
1129 jit->prg = 0;
1130
1131 bpf_jit_prologue(jit);
1132 for (i = 0; i < fp->len; i += insn_count) {
1133 insn_count = bpf_jit_insn(jit, fp, i);
1134 if (insn_count < 0)
1135 return -1;
1136 jit->addrs[i + 1] = jit->prg; /* Next instruction address */
c10302ef 1137 }
05462310
MH		 1138 bpf_jit_epilogue(jit);
1139
1140 jit->lit_start = jit->prg;
1141 jit->size = jit->lit;
1142 jit->size_prg = jit->prg;
c10302ef 1143 return 0;
c10302ef
MS		 1144}
1145
05462310
MH		 1146/*
1147 * Classic BPF function stub. BPF programs will be converted into
1148 * eBPF and then bpf_int_jit_compile() will be called.
1149 */
7ae457c1 1150void bpf_jit_compile(struct bpf_prog *fp)
c10302ef 1151{
05462310
MH		 1152}
1153
1154/*
1155 * Compile eBPF program "fp"
1156 */
1157void bpf_int_jit_compile(struct bpf_prog *fp)
1158{
1159 struct bpf_binary_header *header;
1160 struct bpf_jit jit;
1161 int pass;
c10302ef
MS		 1162
1163 if (!bpf_jit_enable)
1164 return;
05462310
MH		 1165 memset(&jit, 0, sizeof(jit));
1166 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1167 if (jit.addrs == NULL)
c10302ef 1168 return;
05462310
MH		 1169 /*
1170 * Three initial passes:
1171 * - 1/2: Determine clobbered registers
1172 * - 3: Calculate program size and addrs arrray
1173 */
1174 for (pass = 1; pass <= 3; pass++) {
1175 if (bpf_jit_prog(&jit, fp))
1176 goto free_addrs;
c10302ef 1177 }
05462310
MH		 1178 /*
1179 * Final pass: Allocate and generate program
1180 */
1181 if (jit.size >= BPF_SIZE_MAX)
1182 goto free_addrs;
1183 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1184 if (!header)
1185 goto free_addrs;
1186 if (bpf_jit_prog(&jit, fp))
1187 goto free_addrs;
c10302ef 1188 if (bpf_jit_enable > 1) {
05462310
MH		 1189 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1190 if (jit.prg_buf)
1191 print_fn_code(jit.prg_buf, jit.size_prg);
c10302ef 1192 }
05462310 1193 if (jit.prg_buf) {
aa2d2c73 1194 set_memory_ro((unsigned long)header, header->pages);
05462310 1195 fp->bpf_func = (void *) jit.prg_buf;
286aad3c 1196 fp->jited = true;
aa2d2c73 1197 }
05462310
MH		 1198free_addrs:
1199 kfree(jit.addrs);
c10302ef
MS		 1200}
1201
05462310
MH		 1202/*
1203 * Free eBPF program
1204 */
7ae457c1 1205void bpf_jit_free(struct bpf_prog *fp)
c10302ef 1206{
aa2d2c73
HC		 1207 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
1208 struct bpf_binary_header *header = (void *)addr;
1209
f8bbbfc3 1210 if (!fp->jited)
d45ed4a4 1211 goto free_filter;
f8bbbfc3 1212
aa2d2c73 1213 set_memory_rw(addr, header->pages);
738cbe72 1214 bpf_jit_binary_free(header);
f8bbbfc3 1215
d45ed4a4 1216free_filter:
60a3b225 1217 bpf_prog_unlock_free(fp);
c10302ef 1218}
Linux kernel - Deliverables
This page took 0.28446 seconds and 5 git commands to generate.