[deliverable/linux.git] / arch / sh / boards / board-ap325rxa.c

/*
 * Renesas - AP-325RXA
 * (Compatible with Algo System ., LTD. - AP-320A)
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Author : Yusuke Goda <goda.yuske@renesas.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/sh_flctl.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/smsc911x.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
#include <media/ov772x.h>
#include <media/soc_camera.h>
#include <media/soc_camera_platform.h>
#include <media/sh_mobile_ceu.h>
#include <video/sh_mobile_lcdc.h>
#include <asm/io.h>
#include <asm/clock.h>
#include <cpu/sh7723.h>

static struct smsc911x_platform_config smsc911x_config = {
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	.flags		= SMSC911X_USE_32BIT,
};

static struct resource smsc9118_resources[] = {
	[0] = {
		.start	= 0xb6080000,
		.end	= 0xb60fffff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 35,
		.end	= 35,
		.flags	= IORESOURCE_IRQ,
	}
};

static struct platform_device smsc9118_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc9118_resources),
	.resource	= smsc9118_resources,
	.dev		= {
		.platform_data = &smsc911x_config,
	},
};

/*
 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
 * If this area erased, this board can not boot.
 */
static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
	{
		.name = "uboot",
		.offset = 0,
		.size = (1 * 1024 * 1024),
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
	}, {
		.name = "kernel",
		.offset = MTDPART_OFS_APPEND,
		.size = (2 * 1024 * 1024),
	}, {
		.name = "free-area0",
		.offset = MTDPART_OFS_APPEND,
		.size = ((7 * 1024 * 1024) + (512 * 1024)),
	}, {
		.name = "CPLD-Data",
		.offset = MTDPART_OFS_APPEND,
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
		.size = (1024 * 128 * 2),
	}, {
		.name = "free-area1",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data ap325rxa_nor_flash_data = {
	.width		= 2,
	.parts		= ap325rxa_nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(ap325rxa_nor_flash_partitions),
};

static struct resource ap325rxa_nor_flash_resources[] = {
	[0] = {
		.name	= "NOR Flash",
		.start	= 0x00000000,
		.end	= 0x00ffffff,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device ap325rxa_nor_flash_device = {
	.name		= "physmap-flash",
	.resource	= ap325rxa_nor_flash_resources,
	.num_resources	= ARRAY_SIZE(ap325rxa_nor_flash_resources),
	.dev		= {
		.platform_data = &ap325rxa_nor_flash_data,
	},
};

static struct mtd_partition nand_partition_info[] = {
	{
		.name	= "nand_data",
		.offset	= 0,
		.size	= MTDPART_SIZ_FULL,
	},
};

static struct resource nand_flash_resources[] = {
	[0] = {
		.start	= 0xa4530000,
		.end	= 0xa45300ff,
		.flags	= IORESOURCE_MEM,
	}
};

static struct sh_flctl_platform_data nand_flash_data = {
	.parts		= nand_partition_info,
	.nr_parts	= ARRAY_SIZE(nand_partition_info),
	.flcmncr_val	= FCKSEL_E | TYPESEL_SET | NANWF_E,
	.has_hwecc	= 1,
};

static struct platform_device nand_flash_device = {
	.name		= "sh_flctl",
	.resource	= nand_flash_resources,
	.num_resources	= ARRAY_SIZE(nand_flash_resources),
	.dev		= {
		.platform_data = &nand_flash_data,
	},
};

#define FPGA_LCDREG	0xB4100180
#define FPGA_BKLREG	0xB4100212
#define FPGA_LCDREG_VAL	0x0018
#define PORT_MSELCRB	0xA4050182
#define PORT_HIZCRC	0xA405015C
#define PORT_DRVCRA	0xA405018A
#define PORT_DRVCRB	0xA405018C

static void ap320_wvga_power_on(void *board_data)
{
	msleep(100);

	/* ASD AP-320/325 LCD ON */
	ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);

	/* backlight */
	gpio_set_value(GPIO_PTS3, 0);
	ctrl_outw(0x100, FPGA_BKLREG);
}

static void ap320_wvga_power_off(void *board_data)
{
	/* backlight */
	ctrl_outw(0, FPGA_BKLREG);
	gpio_set_value(GPIO_PTS3, 1);

	/* ASD AP-320/325 LCD OFF */
	ctrl_outw(0, FPGA_LCDREG);
}

static struct sh_mobile_lcdc_info lcdc_info = {
	.clock_source = LCDC_CLK_EXTERNAL,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = RGB18,
		.clock_divider = 1,
		.lcd_cfg = {
			.name = "LB070WV1",
			.xres = 800,
			.yres = 480,
			.left_margin = 40,
			.right_margin = 160,
			.hsync_len = 8,
			.upper_margin = 63,
			.lower_margin = 80,
			.vsync_len = 1,
			.sync = 0, /* hsync and vsync are active low */
		},
		.lcd_size_cfg = { /* 7.0 inch */
			.width = 152,
			.height = 91,
		},
		.board_cfg = {
			.display_on = ap320_wvga_power_on,
			.display_off = ap320_wvga_power_off,
		},
	}
};

static struct resource lcdc_resources[] = {
	[0] = {
		.name	= "LCDC",
		.start	= 0xfe940000, /* P4-only space */
		.end	= 0xfe941fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 28,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device lcdc_device = {
	.name		= "sh_mobile_lcdc_fb",
	.num_resources	= ARRAY_SIZE(lcdc_resources),
	.resource	= lcdc_resources,
	.dev		= {
		.platform_data	= &lcdc_info,
	},
};

static void camera_power(int val)
{
	gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
	mdelay(10);
}

#ifdef CONFIG_I2C
/* support for the old ncm03j camera */
static unsigned char camera_ncm03j_magic[] =
{
	0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
	0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
	0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
	0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
	0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
	0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
	0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
	0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
	0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
	0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
	0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
	0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
	0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
	0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
	0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
	0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
};

static int camera_probe(void)
{
	struct i2c_adapter *a = i2c_get_adapter(0);
	struct i2c_msg msg;
	int ret;

	if (!a)
		return -ENODEV;

	camera_power(1);
	msg.addr = 0x6e;
	msg.buf = camera_ncm03j_magic;
	msg.len = 2;
	msg.flags = 0;
	ret = i2c_transfer(a, &msg, 1);
	camera_power(0);

	return ret;
}

static int camera_set_capture(struct soc_camera_platform_info *info,
			      int enable)
{
	struct i2c_adapter *a = i2c_get_adapter(0);
	struct i2c_msg msg;
	int ret = 0;
	int i;

	camera_power(0);
	if (!enable)
		return 0; /* no disable for now */

	camera_power(1);
	for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
		u_int8_t buf[8];

		msg.addr = 0x6e;
		msg.buf = buf;
		msg.len = 2;
		msg.flags = 0;

		buf[0] = camera_ncm03j_magic[i];
		buf[1] = camera_ncm03j_magic[i + 1];

		ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
	}

	return ret;
}

static struct soc_camera_platform_info camera_info = {
	.iface = 0,
	.format_name = "UYVY",
	.format_depth = 16,
	.format = {
		.pixelformat = V4L2_PIX_FMT_UYVY,
		.colorspace = V4L2_COLORSPACE_SMPTE170M,
		.width = 640,
		.height = 480,
	},
	.bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
	SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
	.set_capture = camera_set_capture,
};

static struct platform_device camera_device = {
	.name		= "soc_camera_platform",
	.dev		= {
		.platform_data	= &camera_info,
	},
};

static int __init camera_setup(void)
{
	if (camera_probe() > 0)
		platform_device_register(&camera_device);

	return 0;
}
late_initcall(camera_setup);

#endif /* CONFIG_I2C */

static int ov7725_power(struct device *dev, int mode)
{
	camera_power(0);
	if (mode)
		camera_power(1);

	return 0;
}

static struct ov772x_camera_info ov7725_info = {
	.buswidth  = SOCAM_DATAWIDTH_8,
	.flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
	.edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
	.link = {
		.power  = ov7725_power,
	},
};

static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};

static struct resource ceu_resources[] = {
	[0] = {
		.name	= "CEU",
		.start	= 0xfe910000,
		.end	= 0xfe91009f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = 52,
		.flags  = IORESOURCE_IRQ,
	},
	[2] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device ceu_device = {
	.name		= "sh_mobile_ceu",
	.id             = 0, /* "ceu0" clock */
	.num_resources	= ARRAY_SIZE(ceu_resources),
	.resource	= ceu_resources,
	.dev		= {
		.platform_data	= &sh_mobile_ceu_info,
	},
};

struct spi_gpio_platform_data sdcard_cn3_platform_data = {
	.sck = GPIO_PTD0,
	.mosi = GPIO_PTD1,
	.miso = GPIO_PTD2,
	.num_chipselect = 1,
};

static struct platform_device sdcard_cn3_device = {
	.name		= "spi_gpio",
	.dev	= {
		.platform_data	= &sdcard_cn3_platform_data,
	},
};

static struct platform_device *ap325rxa_devices[] __initdata = {
	&smsc9118_device,
	&ap325rxa_nor_flash_device,
	&lcdc_device,
	&ceu_device,
	&nand_flash_device,
	&sdcard_cn3_device,
};

static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
	{
		I2C_BOARD_INFO("pcf8563", 0x51),
	},
	{
		I2C_BOARD_INFO("ov772x", 0x21),
		.platform_data = &ov7725_info.link,
	},
};

static struct spi_board_info ap325rxa_spi_devices[] = {
	{
		.modalias = "mmc_spi",
		.max_speed_hz = 5000000,
		.chip_select = 0,
		.controller_data = (void *) GPIO_PTD5,
	},
};

static int __init ap325rxa_devices_setup(void)
{
	/* LD3 and LD4 LEDs */
	gpio_request(GPIO_PTX5, NULL); /* RUN */
	gpio_direction_output(GPIO_PTX5, 1);
	gpio_export(GPIO_PTX5, 0);

	gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
	gpio_direction_output(GPIO_PTX4, 0);
	gpio_export(GPIO_PTX4, 0);

	/* SW1 input */
	gpio_request(GPIO_PTF7, NULL); /* MODE */
	gpio_direction_input(GPIO_PTF7);
	gpio_export(GPIO_PTF7, 0);

	/* LCDC */
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD9, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDD0, NULL);
	gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
	gpio_request(GPIO_FN_LCDDCK, NULL);
	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	gpio_request(GPIO_FN_LCDVSYN, NULL);
	gpio_request(GPIO_FN_LCDHSYN, NULL);
	gpio_request(GPIO_FN_LCDDISP, NULL);
	gpio_request(GPIO_FN_LCDDON, NULL);

	/* LCD backlight */
	gpio_request(GPIO_PTS3, NULL);
	gpio_direction_output(GPIO_PTS3, 1);

	/* CEU */
	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	gpio_request(GPIO_FN_VIO_VD2, NULL);
	gpio_request(GPIO_FN_VIO_HD2, NULL);
	gpio_request(GPIO_FN_VIO_FLD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D15, NULL);
	gpio_request(GPIO_FN_VIO_D14, NULL);
	gpio_request(GPIO_FN_VIO_D13, NULL);
	gpio_request(GPIO_FN_VIO_D12, NULL);
	gpio_request(GPIO_FN_VIO_D11, NULL);
	gpio_request(GPIO_FN_VIO_D10, NULL);
	gpio_request(GPIO_FN_VIO_D9, NULL);
	gpio_request(GPIO_FN_VIO_D8, NULL);

	gpio_request(GPIO_PTZ7, NULL);
	gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
	gpio_request(GPIO_PTZ6, NULL);
	gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
	gpio_request(GPIO_PTZ5, NULL);
	gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
	gpio_request(GPIO_PTZ4, NULL);
	gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */

	ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);

	/* FLCTL */
	gpio_request(GPIO_FN_FCE, NULL);
	gpio_request(GPIO_FN_NAF7, NULL);
	gpio_request(GPIO_FN_NAF6, NULL);
	gpio_request(GPIO_FN_NAF5, NULL);
	gpio_request(GPIO_FN_NAF4, NULL);
	gpio_request(GPIO_FN_NAF3, NULL);
	gpio_request(GPIO_FN_NAF2, NULL);
	gpio_request(GPIO_FN_NAF1, NULL);
	gpio_request(GPIO_FN_NAF0, NULL);
	gpio_request(GPIO_FN_FCDE, NULL);
	gpio_request(GPIO_FN_FOE, NULL);
	gpio_request(GPIO_FN_FSC, NULL);
	gpio_request(GPIO_FN_FWE, NULL);
	gpio_request(GPIO_FN_FRB, NULL);

	ctrl_outw(0, PORT_HIZCRC);
	ctrl_outw(0xFFFF, PORT_DRVCRA);
	ctrl_outw(0xFFFF, PORT_DRVCRB);

	platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);

	i2c_register_board_info(0, ap325rxa_i2c_devices,
				ARRAY_SIZE(ap325rxa_i2c_devices));

	spi_register_board_info(ap325rxa_spi_devices,
				ARRAY_SIZE(ap325rxa_spi_devices));

	return platform_add_devices(ap325rxa_devices,
				ARRAY_SIZE(ap325rxa_devices));
}
device_initcall(ap325rxa_devices_setup);

/* Return the board specific boot mode pin configuration */
static int ap325rxa_mode_pins(void)
{
	/* MD0=0, MD1=0, MD2=0: Clock Mode 0
	 * MD3=0: 16-bit Area0 Bus Width
	 * MD5=1: Little Endian
	 * TSTMD=1, MD8=1: Test Mode Disabled
	 */
	return MODE_PIN5 | MODE_PIN8;
}

static struct sh_machine_vector mv_ap325rxa __initmv = {
	.mv_name = "AP-325RXA",
	.mv_mode_pins = ap325rxa_mode_pins,
};
Commit	Line	Data
04e917b6 YG	1	/*
	2	* Renesas - AP-325RXA
	3	* (Compatible with Algo System ., LTD. - AP-320A)
	4	*
	5	* Copyright (C) 2008 Renesas Solutions Corp.
	6	* Author : Yusuke Goda <goda.yuske@renesas.com>
	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/device.h>
4875ea22	15	#include <linux/interrupt.h>
04e917b6 YG	16	#include <linux/platform_device.h>
04e917b6 YG	17	#include <linux/mtd/physmap.h>
908978ac	18	#include <linux/mtd/sh_flctl.h>
04e917b6	19	#include <linux/delay.h>
026953db	20	#include <linux/i2c.h>
90b76491	21	#include <linux/smsc911x.h>
16587c45	22	#include <linux/gpio.h>
fbdd9a70 MD	23	#include <linux/spi/spi.h>
fbdd9a70 MD	24	#include <linux/spi/spi_gpio.h>
47131258	25	#include <media/ov772x.h>
ba087e6f	26	#include <media/soc_camera.h>
8b2224dc MD	27	#include <media/soc_camera_platform.h>
8b2224dc MD	28	#include <media/sh_mobile_ceu.h>
225c9a8d	29	#include <video/sh_mobile_lcdc.h>
04e917b6	30	#include <asm/io.h>
6968980a	31	#include <asm/clock.h>
f7275650	32	#include <cpu/sh7723.h>
04e917b6	33
90b76491 SG	34	static struct smsc911x_platform_config smsc911x_config = {
	35	.phy_interface = PHY_INTERFACE_MODE_MII,
	36	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	37	.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	38	.flags = SMSC911X_USE_32BIT,
4875ea22 MD	39	};
4875ea22 MD	40
90b76491	41	static struct resource smsc9118_resources[] = {
04e917b6 YG	42	[0] = {
	43	.start = 0xb6080000,
	44	.end = 0xb60fffff,
	45	.flags = IORESOURCE_MEM,
	46	},
	47	[1] = {
	48	.start = 35,
	49	.end = 35,
	50	.flags = IORESOURCE_IRQ,
	51	}
	52	};
	53
90b76491 SG	54	static struct platform_device smsc9118_device = {
90b76491 SG	55	.name = "smsc911x",
04e917b6	56	.id = -1,
90b76491 SG	57	.num_resources = ARRAY_SIZE(smsc9118_resources),
90b76491 SG	58	.resource = smsc9118_resources,
4875ea22	59	.dev = {
90b76491	60	.platform_data = &smsc911x_config,
4875ea22	61	},
04e917b6 YG	62	};
04e917b6 YG	63
aa88f169 NI	64	/*
	65	* AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
	66	* If this area erased, this board can not boot.
	67	*/
04e917b6 YG	68	static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
04e917b6 YG	69	{
aa88f169 NI	70	.name = "uboot",
	71	.offset = 0,
	72	.size = (1 * 1024 * 1024),
	73	.mask_flags = MTD_WRITEABLE, /* Read-only */
	74	}, {
	75	.name = "kernel",
	76	.offset = MTDPART_OFS_APPEND,
	77	.size = (2 * 1024 * 1024),
	78	}, {
	79	.name = "free-area0",
	80	.offset = MTDPART_OFS_APPEND,
	81	.size = ((7 * 1024 * 1024) + (512 * 1024)),
04e917b6	82	}, {
aa88f169 NI	83	.name = "CPLD-Data",
	84	.offset = MTDPART_OFS_APPEND,
	85	.mask_flags = MTD_WRITEABLE, /* Read-only */
	86	.size = (1024 * 128 * 2),
04e917b6	87	}, {
aa88f169 NI	88	.name = "free-area1",
	89	.offset = MTDPART_OFS_APPEND,
	90	.size = MTDPART_SIZ_FULL,
04e917b6 YG	91	},
	92	};
	93
	94	static struct physmap_flash_data ap325rxa_nor_flash_data = {
	95	.width = 2,
	96	.parts = ap325rxa_nor_flash_partitions,
	97	.nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
	98	};
	99
	100	static struct resource ap325rxa_nor_flash_resources[] = {
	101	[0] = {
	102	.name = "NOR Flash",
	103	.start = 0x00000000,
	104	.end = 0x00ffffff,
	105	.flags = IORESOURCE_MEM,
	106	}
	107	};
	108
	109	static struct platform_device ap325rxa_nor_flash_device = {
	110	.name = "physmap-flash",
	111	.resource = ap325rxa_nor_flash_resources,
	112	.num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
	113	.dev = {
	114	.platform_data = &ap325rxa_nor_flash_data,
	115	},
	116	};
	117
908978ac YS	118	static struct mtd_partition nand_partition_info[] = {
	119	{
	120	.name = "nand_data",
	121	.offset = 0,
	122	.size = MTDPART_SIZ_FULL,
	123	},
	124	};
	125
	126	static struct resource nand_flash_resources[] = {
	127	[0] = {
	128	.start = 0xa4530000,
	129	.end = 0xa45300ff,
	130	.flags = IORESOURCE_MEM,
	131	}
	132	};
	133
	134	static struct sh_flctl_platform_data nand_flash_data = {
	135	.parts = nand_partition_info,
	136	.nr_parts = ARRAY_SIZE(nand_partition_info),
	137	.flcmncr_val = FCKSEL_E \| TYPESEL_SET \| NANWF_E,
	138	.has_hwecc = 1,
	139	};
	140
	141	static struct platform_device nand_flash_device = {
	142	.name = "sh_flctl",
	143	.resource = nand_flash_resources,
	144	.num_resources = ARRAY_SIZE(nand_flash_resources),
	145	.dev = {
	146	.platform_data = &nand_flash_data,
	147	},
	148	};
	149
6968980a MD	150	#define FPGA_LCDREG 0xB4100180
	151	#define FPGA_BKLREG 0xB4100212
	152	#define FPGA_LCDREG_VAL 0x0018
8b2224dc	153	#define PORT_MSELCRB 0xA4050182
908978ac YS	154	#define PORT_HIZCRC 0xA405015C
	155	#define PORT_DRVCRA 0xA405018A
	156	#define PORT_DRVCRB 0xA405018C
6968980a MD	157
	158	static void ap320_wvga_power_on(void *board_data)
	159	{
	160	msleep(100);
	161
	162	/* ASD AP-320/325 LCD ON */
	163	ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
	164
	165	/* backlight */
16587c45	166	gpio_set_value(GPIO_PTS3, 0);
6968980a MD	167	ctrl_outw(0x100, FPGA_BKLREG);
	168	}
	169
93356d07 MD	170	static void ap320_wvga_power_off(void *board_data)
	171	{
	172	/* backlight */
	173	ctrl_outw(0, FPGA_BKLREG);
	174	gpio_set_value(GPIO_PTS3, 1);
	175
	176	/* ASD AP-320/325 LCD OFF */
	177	ctrl_outw(0, FPGA_LCDREG);
	178	}
	179
6968980a MD	180	static struct sh_mobile_lcdc_info lcdc_info = {
	181	.clock_source = LCDC_CLK_EXTERNAL,
	182	.ch[0] = {
	183	.chan = LCDC_CHAN_MAINLCD,
	184	.bpp = 16,
	185	.interface_type = RGB18,
	186	.clock_divider = 1,
	187	.lcd_cfg = {
	188	.name = "LB070WV1",
	189	.xres = 800,
	190	.yres = 480,
	191	.left_margin = 40,
	192	.right_margin = 160,
	193	.hsync_len = 8,
	194	.upper_margin = 63,
	195	.lower_margin = 80,
	196	.vsync_len = 1,
	197	.sync = 0, /* hsync and vsync are active low */
	198	},
ce9c008c MD	199	.lcd_size_cfg = { /* 7.0 inch */
	200	.width = 152,
	201	.height = 91,
	202	},
6968980a MD	203	.board_cfg = {
6968980a MD	204	.display_on = ap320_wvga_power_on,
93356d07	205	.display_off = ap320_wvga_power_off,
6968980a MD	206	},
	207	}
	208	};
	209
	210	static struct resource lcdc_resources[] = {
	211	[0] = {
	212	.name = "LCDC",
	213	.start = 0xfe940000, /* P4-only space */
	214	.end = 0xfe941fff,
	215	.flags = IORESOURCE_MEM,
	216	},
07905554 MD	217	[1] = {
	218	.start = 28,
	219	.flags = IORESOURCE_IRQ,
	220	},
6968980a MD	221	};
	222
	223	static struct platform_device lcdc_device = {
	224	.name = "sh_mobile_lcdc_fb",
	225	.num_resources = ARRAY_SIZE(lcdc_resources),
	226	.resource = lcdc_resources,
	227	.dev = {
	228	.platform_data = &lcdc_info,
	229	},
	230	};
	231
86746284 KM	232	static void camera_power(int val)
	233	{
	234	gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
	235	mdelay(10);
	236	}
	237
e565b518	238	#ifdef CONFIG_I2C
47131258	239	/* support for the old ncm03j camera */
8b2224dc MD	240	static unsigned char camera_ncm03j_magic[] =
	241	{
	242	0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
	243	0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
	244	0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
	245	0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
	246	0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
	247	0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
	248	0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
	249	0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
	250	0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
	251	0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
	252	0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
	253	0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
	254	0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
	255	0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
	256	0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
	257	0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
	258	};
	259
47131258 KM	260	static int camera_probe(void)
	261	{
	262	struct i2c_adapter *a = i2c_get_adapter(0);
	263	struct i2c_msg msg;
	264	int ret;
	265
37869fa2 MD	266	if (!a)
	267	return -ENODEV;
	268
47131258 KM	269	camera_power(1);
	270	msg.addr = 0x6e;
	271	msg.buf = camera_ncm03j_magic;
	272	msg.len = 2;
	273	msg.flags = 0;
	274	ret = i2c_transfer(a, &msg, 1);
	275	camera_power(0);
	276
	277	return ret;
	278	}
	279
8b2224dc MD	280	static int camera_set_capture(struct soc_camera_platform_info *info,
	281	int enable)
	282	{
	283	struct i2c_adapter *a = i2c_get_adapter(0);
	284	struct i2c_msg msg;
	285	int ret = 0;
	286	int i;
	287
86746284	288	camera_power(0);
8b2224dc MD	289	if (!enable)
	290	return 0; /* no disable for now */
	291
86746284	292	camera_power(1);
8b2224dc MD	293	for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
	294	u_int8_t buf[8];
	295
	296	msg.addr = 0x6e;
	297	msg.buf = buf;
	298	msg.len = 2;
	299	msg.flags = 0;
	300
	301	buf[0] = camera_ncm03j_magic[i];
	302	buf[1] = camera_ncm03j_magic[i + 1];
	303
	304	ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
	305	}
	306
	307	return ret;
	308	}
	309
	310	static struct soc_camera_platform_info camera_info = {
	311	.iface = 0,
	312	.format_name = "UYVY",
	313	.format_depth = 16,
	314	.format = {
	315	.pixelformat = V4L2_PIX_FMT_UYVY,
	316	.colorspace = V4L2_COLORSPACE_SMPTE170M,
	317	.width = 640,
	318	.height = 480,
	319	},
	320	.bus_param = SOCAM_PCLK_SAMPLE_RISING \| SOCAM_HSYNC_ACTIVE_HIGH \|
	321	SOCAM_VSYNC_ACTIVE_HIGH \| SOCAM_MASTER \| SOCAM_DATAWIDTH_8,
	322	.set_capture = camera_set_capture,
	323	};
	324
	325	static struct platform_device camera_device = {
	326	.name = "soc_camera_platform",
	327	.dev = {
	328	.platform_data = &camera_info,
	329	},
	330	};
47131258 KM	331
	332	static int __init camera_setup(void)
	333	{
	334	if (camera_probe() > 0)
	335	platform_device_register(&camera_device);
	336
	337	return 0;
	338	}
	339	late_initcall(camera_setup);
	340
e565b518	341	#endif /* CONFIG_I2C */
8b2224dc	342
47131258 KM	343	static int ov7725_power(struct device *dev, int mode)
	344	{
	345	camera_power(0);
	346	if (mode)
	347	camera_power(1);
	348
	349	return 0;
	350	}
	351
	352	static struct ov772x_camera_info ov7725_info = {
	353	.buswidth = SOCAM_DATAWIDTH_8,
	354	.flags = OV772X_FLAG_VFLIP \| OV772X_FLAG_HFLIP,
fc3f55e6	355	.edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
47131258 KM	356	.link = {
	357	.power = ov7725_power,
	358	},
	359	};
	360
8b2224dc	361	static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
46368fa0	362	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
8b2224dc MD	363	};
	364
	365	static struct resource ceu_resources[] = {
	366	[0] = {
	367	.name = "CEU",
	368	.start = 0xfe910000,
	369	.end = 0xfe91009f,
	370	.flags = IORESOURCE_MEM,
	371	},
	372	[1] = {
	373	.start = 52,
	374	.flags = IORESOURCE_IRQ,
	375	},
	376	[2] = {
	377	/* place holder for contiguous memory */
	378	},
	379	};
	380
	381	static struct platform_device ceu_device = {
	382	.name = "sh_mobile_ceu",
a42b6dd6	383	.id = 0, /* "ceu0" clock */
8b2224dc MD	384	.num_resources = ARRAY_SIZE(ceu_resources),
	385	.resource = ceu_resources,
	386	.dev = {
	387	.platform_data = &sh_mobile_ceu_info,
	388	},
	389	};
	390
fbdd9a70 MD	391	struct spi_gpio_platform_data sdcard_cn3_platform_data = {
	392	.sck = GPIO_PTD0,
	393	.mosi = GPIO_PTD1,
	394	.miso = GPIO_PTD2,
	395	.num_chipselect = 1,
	396	};
	397
	398	static struct platform_device sdcard_cn3_device = {
	399	.name = "spi_gpio",
	400	.dev = {
	401	.platform_data = &sdcard_cn3_platform_data,
	402	},
	403	};
	404
04e917b6	405	static struct platform_device *ap325rxa_devices[] __initdata = {
90b76491	406	&smsc9118_device,
6968980a MD	407	&ap325rxa_nor_flash_device,
6968980a MD	408	&lcdc_device,
8b2224dc	409	&ceu_device,
908978ac	410	&nand_flash_device,
fbdd9a70	411	&sdcard_cn3_device,
04e917b6 YG	412	};
04e917b6 YG	413
026953db	414	static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
a3e02706 NI	415	{
	416	I2C_BOARD_INFO("pcf8563", 0x51),
	417	},
47131258 KM	418	{
47131258 KM	419	I2C_BOARD_INFO("ov772x", 0x21),
0a861e9e	420	.platform_data = &ov7725_info.link,
47131258	421	},
026953db MD	422	};
026953db MD	423
fbdd9a70 MD	424	static struct spi_board_info ap325rxa_spi_devices[] = {
	425	{
	426	.modalias = "mmc_spi",
	427	.max_speed_hz = 5000000,
	428	.chip_select = 0,
	429	.controller_data = (void *) GPIO_PTD5,
	430	},
	431	};
	432
04e917b6 YG	433	static int __init ap325rxa_devices_setup(void)
04e917b6 YG	434	{
16587c45 MD	435	/* LD3 and LD4 LEDs */
	436	gpio_request(GPIO_PTX5, NULL); /* RUN */
	437	gpio_direction_output(GPIO_PTX5, 1);
	438	gpio_export(GPIO_PTX5, 0);
	439
	440	gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
	441	gpio_direction_output(GPIO_PTX4, 0);
	442	gpio_export(GPIO_PTX4, 0);
	443
	444	/* SW1 input */
	445	gpio_request(GPIO_PTF7, NULL); /* MODE */
	446	gpio_direction_input(GPIO_PTF7);
	447	gpio_export(GPIO_PTF7, 0);
	448
	449	/* LCDC */
16587c45 MD	450	gpio_request(GPIO_FN_LCDD15, NULL);
	451	gpio_request(GPIO_FN_LCDD14, NULL);
	452	gpio_request(GPIO_FN_LCDD13, NULL);
	453	gpio_request(GPIO_FN_LCDD12, NULL);
	454	gpio_request(GPIO_FN_LCDD11, NULL);
	455	gpio_request(GPIO_FN_LCDD10, NULL);
	456	gpio_request(GPIO_FN_LCDD9, NULL);
	457	gpio_request(GPIO_FN_LCDD8, NULL);
	458	gpio_request(GPIO_FN_LCDD7, NULL);
	459	gpio_request(GPIO_FN_LCDD6, NULL);
	460	gpio_request(GPIO_FN_LCDD5, NULL);
	461	gpio_request(GPIO_FN_LCDD4, NULL);
	462	gpio_request(GPIO_FN_LCDD3, NULL);
	463	gpio_request(GPIO_FN_LCDD2, NULL);
	464	gpio_request(GPIO_FN_LCDD1, NULL);
	465	gpio_request(GPIO_FN_LCDD0, NULL);
	466	gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
	467	gpio_request(GPIO_FN_LCDDCK, NULL);
	468	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	469	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	470	gpio_request(GPIO_FN_LCDVSYN, NULL);
	471	gpio_request(GPIO_FN_LCDHSYN, NULL);
	472	gpio_request(GPIO_FN_LCDDISP, NULL);
	473	gpio_request(GPIO_FN_LCDDON, NULL);
	474
	475	/* LCD backlight */
	476	gpio_request(GPIO_PTS3, NULL);
	477	gpio_direction_output(GPIO_PTS3, 1);
	478
	479	/* CEU */
16587c45 MD	480	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	481	gpio_request(GPIO_FN_VIO_VD2, NULL);
	482	gpio_request(GPIO_FN_VIO_HD2, NULL);
	483	gpio_request(GPIO_FN_VIO_FLD, NULL);
	484	gpio_request(GPIO_FN_VIO_CKO, NULL);
	485	gpio_request(GPIO_FN_VIO_D15, NULL);
	486	gpio_request(GPIO_FN_VIO_D14, NULL);
	487	gpio_request(GPIO_FN_VIO_D13, NULL);
	488	gpio_request(GPIO_FN_VIO_D12, NULL);
	489	gpio_request(GPIO_FN_VIO_D11, NULL);
	490	gpio_request(GPIO_FN_VIO_D10, NULL);
	491	gpio_request(GPIO_FN_VIO_D9, NULL);
	492	gpio_request(GPIO_FN_VIO_D8, NULL);
	493
	494	gpio_request(GPIO_PTZ7, NULL);
	495	gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
	496	gpio_request(GPIO_PTZ6, NULL);
	497	gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
	498	gpio_request(GPIO_PTZ5, NULL);
86746284	499	gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
16587c45 MD	500	gpio_request(GPIO_PTZ4, NULL);
	501	gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
	502
	503	ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
8b2224dc	504
908978ac	505	/* FLCTL */
dd0e20e5 PM	506	gpio_request(GPIO_FN_FCE, NULL);
	507	gpio_request(GPIO_FN_NAF7, NULL);
	508	gpio_request(GPIO_FN_NAF6, NULL);
	509	gpio_request(GPIO_FN_NAF5, NULL);
	510	gpio_request(GPIO_FN_NAF4, NULL);
	511	gpio_request(GPIO_FN_NAF3, NULL);
	512	gpio_request(GPIO_FN_NAF2, NULL);
	513	gpio_request(GPIO_FN_NAF1, NULL);
	514	gpio_request(GPIO_FN_NAF0, NULL);
	515	gpio_request(GPIO_FN_FCDE, NULL);
	516	gpio_request(GPIO_FN_FOE, NULL);
	517	gpio_request(GPIO_FN_FSC, NULL);
	518	gpio_request(GPIO_FN_FWE, NULL);
	519	gpio_request(GPIO_FN_FRB, NULL);
908978ac YS	520
	521	ctrl_outw(0, PORT_HIZCRC);
	522	ctrl_outw(0xFFFF, PORT_DRVCRA);
	523	ctrl_outw(0xFFFF, PORT_DRVCRB);
	524
8b2224dc	525	platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
6968980a	526
026953db MD	527	i2c_register_board_info(0, ap325rxa_i2c_devices,
026953db MD	528	ARRAY_SIZE(ap325rxa_i2c_devices));
908978ac	529
fbdd9a70 MD	530	spi_register_board_info(ap325rxa_spi_devices,
	531	ARRAY_SIZE(ap325rxa_spi_devices));
	532
04e917b6 YG	533	return platform_add_devices(ap325rxa_devices,
	534	ARRAY_SIZE(ap325rxa_devices));
	535	}
	536	device_initcall(ap325rxa_devices_setup);
	537
c01641b4 MD	538	/* Return the board specific boot mode pin configuration */
	539	static int ap325rxa_mode_pins(void)
	540	{
	541	/* MD0=0, MD1=0, MD2=0: Clock Mode 0
	542	* MD3=0: 16-bit Area0 Bus Width
	543	* MD5=1: Little Endian
	544	* TSTMD=1, MD8=1: Test Mode Disabled
	545	*/
	546	return MODE_PIN5 \| MODE_PIN8;
	547	}
	548
04e917b6 YG	549	static struct sh_machine_vector mv_ap325rxa __initmv = {
04e917b6 YG	550	.mv_name = "AP-325RXA",
c01641b4	551	.mv_mode_pins = ap325rxa_mode_pins,
04e917b6	552	};