[deliverable/linux.git] / arch / sh / boards / board-sh7757lcr.c

/*
 * Renesas R0P7757LC0012RL Support.
 *
 * Copyright (C) 2009 - 2010  Renesas Solutions Corp.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/io.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <linux/usb/renesas_usbhs.h>
#include <cpu/sh7757.h>
#include <asm/heartbeat.h>

static struct resource heartbeat_resource = {
	.start	= 0xffec005c,	/* PUDR */
	.end	= 0xffec005c,
	.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
};

static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };

static struct heartbeat_data heartbeat_data = {
	.bit_pos	= heartbeat_bit_pos,
	.nr_bits	= ARRAY_SIZE(heartbeat_bit_pos),
	.flags		= HEARTBEAT_INVERTED,
};

static struct platform_device heartbeat_device = {
	.name		= "heartbeat",
	.id		= -1,
	.dev	= {
		.platform_data	= &heartbeat_data,
	},
	.num_resources	= 1,
	.resource	= &heartbeat_resource,
};

/* Fast Ethernet */
#define GBECONT		0xffc10100
#define GBECONT_RMII1	BIT(17)
#define GBECONT_RMII0	BIT(16)
static void sh7757_eth_set_mdio_gate(void *addr)
{
	if (((unsigned long)addr & 0x00000fff) < 0x0800)
		writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
	else
		writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
}

static struct resource sh_eth0_resources[] = {
	{
		.start  = 0xfef00000,
		.end    = 0xfef001ff,
		.flags  = IORESOURCE_MEM,
	}, {
		.start  = evt2irq(0xc80),
		.end    = evt2irq(0xc80),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct sh_eth_plat_data sh7757_eth0_pdata = {
	.phy = 1,
	.edmac_endian = EDMAC_LITTLE_ENDIAN,
	.set_mdio_gate = sh7757_eth_set_mdio_gate,
};

static struct platform_device sh7757_eth0_device = {
	.name		= "sh7757-ether",
	.resource	= sh_eth0_resources,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(sh_eth0_resources),
	.dev		= {
		.platform_data = &sh7757_eth0_pdata,
	},
};

static struct resource sh_eth1_resources[] = {
	{
		.start  = 0xfef00800,
		.end    = 0xfef009ff,
		.flags  = IORESOURCE_MEM,
	}, {
		.start  = evt2irq(0xc80),
		.end    = evt2irq(0xc80),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct sh_eth_plat_data sh7757_eth1_pdata = {
	.phy = 1,
	.edmac_endian = EDMAC_LITTLE_ENDIAN,
	.set_mdio_gate = sh7757_eth_set_mdio_gate,
};

static struct platform_device sh7757_eth1_device = {
	.name		= "sh7757-ether",
	.resource	= sh_eth1_resources,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(sh_eth1_resources),
	.dev		= {
		.platform_data = &sh7757_eth1_pdata,
	},
};

static void sh7757_eth_giga_set_mdio_gate(void *addr)
{
	if (((unsigned long)addr & 0x00000fff) < 0x0800) {
		gpio_set_value(GPIO_PTT4, 1);
		writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
	} else {
		gpio_set_value(GPIO_PTT4, 0);
		writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
	}
}

static struct resource sh_eth_giga0_resources[] = {
	{
		.start  = 0xfee00000,
		.end    = 0xfee007ff,
		.flags  = IORESOURCE_MEM,
	}, {
		/* TSU */
		.start  = 0xfee01800,
		.end    = 0xfee01fff,
		.flags  = IORESOURCE_MEM,
	}, {
		.start  = evt2irq(0x2960),
		.end    = evt2irq(0x2960),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
	.phy = 18,
	.edmac_endian = EDMAC_LITTLE_ENDIAN,
	.set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
	.phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
};

static struct platform_device sh7757_eth_giga0_device = {
	.name		= "sh7757-gether",
	.resource	= sh_eth_giga0_resources,
	.id		= 2,
	.num_resources	= ARRAY_SIZE(sh_eth_giga0_resources),
	.dev		= {
		.platform_data = &sh7757_eth_giga0_pdata,
	},
};

static struct resource sh_eth_giga1_resources[] = {
	{
		.start  = 0xfee00800,
		.end    = 0xfee00fff,
		.flags  = IORESOURCE_MEM,
	}, {
		/* TSU */
		.start  = 0xfee01800,
		.end    = 0xfee01fff,
		.flags  = IORESOURCE_MEM,
	}, {
		.start  = evt2irq(0x2980),
		.end    = evt2irq(0x2980),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
	.phy = 19,
	.edmac_endian = EDMAC_LITTLE_ENDIAN,
	.set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
	.phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
};

static struct platform_device sh7757_eth_giga1_device = {
	.name		= "sh7757-gether",
	.resource	= sh_eth_giga1_resources,
	.id		= 3,
	.num_resources	= ARRAY_SIZE(sh_eth_giga1_resources),
	.dev		= {
		.platform_data = &sh7757_eth_giga1_pdata,
	},
};

/* Fixed 3.3V regulator to be used by SDHI0, MMCIF */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
	REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
	REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
};

/* SH_MMCIF */
static struct resource sh_mmcif_resources[] = {
	[0] = {
		.start	= 0xffcb0000,
		.end	= 0xffcb00ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x1c60),
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		.start	= evt2irq(0x1c80),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct sh_mmcif_plat_data sh_mmcif_plat = {
	.sup_pclk	= 0x0f,
	.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
			  MMC_CAP_NONREMOVABLE,
	.ocr		= MMC_VDD_32_33 | MMC_VDD_33_34,
	.slave_id_tx	= SHDMA_SLAVE_MMCIF_TX,
	.slave_id_rx	= SHDMA_SLAVE_MMCIF_RX,
};

static struct platform_device sh_mmcif_device = {
	.name		= "sh_mmcif",
	.id		= 0,
	.dev		= {
		.platform_data		= &sh_mmcif_plat,
	},
	.num_resources	= ARRAY_SIZE(sh_mmcif_resources),
	.resource	= sh_mmcif_resources,
};

/* SDHI0 */
static struct tmio_mmc_data sdhi_info = {
	.chan_priv_tx	= (void *)SHDMA_SLAVE_SDHI_TX,
	.chan_priv_rx	= (void *)SHDMA_SLAVE_SDHI_RX,
	.capabilities	= MMC_CAP_SD_HIGHSPEED,
};

static struct resource sdhi_resources[] = {
	[0] = {
		.start  = 0xffe50000,
		.end    = 0xffe500ff,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0x480),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device sdhi_device = {
	.name           = "sh_mobile_sdhi",
	.num_resources  = ARRAY_SIZE(sdhi_resources),
	.resource       = sdhi_resources,
	.id             = 0,
	.dev	= {
		.platform_data	= &sdhi_info,
	},
};

static int usbhs0_get_id(struct platform_device *pdev)
{
	return USBHS_GADGET;
}

static struct renesas_usbhs_platform_info usb0_data = {
	.platform_callback = {
		.get_id = usbhs0_get_id,
	},
	.driver_param = {
		.buswait_bwait = 5,
	}
};

static struct resource usb0_resources[] = {
	[0] = {
		.start	= 0xfe450000,
		.end	= 0xfe4501ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x840),
		.end	= evt2irq(0x840),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device usb0_device = {
	.name		= "renesas_usbhs",
	.id		= 0,
	.dev = {
		.platform_data		= &usb0_data,
	},
	.num_resources	= ARRAY_SIZE(usb0_resources),
	.resource	= usb0_resources,
};

static struct platform_device *sh7757lcr_devices[] __initdata = {
	&heartbeat_device,
	&sh7757_eth0_device,
	&sh7757_eth1_device,
	&sh7757_eth_giga0_device,
	&sh7757_eth_giga1_device,
	&sh_mmcif_device,
	&sdhi_device,
	&usb0_device,
};

static struct flash_platform_data spi_flash_data = {
	.name = "m25p80",
	.type = "m25px64",
};

static struct spi_board_info spi_board_info[] = {
	{
		.modalias = "m25p80",
		.max_speed_hz = 25000000,
		.bus_num = 0,
		.chip_select = 1,
		.platform_data = &spi_flash_data,
	},
};

static int __init sh7757lcr_devices_setup(void)
{
	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
				     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);

	/* RGMII (PTA) */
	gpio_request(GPIO_FN_ET0_MDC, NULL);
	gpio_request(GPIO_FN_ET0_MDIO, NULL);
	gpio_request(GPIO_FN_ET1_MDC, NULL);
	gpio_request(GPIO_FN_ET1_MDIO, NULL);

	/* ONFI (PTB, PTZ) */
	gpio_request(GPIO_FN_ON_NRE, NULL);
	gpio_request(GPIO_FN_ON_NWE, NULL);
	gpio_request(GPIO_FN_ON_NWP, NULL);
	gpio_request(GPIO_FN_ON_NCE0, NULL);
	gpio_request(GPIO_FN_ON_R_B0, NULL);
	gpio_request(GPIO_FN_ON_ALE, NULL);
	gpio_request(GPIO_FN_ON_CLE, NULL);

	gpio_request(GPIO_FN_ON_DQ7, NULL);
	gpio_request(GPIO_FN_ON_DQ6, NULL);
	gpio_request(GPIO_FN_ON_DQ5, NULL);
	gpio_request(GPIO_FN_ON_DQ4, NULL);
	gpio_request(GPIO_FN_ON_DQ3, NULL);
	gpio_request(GPIO_FN_ON_DQ2, NULL);
	gpio_request(GPIO_FN_ON_DQ1, NULL);
	gpio_request(GPIO_FN_ON_DQ0, NULL);

	/* IRQ8 to 0 (PTB, PTC) */
	gpio_request(GPIO_FN_IRQ8, NULL);
	gpio_request(GPIO_FN_IRQ7, NULL);
	gpio_request(GPIO_FN_IRQ6, NULL);
	gpio_request(GPIO_FN_IRQ5, NULL);
	gpio_request(GPIO_FN_IRQ4, NULL);
	gpio_request(GPIO_FN_IRQ3, NULL);
	gpio_request(GPIO_FN_IRQ2, NULL);
	gpio_request(GPIO_FN_IRQ1, NULL);
	gpio_request(GPIO_FN_IRQ0, NULL);

	/* SPI0 (PTD) */
	gpio_request(GPIO_FN_SP0_MOSI, NULL);
	gpio_request(GPIO_FN_SP0_MISO, NULL);
	gpio_request(GPIO_FN_SP0_SCK, NULL);
	gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
	gpio_request(GPIO_FN_SP0_SS0, NULL);
	gpio_request(GPIO_FN_SP0_SS1, NULL);
	gpio_request(GPIO_FN_SP0_SS2, NULL);
	gpio_request(GPIO_FN_SP0_SS3, NULL);

	/* RMII 0/1 (PTE, PTF) */
	gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
	gpio_request(GPIO_FN_RMII0_TXD1, NULL);
	gpio_request(GPIO_FN_RMII0_TXD0, NULL);
	gpio_request(GPIO_FN_RMII0_TXEN, NULL);
	gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
	gpio_request(GPIO_FN_RMII0_RXD1, NULL);
	gpio_request(GPIO_FN_RMII0_RXD0, NULL);
	gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
	gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
	gpio_request(GPIO_FN_RMII1_TXD1, NULL);
	gpio_request(GPIO_FN_RMII1_TXD0, NULL);
	gpio_request(GPIO_FN_RMII1_TXEN, NULL);
	gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
	gpio_request(GPIO_FN_RMII1_RXD1, NULL);
	gpio_request(GPIO_FN_RMII1_RXD0, NULL);
	gpio_request(GPIO_FN_RMII1_RX_ER, NULL);

	/* eMMC (PTG) */
	gpio_request(GPIO_FN_MMCCLK, NULL);
	gpio_request(GPIO_FN_MMCCMD, NULL);
	gpio_request(GPIO_FN_MMCDAT7, NULL);
	gpio_request(GPIO_FN_MMCDAT6, NULL);
	gpio_request(GPIO_FN_MMCDAT5, NULL);
	gpio_request(GPIO_FN_MMCDAT4, NULL);
	gpio_request(GPIO_FN_MMCDAT3, NULL);
	gpio_request(GPIO_FN_MMCDAT2, NULL);
	gpio_request(GPIO_FN_MMCDAT1, NULL);
	gpio_request(GPIO_FN_MMCDAT0, NULL);

	/* LPC (PTG, PTH, PTQ, PTU) */
	gpio_request(GPIO_FN_SERIRQ, NULL);
	gpio_request(GPIO_FN_LPCPD, NULL);
	gpio_request(GPIO_FN_LDRQ, NULL);
	gpio_request(GPIO_FN_WP, NULL);
	gpio_request(GPIO_FN_FMS0, NULL);
	gpio_request(GPIO_FN_LAD3, NULL);
	gpio_request(GPIO_FN_LAD2, NULL);
	gpio_request(GPIO_FN_LAD1, NULL);
	gpio_request(GPIO_FN_LAD0, NULL);
	gpio_request(GPIO_FN_LFRAME, NULL);
	gpio_request(GPIO_FN_LRESET, NULL);
	gpio_request(GPIO_FN_LCLK, NULL);
	gpio_request(GPIO_FN_LGPIO7, NULL);
	gpio_request(GPIO_FN_LGPIO6, NULL);
	gpio_request(GPIO_FN_LGPIO5, NULL);
	gpio_request(GPIO_FN_LGPIO4, NULL);

	/* SPI1 (PTH) */
	gpio_request(GPIO_FN_SP1_MOSI, NULL);
	gpio_request(GPIO_FN_SP1_MISO, NULL);
	gpio_request(GPIO_FN_SP1_SCK, NULL);
	gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
	gpio_request(GPIO_FN_SP1_SS0, NULL);
	gpio_request(GPIO_FN_SP1_SS1, NULL);

	/* SDHI (PTI) */
	gpio_request(GPIO_FN_SD_WP, NULL);
	gpio_request(GPIO_FN_SD_CD, NULL);
	gpio_request(GPIO_FN_SD_CLK, NULL);
	gpio_request(GPIO_FN_SD_CMD, NULL);
	gpio_request(GPIO_FN_SD_D3, NULL);
	gpio_request(GPIO_FN_SD_D2, NULL);
	gpio_request(GPIO_FN_SD_D1, NULL);
	gpio_request(GPIO_FN_SD_D0, NULL);

	/* SCIF3/4 (PTJ, PTW) */
	gpio_request(GPIO_FN_RTS3, NULL);
	gpio_request(GPIO_FN_CTS3, NULL);
	gpio_request(GPIO_FN_TXD3, NULL);
	gpio_request(GPIO_FN_RXD3, NULL);
	gpio_request(GPIO_FN_RTS4, NULL);
	gpio_request(GPIO_FN_RXD4, NULL);
	gpio_request(GPIO_FN_TXD4, NULL);
	gpio_request(GPIO_FN_CTS4, NULL);

	/* SERMUX (PTK, PTL, PTO, PTV) */
	gpio_request(GPIO_FN_COM2_TXD, NULL);
	gpio_request(GPIO_FN_COM2_RXD, NULL);
	gpio_request(GPIO_FN_COM2_RTS, NULL);
	gpio_request(GPIO_FN_COM2_CTS, NULL);
	gpio_request(GPIO_FN_COM2_DTR, NULL);
	gpio_request(GPIO_FN_COM2_DSR, NULL);
	gpio_request(GPIO_FN_COM2_DCD, NULL);
	gpio_request(GPIO_FN_COM2_RI, NULL);
	gpio_request(GPIO_FN_RAC_RXD, NULL);
	gpio_request(GPIO_FN_RAC_RTS, NULL);
	gpio_request(GPIO_FN_RAC_CTS, NULL);
	gpio_request(GPIO_FN_RAC_DTR, NULL);
	gpio_request(GPIO_FN_RAC_DSR, NULL);
	gpio_request(GPIO_FN_RAC_DCD, NULL);
	gpio_request(GPIO_FN_RAC_TXD, NULL);
	gpio_request(GPIO_FN_COM1_TXD, NULL);
	gpio_request(GPIO_FN_COM1_RXD, NULL);
	gpio_request(GPIO_FN_COM1_RTS, NULL);
	gpio_request(GPIO_FN_COM1_CTS, NULL);

	writeb(0x10, 0xfe470000);	/* SMR0: SerMux mode 0 */

	/* IIC (PTM, PTR, PTS) */
	gpio_request(GPIO_FN_SDA7, NULL);
	gpio_request(GPIO_FN_SCL7, NULL);
	gpio_request(GPIO_FN_SDA6, NULL);
	gpio_request(GPIO_FN_SCL6, NULL);
	gpio_request(GPIO_FN_SDA5, NULL);
	gpio_request(GPIO_FN_SCL5, NULL);
	gpio_request(GPIO_FN_SDA4, NULL);
	gpio_request(GPIO_FN_SCL4, NULL);
	gpio_request(GPIO_FN_SDA3, NULL);
	gpio_request(GPIO_FN_SCL3, NULL);
	gpio_request(GPIO_FN_SDA2, NULL);
	gpio_request(GPIO_FN_SCL2, NULL);
	gpio_request(GPIO_FN_SDA1, NULL);
	gpio_request(GPIO_FN_SCL1, NULL);
	gpio_request(GPIO_FN_SDA0, NULL);
	gpio_request(GPIO_FN_SCL0, NULL);

	/* USB (PTN) */
	gpio_request(GPIO_FN_VBUS_EN, NULL);
	gpio_request(GPIO_FN_VBUS_OC, NULL);

	/* SGPIO1/0 (PTN, PTO) */
	gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
	gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
	gpio_request(GPIO_FN_SGPIO1_DI, NULL);
	gpio_request(GPIO_FN_SGPIO1_DO, NULL);
	gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
	gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
	gpio_request(GPIO_FN_SGPIO0_DI, NULL);
	gpio_request(GPIO_FN_SGPIO0_DO, NULL);

	/* WDT (PTN) */
	gpio_request(GPIO_FN_SUB_CLKIN, NULL);

	/* System (PTT) */
	gpio_request(GPIO_FN_STATUS1, NULL);
	gpio_request(GPIO_FN_STATUS0, NULL);

	/* PWMX (PTT) */
	gpio_request(GPIO_FN_PWMX1, NULL);
	gpio_request(GPIO_FN_PWMX0, NULL);

	/* R-SPI (PTV) */
	gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
	gpio_request(GPIO_FN_R_SPI_MISO, NULL);
	gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
	gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
	gpio_request(GPIO_FN_R_SPI_SSL1, NULL);

	/* EVC (PTV, PTW) */
	gpio_request(GPIO_FN_EVENT7, NULL);
	gpio_request(GPIO_FN_EVENT6, NULL);
	gpio_request(GPIO_FN_EVENT5, NULL);
	gpio_request(GPIO_FN_EVENT4, NULL);
	gpio_request(GPIO_FN_EVENT3, NULL);
	gpio_request(GPIO_FN_EVENT2, NULL);
	gpio_request(GPIO_FN_EVENT1, NULL);
	gpio_request(GPIO_FN_EVENT0, NULL);

	/* LED for heartbeat */
	gpio_request(GPIO_PTU3, NULL);
	gpio_direction_output(GPIO_PTU3, 1);
	gpio_request(GPIO_PTU2, NULL);
	gpio_direction_output(GPIO_PTU2, 1);
	gpio_request(GPIO_PTU1, NULL);
	gpio_direction_output(GPIO_PTU1, 1);
	gpio_request(GPIO_PTU0, NULL);
	gpio_direction_output(GPIO_PTU0, 1);

	/* control for MDIO of Gigabit Ethernet */
	gpio_request(GPIO_PTT4, NULL);
	gpio_direction_output(GPIO_PTT4, 1);

	/* control for eMMC */
	gpio_request(GPIO_PTT7, NULL);		/* eMMC_RST# */
	gpio_direction_output(GPIO_PTT7, 0);
	gpio_request(GPIO_PTT6, NULL);		/* eMMC_INDEX# */
	gpio_direction_output(GPIO_PTT6, 0);
	gpio_request(GPIO_PTT5, NULL);		/* eMMC_PRST# */
	gpio_direction_output(GPIO_PTT5, 1);

	/* register SPI device information */
	spi_register_board_info(spi_board_info,
				ARRAY_SIZE(spi_board_info));

	/* General platform */
	return platform_add_devices(sh7757lcr_devices,
				    ARRAY_SIZE(sh7757lcr_devices));
}
arch_initcall(sh7757lcr_devices_setup);

/* Initialize IRQ setting */
void __init init_sh7757lcr_IRQ(void)
{
	plat_irq_setup_pins(IRQ_MODE_IRQ7654);
	plat_irq_setup_pins(IRQ_MODE_IRQ3210);
}

/* Initialize the board */
static void __init sh7757lcr_setup(char **cmdline_p)
{
	printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
}

static int sh7757lcr_mode_pins(void)
{
	int value = 0;

	/* These are the factory default settings of S3 (Low active).
	 * If you change these dip switches then you will need to
	 * adjust the values below as well.
	 */
	value |= MODE_PIN0;	/* Clock Mode: 1 */

	return value;
}

/* The Machine Vector */
static struct sh_machine_vector mv_sh7757lcr __initmv = {
	.mv_name		= "SH7757LCR",
	.mv_setup		= sh7757lcr_setup,
	.mv_init_irq		= init_sh7757lcr_IRQ,
	.mv_mode_pins		= sh7757lcr_mode_pins,
};
Commit	Line	Data
36239c67 YS	1	/*
	2	* Renesas R0P7757LC0012RL Support.
	3	*
	4	* Copyright (C) 2009 - 2010 Renesas Solutions Corp.
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/gpio.h>
	14	#include <linux/irq.h>
2db73c9b GL	15	#include <linux/regulator/fixed.h>
2db73c9b GL	16	#include <linux/regulator/machine.h>
36239c67 YS	17	#include <linux/spi/spi.h>
	18	#include <linux/spi/flash.h>
	19	#include <linux/io.h>
84f11d5b	20	#include <linux/mfd/tmio.h>
65f63eab YS	21	#include <linux/mmc/host.h>
65f63eab YS	22	#include <linux/mmc/sh_mmcif.h>
9a86cad6	23	#include <linux/mmc/sh_mobile_sdhi.h>
389cc10c	24	#include <linux/sh_eth.h>
a7734e51	25	#include <linux/sh_intc.h>
7afb4e9a	26	#include <linux/usb/renesas_usbhs.h>
36239c67	27	#include <cpu/sh7757.h>
36239c67 YS	28	#include <asm/heartbeat.h>
	29
	30	static struct resource heartbeat_resource = {
	31	.start = 0xffec005c, /* PUDR */
	32	.end = 0xffec005c,
	33	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_8BIT,
	34	};
	35
	36	static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
	37
	38	static struct heartbeat_data heartbeat_data = {
	39	.bit_pos = heartbeat_bit_pos,
	40	.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
	41	.flags = HEARTBEAT_INVERTED,
	42	};
	43
	44	static struct platform_device heartbeat_device = {
	45	.name = "heartbeat",
	46	.id = -1,
	47	.dev = {
	48	.platform_data = &heartbeat_data,
	49	},
	50	.num_resources = 1,
	51	.resource = &heartbeat_resource,
	52	};
	53
	54	/* Fast Ethernet */
984f6cfd YS	55	#define GBECONT 0xffc10100
	56	#define GBECONT_RMII1 BIT(17)
	57	#define GBECONT_RMII0 BIT(16)
19d7ca29	58	static void sh7757_eth_set_mdio_gate(void *addr)
984f6cfd	59	{
19d7ca29	60	if (((unsigned long)addr & 0x00000fff) < 0x0800)
984f6cfd YS	61	writel(readl(GBECONT) \| GBECONT_RMII0, GBECONT);
	62	else
	63	writel(readl(GBECONT) \| GBECONT_RMII1, GBECONT);
	64	}
	65
36239c67 YS	66	static struct resource sh_eth0_resources[] = {
	67	{
	68	.start = 0xfef00000,
	69	.end = 0xfef001ff,
	70	.flags = IORESOURCE_MEM,
	71	}, {
a7734e51 PM	72	.start = evt2irq(0xc80),
a7734e51 PM	73	.end = evt2irq(0xc80),
36239c67 YS	74	.flags = IORESOURCE_IRQ,
	75	},
	76	};
	77
	78	static struct sh_eth_plat_data sh7757_eth0_pdata = {
	79	.phy = 1,
	80	.edmac_endian = EDMAC_LITTLE_ENDIAN,
984f6cfd	81	.set_mdio_gate = sh7757_eth_set_mdio_gate,
36239c67 YS	82	};
	83
	84	static struct platform_device sh7757_eth0_device = {
24549e2a	85	.name = "sh7757-ether",
36239c67 YS	86	.resource = sh_eth0_resources,
	87	.id = 0,
	88	.num_resources = ARRAY_SIZE(sh_eth0_resources),
	89	.dev = {
	90	.platform_data = &sh7757_eth0_pdata,
	91	},
	92	};
	93
	94	static struct resource sh_eth1_resources[] = {
	95	{
	96	.start = 0xfef00800,
	97	.end = 0xfef009ff,
	98	.flags = IORESOURCE_MEM,
	99	}, {
a7734e51 PM	100	.start = evt2irq(0xc80),
a7734e51 PM	101	.end = evt2irq(0xc80),
36239c67 YS	102	.flags = IORESOURCE_IRQ,
	103	},
	104	};
	105
	106	static struct sh_eth_plat_data sh7757_eth1_pdata = {
	107	.phy = 1,
	108	.edmac_endian = EDMAC_LITTLE_ENDIAN,
984f6cfd	109	.set_mdio_gate = sh7757_eth_set_mdio_gate,
36239c67 YS	110	};
	111
	112	static struct platform_device sh7757_eth1_device = {
24549e2a	113	.name = "sh7757-ether",
36239c67 YS	114	.resource = sh_eth1_resources,
	115	.id = 1,
	116	.num_resources = ARRAY_SIZE(sh_eth1_resources),
	117	.dev = {
	118	.platform_data = &sh7757_eth1_pdata,
	119	},
	120	};
	121
19d7ca29	122	static void sh7757_eth_giga_set_mdio_gate(void *addr)
984f6cfd	123	{
19d7ca29	124	if (((unsigned long)addr & 0x00000fff) < 0x0800) {
984f6cfd YS	125	gpio_set_value(GPIO_PTT4, 1);
	126	writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
	127	} else {
	128	gpio_set_value(GPIO_PTT4, 0);
	129	writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
	130	}
	131	}
	132
	133	static struct resource sh_eth_giga0_resources[] = {
	134	{
	135	.start = 0xfee00000,
	136	.end = 0xfee007ff,
	137	.flags = IORESOURCE_MEM,
	138	}, {
	139	/* TSU */
	140	.start = 0xfee01800,
	141	.end = 0xfee01fff,
	142	.flags = IORESOURCE_MEM,
	143	}, {
a7734e51 PM	144	.start = evt2irq(0x2960),
a7734e51 PM	145	.end = evt2irq(0x2960),
984f6cfd YS	146	.flags = IORESOURCE_IRQ,
	147	},
	148	};
	149
	150	static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
	151	.phy = 18,
	152	.edmac_endian = EDMAC_LITTLE_ENDIAN,
984f6cfd YS	153	.set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
	154	.phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
	155	};
	156
	157	static struct platform_device sh7757_eth_giga0_device = {
24549e2a	158	.name = "sh7757-gether",
984f6cfd YS	159	.resource = sh_eth_giga0_resources,
	160	.id = 2,
	161	.num_resources = ARRAY_SIZE(sh_eth_giga0_resources),
	162	.dev = {
	163	.platform_data = &sh7757_eth_giga0_pdata,
	164	},
	165	};
	166
	167	static struct resource sh_eth_giga1_resources[] = {
	168	{
	169	.start = 0xfee00800,
	170	.end = 0xfee00fff,
	171	.flags = IORESOURCE_MEM,
befe0756 SY	172	}, {
	173	/* TSU */
	174	.start = 0xfee01800,
	175	.end = 0xfee01fff,
	176	.flags = IORESOURCE_MEM,
984f6cfd	177	}, {
a7734e51 PM	178	.start = evt2irq(0x2980),
a7734e51 PM	179	.end = evt2irq(0x2980),
984f6cfd YS	180	.flags = IORESOURCE_IRQ,
	181	},
	182	};
	183
	184	static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
	185	.phy = 19,
	186	.edmac_endian = EDMAC_LITTLE_ENDIAN,
984f6cfd YS	187	.set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
	188	.phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
	189	};
	190
	191	static struct platform_device sh7757_eth_giga1_device = {
24549e2a	192	.name = "sh7757-gether",
984f6cfd YS	193	.resource = sh_eth_giga1_resources,
	194	.id = 3,
	195	.num_resources = ARRAY_SIZE(sh_eth_giga1_resources),
	196	.dev = {
	197	.platform_data = &sh7757_eth_giga1_pdata,
	198	},
	199	};
	200
2db73c9b GL	201	/* Fixed 3.3V regulator to be used by SDHI0, MMCIF */
	202	static struct regulator_consumer_supply fixed3v3_power_consumers[] =
	203	{
	204	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
	205	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
	206	REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
	207	REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
	208	};
	209
65f63eab YS	210	/* SH_MMCIF */
	211	static struct resource sh_mmcif_resources[] = {
	212	[0] = {
	213	.start = 0xffcb0000,
	214	.end = 0xffcb00ff,
	215	.flags = IORESOURCE_MEM,
	216	},
	217	[1] = {
a7734e51	218	.start = evt2irq(0x1c60),
65f63eab YS	219	.flags = IORESOURCE_IRQ,
	220	},
	221	[2] = {
a7734e51	222	.start = evt2irq(0x1c80),
65f63eab YS	223	.flags = IORESOURCE_IRQ,
	224	},
	225	};
	226
65f63eab	227	static struct sh_mmcif_plat_data sh_mmcif_plat = {
65f63eab	228	.sup_pclk = 0x0f,
78da107a SY	229	.caps = MMC_CAP_4_BIT_DATA \| MMC_CAP_8_BIT_DATA \|
78da107a SY	230	MMC_CAP_NONREMOVABLE,
65f63eab	231	.ocr = MMC_VDD_32_33 \| MMC_VDD_33_34,
482835ce GL	232	.slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
482835ce GL	233	.slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
65f63eab YS	234	};
	235
	236	static struct platform_device sh_mmcif_device = {
	237	.name = "sh_mmcif",
	238	.id = 0,
	239	.dev = {
	240	.platform_data = &sh_mmcif_plat,
	241	},
	242	.num_resources = ARRAY_SIZE(sh_mmcif_resources),
	243	.resource = sh_mmcif_resources,
	244	};
	245
	246	/* SDHI0 */
84f11d5b KM	247	static struct tmio_mmc_data sdhi_info = {
	248	.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI_TX,
	249	.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI_RX,
	250	.capabilities = MMC_CAP_SD_HIGHSPEED,
65f63eab YS	251	};
	252
	253	static struct resource sdhi_resources[] = {
	254	[0] = {
	255	.start = 0xffe50000,
f0767e89	256	.end = 0xffe500ff,
65f63eab YS	257	.flags = IORESOURCE_MEM,
	258	},
	259	[1] = {
a7734e51	260	.start = evt2irq(0x480),
65f63eab YS	261	.flags = IORESOURCE_IRQ,
	262	},
	263	};
	264
	265	static struct platform_device sdhi_device = {
	266	.name = "sh_mobile_sdhi",
	267	.num_resources = ARRAY_SIZE(sdhi_resources),
	268	.resource = sdhi_resources,
	269	.id = 0,
	270	.dev = {
	271	.platform_data = &sdhi_info,
	272	},
	273	};
	274
7afb4e9a SY	275	static int usbhs0_get_id(struct platform_device *pdev)
	276	{
	277	return USBHS_GADGET;
	278	}
	279
	280	static struct renesas_usbhs_platform_info usb0_data = {
	281	.platform_callback = {
	282	.get_id = usbhs0_get_id,
	283	},
	284	.driver_param = {
	285	.buswait_bwait = 5,
	286	}
	287	};
	288
	289	static struct resource usb0_resources[] = {
	290	[0] = {
	291	.start = 0xfe450000,
	292	.end = 0xfe4501ff,
	293	.flags = IORESOURCE_MEM,
	294	},
	295	[1] = {
a7734e51 PM	296	.start = evt2irq(0x840),
a7734e51 PM	297	.end = evt2irq(0x840),
7afb4e9a SY	298	.flags = IORESOURCE_IRQ,
	299	},
	300	};
	301
	302	static struct platform_device usb0_device = {
	303	.name = "renesas_usbhs",
	304	.id = 0,
	305	.dev = {
	306	.platform_data = &usb0_data,
	307	},
	308	.num_resources = ARRAY_SIZE(usb0_resources),
	309	.resource = usb0_resources,
	310	};
	311
36239c67 YS	312	static struct platform_device *sh7757lcr_devices[] __initdata = {
	313	&heartbeat_device,
	314	&sh7757_eth0_device,
	315	&sh7757_eth1_device,
984f6cfd YS	316	&sh7757_eth_giga0_device,
984f6cfd YS	317	&sh7757_eth_giga1_device,
65f63eab YS	318	&sh_mmcif_device,
65f63eab YS	319	&sdhi_device,
7afb4e9a	320	&usb0_device,
36239c67 YS	321	};
36239c67 YS	322
ceb7afe2 YS	323	static struct flash_platform_data spi_flash_data = {
	324	.name = "m25p80",
	325	.type = "m25px64",
	326	};
	327
	328	static struct spi_board_info spi_board_info[] = {
	329	{
	330	.modalias = "m25p80",
	331	.max_speed_hz = 25000000,
	332	.bus_num = 0,
	333	.chip_select = 1,
	334	.platform_data = &spi_flash_data,
	335	},
	336	};
	337
36239c67 YS	338	static int __init sh7757lcr_devices_setup(void)
36239c67 YS	339	{
2db73c9b GL	340	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
	341	ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
	342
36239c67 YS	343	/* RGMII (PTA) */
	344	gpio_request(GPIO_FN_ET0_MDC, NULL);
	345	gpio_request(GPIO_FN_ET0_MDIO, NULL);
	346	gpio_request(GPIO_FN_ET1_MDC, NULL);
	347	gpio_request(GPIO_FN_ET1_MDIO, NULL);
	348
	349	/* ONFI (PTB, PTZ) */
	350	gpio_request(GPIO_FN_ON_NRE, NULL);
	351	gpio_request(GPIO_FN_ON_NWE, NULL);
	352	gpio_request(GPIO_FN_ON_NWP, NULL);
	353	gpio_request(GPIO_FN_ON_NCE0, NULL);
	354	gpio_request(GPIO_FN_ON_R_B0, NULL);
	355	gpio_request(GPIO_FN_ON_ALE, NULL);
	356	gpio_request(GPIO_FN_ON_CLE, NULL);
	357
	358	gpio_request(GPIO_FN_ON_DQ7, NULL);
	359	gpio_request(GPIO_FN_ON_DQ6, NULL);
	360	gpio_request(GPIO_FN_ON_DQ5, NULL);
	361	gpio_request(GPIO_FN_ON_DQ4, NULL);
	362	gpio_request(GPIO_FN_ON_DQ3, NULL);
	363	gpio_request(GPIO_FN_ON_DQ2, NULL);
	364	gpio_request(GPIO_FN_ON_DQ1, NULL);
	365	gpio_request(GPIO_FN_ON_DQ0, NULL);
	366
	367	/* IRQ8 to 0 (PTB, PTC) */
	368	gpio_request(GPIO_FN_IRQ8, NULL);
	369	gpio_request(GPIO_FN_IRQ7, NULL);
	370	gpio_request(GPIO_FN_IRQ6, NULL);
	371	gpio_request(GPIO_FN_IRQ5, NULL);
	372	gpio_request(GPIO_FN_IRQ4, NULL);
	373	gpio_request(GPIO_FN_IRQ3, NULL);
	374	gpio_request(GPIO_FN_IRQ2, NULL);
	375	gpio_request(GPIO_FN_IRQ1, NULL);
	376	gpio_request(GPIO_FN_IRQ0, NULL);
	377
	378	/* SPI0 (PTD) */
	379	gpio_request(GPIO_FN_SP0_MOSI, NULL);
	380	gpio_request(GPIO_FN_SP0_MISO, NULL);
	381	gpio_request(GPIO_FN_SP0_SCK, NULL);
	382	gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
	383	gpio_request(GPIO_FN_SP0_SS0, NULL);
	384	gpio_request(GPIO_FN_SP0_SS1, NULL);
	385	gpio_request(GPIO_FN_SP0_SS2, NULL);
	386	gpio_request(GPIO_FN_SP0_SS3, NULL);
	387
	388	/* RMII 0/1 (PTE, PTF) */
	389	gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
	390	gpio_request(GPIO_FN_RMII0_TXD1, NULL);
	391	gpio_request(GPIO_FN_RMII0_TXD0, NULL);
	392	gpio_request(GPIO_FN_RMII0_TXEN, NULL);
	393	gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
	394	gpio_request(GPIO_FN_RMII0_RXD1, NULL);
	395	gpio_request(GPIO_FN_RMII0_RXD0, NULL);
	396	gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
	397	gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
	398	gpio_request(GPIO_FN_RMII1_TXD1, NULL);
	399	gpio_request(GPIO_FN_RMII1_TXD0, NULL);
	400	gpio_request(GPIO_FN_RMII1_TXEN, NULL);
	401	gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
	402	gpio_request(GPIO_FN_RMII1_RXD1, NULL);
	403	gpio_request(GPIO_FN_RMII1_RXD0, NULL);
	404	gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
	405
	406	/* eMMC (PTG) */
407	gpio_request(GPIO_FN_MMCCLK, NULL);
408	gpio_request(GPIO_FN_MMCCMD, NULL);
409	gpio_request(GPIO_FN_MMCDAT7, NULL);
410	gpio_request(GPIO_FN_MMCDAT6, NULL);
411	gpio_request(GPIO_FN_MMCDAT5, NULL);
412	gpio_request(GPIO_FN_MMCDAT4, NULL);
413	gpio_request(GPIO_FN_MMCDAT3, NULL);
414	gpio_request(GPIO_FN_MMCDAT2, NULL);
415	gpio_request(GPIO_FN_MMCDAT1, NULL);
416	gpio_request(GPIO_FN_MMCDAT0, NULL);
417
418	/* LPC (PTG, PTH, PTQ, PTU) */
419	gpio_request(GPIO_FN_SERIRQ, NULL);
420	gpio_request(GPIO_FN_LPCPD, NULL);
421	gpio_request(GPIO_FN_LDRQ, NULL);
422	gpio_request(GPIO_FN_WP, NULL);
423	gpio_request(GPIO_FN_FMS0, NULL);
424	gpio_request(GPIO_FN_LAD3, NULL);
425	gpio_request(GPIO_FN_LAD2, NULL);
426	gpio_request(GPIO_FN_LAD1, NULL);
427	gpio_request(GPIO_FN_LAD0, NULL);
428	gpio_request(GPIO_FN_LFRAME, NULL);
429	gpio_request(GPIO_FN_LRESET, NULL);
430	gpio_request(GPIO_FN_LCLK, NULL);
431	gpio_request(GPIO_FN_LGPIO7, NULL);
432	gpio_request(GPIO_FN_LGPIO6, NULL);
433	gpio_request(GPIO_FN_LGPIO5, NULL);
434	gpio_request(GPIO_FN_LGPIO4, NULL);
435
436	/* SPI1 (PTH) */
437	gpio_request(GPIO_FN_SP1_MOSI, NULL);
438	gpio_request(GPIO_FN_SP1_MISO, NULL);
439	gpio_request(GPIO_FN_SP1_SCK, NULL);
440	gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
441	gpio_request(GPIO_FN_SP1_SS0, NULL);
442	gpio_request(GPIO_FN_SP1_SS1, NULL);
443
444	/* SDHI (PTI) */
445	gpio_request(GPIO_FN_SD_WP, NULL);
446	gpio_request(GPIO_FN_SD_CD, NULL);
447	gpio_request(GPIO_FN_SD_CLK, NULL);
448	gpio_request(GPIO_FN_SD_CMD, NULL);
449	gpio_request(GPIO_FN_SD_D3, NULL);
450	gpio_request(GPIO_FN_SD_D2, NULL);
451	gpio_request(GPIO_FN_SD_D1, NULL);
452	gpio_request(GPIO_FN_SD_D0, NULL);
453
454	/* SCIF3/4 (PTJ, PTW) */
455	gpio_request(GPIO_FN_RTS3, NULL);
456	gpio_request(GPIO_FN_CTS3, NULL);
457	gpio_request(GPIO_FN_TXD3, NULL);
458	gpio_request(GPIO_FN_RXD3, NULL);
459	gpio_request(GPIO_FN_RTS4, NULL);
460	gpio_request(GPIO_FN_RXD4, NULL);
461	gpio_request(GPIO_FN_TXD4, NULL);
462	gpio_request(GPIO_FN_CTS4, NULL);
463
464	/* SERMUX (PTK, PTL, PTO, PTV) */
465	gpio_request(GPIO_FN_COM2_TXD, NULL);
466	gpio_request(GPIO_FN_COM2_RXD, NULL);
467	gpio_request(GPIO_FN_COM2_RTS, NULL);
468	gpio_request(GPIO_FN_COM2_CTS, NULL);
469	gpio_request(GPIO_FN_COM2_DTR, NULL);
470	gpio_request(GPIO_FN_COM2_DSR, NULL);
471	gpio_request(GPIO_FN_COM2_DCD, NULL);
472	gpio_request(GPIO_FN_COM2_RI, NULL);
473	gpio_request(GPIO_FN_RAC_RXD, NULL);
474	gpio_request(GPIO_FN_RAC_RTS, NULL);
475	gpio_request(GPIO_FN_RAC_CTS, NULL);
476	gpio_request(GPIO_FN_RAC_DTR, NULL);
477	gpio_request(GPIO_FN_RAC_DSR, NULL);
478	gpio_request(GPIO_FN_RAC_DCD, NULL);
479	gpio_request(GPIO_FN_RAC_TXD, NULL);
480	gpio_request(GPIO_FN_COM1_TXD, NULL);
481	gpio_request(GPIO_FN_COM1_RXD, NULL);
482	gpio_request(GPIO_FN_COM1_RTS, NULL);
483	gpio_request(GPIO_FN_COM1_CTS, NULL);
484
485	writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */
486
487	/* IIC (PTM, PTR, PTS) */
488	gpio_request(GPIO_FN_SDA7, NULL);
489	gpio_request(GPIO_FN_SCL7, NULL);
490	gpio_request(GPIO_FN_SDA6, NULL);
491	gpio_request(GPIO_FN_SCL6, NULL);
492	gpio_request(GPIO_FN_SDA5, NULL);
493	gpio_request(GPIO_FN_SCL5, NULL);
494	gpio_request(GPIO_FN_SDA4, NULL);
495	gpio_request(GPIO_FN_SCL4, NULL);
496	gpio_request(GPIO_FN_SDA3, NULL);
497	gpio_request(GPIO_FN_SCL3, NULL);
498	gpio_request(GPIO_FN_SDA2, NULL);
499	gpio_request(GPIO_FN_SCL2, NULL);
500	gpio_request(GPIO_FN_SDA1, NULL);
501	gpio_request(GPIO_FN_SCL1, NULL);
502	gpio_request(GPIO_FN_SDA0, NULL);
503	gpio_request(GPIO_FN_SCL0, NULL);
504
505	/* USB (PTN) */
506	gpio_request(GPIO_FN_VBUS_EN, NULL);
507	gpio_request(GPIO_FN_VBUS_OC, NULL);
508
509	/* SGPIO1/0 (PTN, PTO) */
510	gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
511	gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
512	gpio_request(GPIO_FN_SGPIO1_DI, NULL);
513	gpio_request(GPIO_FN_SGPIO1_DO, NULL);
514	gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
515	gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
516	gpio_request(GPIO_FN_SGPIO0_DI, NULL);
517	gpio_request(GPIO_FN_SGPIO0_DO, NULL);
518
519	/* WDT (PTN) */
520	gpio_request(GPIO_FN_SUB_CLKIN, NULL);
521
522	/* System (PTT) */
523	gpio_request(GPIO_FN_STATUS1, NULL);
524	gpio_request(GPIO_FN_STATUS0, NULL);
525
526	/* PWMX (PTT) */
527	gpio_request(GPIO_FN_PWMX1, NULL);
528	gpio_request(GPIO_FN_PWMX0, NULL);
529
530	/* R-SPI (PTV) */
531	gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
532	gpio_request(GPIO_FN_R_SPI_MISO, NULL);
533	gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
534	gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
535	gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
536
537	/* EVC (PTV, PTW) */
538	gpio_request(GPIO_FN_EVENT7, NULL);
539	gpio_request(GPIO_FN_EVENT6, NULL);
540	gpio_request(GPIO_FN_EVENT5, NULL);
541	gpio_request(GPIO_FN_EVENT4, NULL);
542	gpio_request(GPIO_FN_EVENT3, NULL);
543	gpio_request(GPIO_FN_EVENT2, NULL);
544	gpio_request(GPIO_FN_EVENT1, NULL);
545	gpio_request(GPIO_FN_EVENT0, NULL);
546
547	/* LED for heartbeat */
548	gpio_request(GPIO_PTU3, NULL);
549	gpio_direction_output(GPIO_PTU3, 1);
550	gpio_request(GPIO_PTU2, NULL);
551	gpio_direction_output(GPIO_PTU2, 1);
552	gpio_request(GPIO_PTU1, NULL);
553	gpio_direction_output(GPIO_PTU1, 1);
554	gpio_request(GPIO_PTU0, NULL);
555	gpio_direction_output(GPIO_PTU0, 1);
556
557	/* control for MDIO of Gigabit Ethernet */
558	gpio_request(GPIO_PTT4, NULL);
559	gpio_direction_output(GPIO_PTT4, 1);
560
561	/* control for eMMC */
562	gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */
563	gpio_direction_output(GPIO_PTT7, 0);
564	gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */
565	gpio_direction_output(GPIO_PTT6, 0);
566	gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */
567	gpio_direction_output(GPIO_PTT5, 1);
568
ceb7afe2 YS	569	/* register SPI device information */
	570	spi_register_board_info(spi_board_info,
	571	ARRAY_SIZE(spi_board_info));
	572
36239c67 YS	573	/* General platform */
	574	return platform_add_devices(sh7757lcr_devices,
	575	ARRAY_SIZE(sh7757lcr_devices));
	576	}
	577	arch_initcall(sh7757lcr_devices_setup);
	578
	579	/* Initialize IRQ setting */
	580	void __init init_sh7757lcr_IRQ(void)
	581	{
	582	plat_irq_setup_pins(IRQ_MODE_IRQ7654);
	583	plat_irq_setup_pins(IRQ_MODE_IRQ3210);
	584	}
	585
	586	/* Initialize the board */
	587	static void __init sh7757lcr_setup(char **cmdline_p)
	588	{
	589	printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
	590	}
	591
	592	static int sh7757lcr_mode_pins(void)
	593	{
	594	int value = 0;
	595
	596	/* These are the factory default settings of S3 (Low active).
	597	* If you change these dip switches then you will need to
	598	* adjust the values below as well.
	599	*/
	600	value \|= MODE_PIN0; /* Clock Mode: 1 */
	601
	602	return value;
	603	}
	604
	605	/* The Machine Vector */
	606	static struct sh_machine_vector mv_sh7757lcr __initmv = {
	607	.mv_name = "SH7757LCR",
	608	.mv_setup = sh7757lcr_setup,
	609	.mv_init_irq = init_sh7757lcr_IRQ,
	610	.mv_mode_pins = sh7757lcr_mode_pins,
	611	};
	612