Commit | Line | Data |
---|---|---|
04e917b6 YG |
1 | /* |
2 | * Renesas - AP-325RXA | |
3 | * (Compatible with Algo System ., LTD. - AP-320A) | |
4 | * | |
5 | * Copyright (C) 2008 Renesas Solutions Corp. | |
6 | * Author : Yusuke Goda <goda.yuske@renesas.com> | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/device.h> | |
4875ea22 | 15 | #include <linux/interrupt.h> |
04e917b6 YG |
16 | #include <linux/platform_device.h> |
17 | #include <linux/mtd/physmap.h> | |
908978ac | 18 | #include <linux/mtd/sh_flctl.h> |
04e917b6 | 19 | #include <linux/delay.h> |
026953db | 20 | #include <linux/i2c.h> |
90b76491 | 21 | #include <linux/smsc911x.h> |
16587c45 | 22 | #include <linux/gpio.h> |
47131258 | 23 | #include <media/ov772x.h> |
ba087e6f | 24 | #include <media/soc_camera.h> |
8b2224dc MD |
25 | #include <media/soc_camera_platform.h> |
26 | #include <media/sh_mobile_ceu.h> | |
225c9a8d | 27 | #include <video/sh_mobile_lcdc.h> |
04e917b6 | 28 | #include <asm/io.h> |
6968980a | 29 | #include <asm/clock.h> |
86c7d03a | 30 | #include <asm/suspend.h> |
f7275650 | 31 | #include <cpu/sh7723.h> |
04e917b6 | 32 | |
90b76491 SG |
33 | static struct smsc911x_platform_config smsc911x_config = { |
34 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
35 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | |
36 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | |
37 | .flags = SMSC911X_USE_32BIT, | |
4875ea22 MD |
38 | }; |
39 | ||
90b76491 | 40 | static struct resource smsc9118_resources[] = { |
04e917b6 YG |
41 | [0] = { |
42 | .start = 0xb6080000, | |
43 | .end = 0xb60fffff, | |
44 | .flags = IORESOURCE_MEM, | |
45 | }, | |
46 | [1] = { | |
47 | .start = 35, | |
48 | .end = 35, | |
49 | .flags = IORESOURCE_IRQ, | |
50 | } | |
51 | }; | |
52 | ||
90b76491 SG |
53 | static struct platform_device smsc9118_device = { |
54 | .name = "smsc911x", | |
04e917b6 | 55 | .id = -1, |
90b76491 SG |
56 | .num_resources = ARRAY_SIZE(smsc9118_resources), |
57 | .resource = smsc9118_resources, | |
4875ea22 | 58 | .dev = { |
90b76491 | 59 | .platform_data = &smsc911x_config, |
4875ea22 | 60 | }, |
04e917b6 YG |
61 | }; |
62 | ||
aa88f169 NI |
63 | /* |
64 | * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF). | |
65 | * If this area erased, this board can not boot. | |
66 | */ | |
04e917b6 YG |
67 | static struct mtd_partition ap325rxa_nor_flash_partitions[] = { |
68 | { | |
aa88f169 NI |
69 | .name = "uboot", |
70 | .offset = 0, | |
71 | .size = (1 * 1024 * 1024), | |
72 | .mask_flags = MTD_WRITEABLE, /* Read-only */ | |
73 | }, { | |
74 | .name = "kernel", | |
75 | .offset = MTDPART_OFS_APPEND, | |
76 | .size = (2 * 1024 * 1024), | |
77 | }, { | |
78 | .name = "free-area0", | |
79 | .offset = MTDPART_OFS_APPEND, | |
80 | .size = ((7 * 1024 * 1024) + (512 * 1024)), | |
04e917b6 | 81 | }, { |
aa88f169 NI |
82 | .name = "CPLD-Data", |
83 | .offset = MTDPART_OFS_APPEND, | |
84 | .mask_flags = MTD_WRITEABLE, /* Read-only */ | |
85 | .size = (1024 * 128 * 2), | |
04e917b6 | 86 | }, { |
aa88f169 NI |
87 | .name = "free-area1", |
88 | .offset = MTDPART_OFS_APPEND, | |
89 | .size = MTDPART_SIZ_FULL, | |
04e917b6 YG |
90 | }, |
91 | }; | |
92 | ||
93 | static struct physmap_flash_data ap325rxa_nor_flash_data = { | |
94 | .width = 2, | |
95 | .parts = ap325rxa_nor_flash_partitions, | |
96 | .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), | |
97 | }; | |
98 | ||
99 | static struct resource ap325rxa_nor_flash_resources[] = { | |
100 | [0] = { | |
101 | .name = "NOR Flash", | |
102 | .start = 0x00000000, | |
103 | .end = 0x00ffffff, | |
104 | .flags = IORESOURCE_MEM, | |
105 | } | |
106 | }; | |
107 | ||
108 | static struct platform_device ap325rxa_nor_flash_device = { | |
109 | .name = "physmap-flash", | |
110 | .resource = ap325rxa_nor_flash_resources, | |
111 | .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), | |
112 | .dev = { | |
113 | .platform_data = &ap325rxa_nor_flash_data, | |
114 | }, | |
115 | }; | |
116 | ||
908978ac YS |
117 | static struct mtd_partition nand_partition_info[] = { |
118 | { | |
119 | .name = "nand_data", | |
120 | .offset = 0, | |
121 | .size = MTDPART_SIZ_FULL, | |
122 | }, | |
123 | }; | |
124 | ||
125 | static struct resource nand_flash_resources[] = { | |
126 | [0] = { | |
127 | .start = 0xa4530000, | |
128 | .end = 0xa45300ff, | |
129 | .flags = IORESOURCE_MEM, | |
130 | } | |
131 | }; | |
132 | ||
133 | static struct sh_flctl_platform_data nand_flash_data = { | |
134 | .parts = nand_partition_info, | |
135 | .nr_parts = ARRAY_SIZE(nand_partition_info), | |
136 | .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E, | |
137 | .has_hwecc = 1, | |
138 | }; | |
139 | ||
140 | static struct platform_device nand_flash_device = { | |
141 | .name = "sh_flctl", | |
142 | .resource = nand_flash_resources, | |
143 | .num_resources = ARRAY_SIZE(nand_flash_resources), | |
144 | .dev = { | |
145 | .platform_data = &nand_flash_data, | |
146 | }, | |
147 | }; | |
148 | ||
6968980a MD |
149 | #define FPGA_LCDREG 0xB4100180 |
150 | #define FPGA_BKLREG 0xB4100212 | |
151 | #define FPGA_LCDREG_VAL 0x0018 | |
8b2224dc | 152 | #define PORT_MSELCRB 0xA4050182 |
908978ac YS |
153 | #define PORT_HIZCRC 0xA405015C |
154 | #define PORT_DRVCRA 0xA405018A | |
155 | #define PORT_DRVCRB 0xA405018C | |
6968980a MD |
156 | |
157 | static void ap320_wvga_power_on(void *board_data) | |
158 | { | |
159 | msleep(100); | |
160 | ||
161 | /* ASD AP-320/325 LCD ON */ | |
162 | ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); | |
163 | ||
164 | /* backlight */ | |
16587c45 | 165 | gpio_set_value(GPIO_PTS3, 0); |
6968980a MD |
166 | ctrl_outw(0x100, FPGA_BKLREG); |
167 | } | |
168 | ||
93356d07 MD |
169 | static void ap320_wvga_power_off(void *board_data) |
170 | { | |
171 | /* backlight */ | |
172 | ctrl_outw(0, FPGA_BKLREG); | |
173 | gpio_set_value(GPIO_PTS3, 1); | |
174 | ||
175 | /* ASD AP-320/325 LCD OFF */ | |
176 | ctrl_outw(0, FPGA_LCDREG); | |
177 | } | |
178 | ||
6968980a MD |
179 | static struct sh_mobile_lcdc_info lcdc_info = { |
180 | .clock_source = LCDC_CLK_EXTERNAL, | |
181 | .ch[0] = { | |
182 | .chan = LCDC_CHAN_MAINLCD, | |
183 | .bpp = 16, | |
184 | .interface_type = RGB18, | |
185 | .clock_divider = 1, | |
186 | .lcd_cfg = { | |
187 | .name = "LB070WV1", | |
188 | .xres = 800, | |
189 | .yres = 480, | |
6a78ec16 | 190 | .left_margin = 32, |
6968980a MD |
191 | .right_margin = 160, |
192 | .hsync_len = 8, | |
193 | .upper_margin = 63, | |
194 | .lower_margin = 80, | |
195 | .vsync_len = 1, | |
196 | .sync = 0, /* hsync and vsync are active low */ | |
197 | }, | |
ce9c008c MD |
198 | .lcd_size_cfg = { /* 7.0 inch */ |
199 | .width = 152, | |
200 | .height = 91, | |
201 | }, | |
6968980a MD |
202 | .board_cfg = { |
203 | .display_on = ap320_wvga_power_on, | |
93356d07 | 204 | .display_off = ap320_wvga_power_off, |
6968980a MD |
205 | }, |
206 | } | |
207 | }; | |
208 | ||
209 | static struct resource lcdc_resources[] = { | |
210 | [0] = { | |
211 | .name = "LCDC", | |
212 | .start = 0xfe940000, /* P4-only space */ | |
a6f15ade | 213 | .end = 0xfe942fff, |
6968980a MD |
214 | .flags = IORESOURCE_MEM, |
215 | }, | |
07905554 MD |
216 | [1] = { |
217 | .start = 28, | |
218 | .flags = IORESOURCE_IRQ, | |
219 | }, | |
6968980a MD |
220 | }; |
221 | ||
222 | static struct platform_device lcdc_device = { | |
223 | .name = "sh_mobile_lcdc_fb", | |
224 | .num_resources = ARRAY_SIZE(lcdc_resources), | |
225 | .resource = lcdc_resources, | |
226 | .dev = { | |
227 | .platform_data = &lcdc_info, | |
228 | }, | |
d3a6f626 MD |
229 | .archdata = { |
230 | .hwblk_id = HWBLK_LCDC, | |
231 | }, | |
6968980a MD |
232 | }; |
233 | ||
86746284 KM |
234 | static void camera_power(int val) |
235 | { | |
236 | gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */ | |
237 | mdelay(10); | |
238 | } | |
239 | ||
e565b518 | 240 | #ifdef CONFIG_I2C |
47131258 | 241 | /* support for the old ncm03j camera */ |
8b2224dc MD |
242 | static unsigned char camera_ncm03j_magic[] = |
243 | { | |
244 | 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, | |
245 | 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, | |
246 | 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, | |
247 | 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, | |
248 | 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, | |
249 | 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, | |
250 | 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, | |
251 | 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, | |
252 | 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, | |
253 | 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, | |
254 | 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, | |
255 | 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, | |
256 | 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, | |
257 | 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, | |
258 | 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, | |
259 | 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, | |
260 | }; | |
261 | ||
47131258 KM |
262 | static int camera_probe(void) |
263 | { | |
264 | struct i2c_adapter *a = i2c_get_adapter(0); | |
265 | struct i2c_msg msg; | |
266 | int ret; | |
267 | ||
37869fa2 MD |
268 | if (!a) |
269 | return -ENODEV; | |
270 | ||
47131258 KM |
271 | camera_power(1); |
272 | msg.addr = 0x6e; | |
273 | msg.buf = camera_ncm03j_magic; | |
274 | msg.len = 2; | |
275 | msg.flags = 0; | |
276 | ret = i2c_transfer(a, &msg, 1); | |
277 | camera_power(0); | |
278 | ||
279 | return ret; | |
280 | } | |
281 | ||
8b2224dc MD |
282 | static int camera_set_capture(struct soc_camera_platform_info *info, |
283 | int enable) | |
284 | { | |
285 | struct i2c_adapter *a = i2c_get_adapter(0); | |
286 | struct i2c_msg msg; | |
287 | int ret = 0; | |
288 | int i; | |
289 | ||
86746284 | 290 | camera_power(0); |
8b2224dc MD |
291 | if (!enable) |
292 | return 0; /* no disable for now */ | |
293 | ||
86746284 | 294 | camera_power(1); |
8b2224dc MD |
295 | for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { |
296 | u_int8_t buf[8]; | |
297 | ||
298 | msg.addr = 0x6e; | |
299 | msg.buf = buf; | |
300 | msg.len = 2; | |
301 | msg.flags = 0; | |
302 | ||
303 | buf[0] = camera_ncm03j_magic[i]; | |
304 | buf[1] = camera_ncm03j_magic[i + 1]; | |
305 | ||
306 | ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); | |
307 | } | |
308 | ||
309 | return ret; | |
310 | } | |
311 | ||
c41debaf GL |
312 | static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev); |
313 | static void ap325rxa_camera_del(struct soc_camera_link *icl); | |
314 | ||
8b2224dc | 315 | static struct soc_camera_platform_info camera_info = { |
8b2224dc MD |
316 | .format_name = "UYVY", |
317 | .format_depth = 16, | |
318 | .format = { | |
760697be | 319 | .code = V4L2_MBUS_FMT_YUYV8_2X8_BE, |
8b2224dc | 320 | .colorspace = V4L2_COLORSPACE_SMPTE170M, |
760697be | 321 | .field = V4L2_FIELD_NONE, |
8b2224dc MD |
322 | .width = 640, |
323 | .height = 480, | |
324 | }, | |
325 | .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | | |
326 | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, | |
327 | .set_capture = camera_set_capture, | |
0f448294 GL |
328 | }; |
329 | ||
330 | struct soc_camera_link camera_link = { | |
331 | .bus_id = 0, | |
332 | .add_device = ap325rxa_camera_add, | |
333 | .del_device = ap325rxa_camera_del, | |
334 | .module_name = "soc_camera_platform", | |
335 | .priv = &camera_info, | |
8b2224dc MD |
336 | }; |
337 | ||
0bab829d GL |
338 | static void dummy_release(struct device *dev) |
339 | { | |
340 | } | |
341 | ||
8b2224dc MD |
342 | static struct platform_device camera_device = { |
343 | .name = "soc_camera_platform", | |
344 | .dev = { | |
345 | .platform_data = &camera_info, | |
0bab829d | 346 | .release = dummy_release, |
8b2224dc MD |
347 | }, |
348 | }; | |
47131258 | 349 | |
c41debaf GL |
350 | static int ap325rxa_camera_add(struct soc_camera_link *icl, |
351 | struct device *dev) | |
47131258 | 352 | { |
0f448294 | 353 | if (icl != &camera_link || camera_probe() <= 0) |
c41debaf | 354 | return -ENODEV; |
47131258 | 355 | |
bc1937b4 GL |
356 | camera_info.dev = dev; |
357 | ||
c41debaf | 358 | return platform_device_register(&camera_device); |
47131258 | 359 | } |
47131258 | 360 | |
c41debaf GL |
361 | static void ap325rxa_camera_del(struct soc_camera_link *icl) |
362 | { | |
0f448294 | 363 | if (icl != &camera_link) |
0bab829d GL |
364 | return; |
365 | ||
366 | platform_device_unregister(&camera_device); | |
367 | memset(&camera_device.dev.kobj, 0, | |
368 | sizeof(camera_device.dev.kobj)); | |
c41debaf | 369 | } |
e565b518 | 370 | #endif /* CONFIG_I2C */ |
8b2224dc | 371 | |
47131258 KM |
372 | static int ov7725_power(struct device *dev, int mode) |
373 | { | |
374 | camera_power(0); | |
375 | if (mode) | |
376 | camera_power(1); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
8b2224dc | 381 | static struct sh_mobile_ceu_info sh_mobile_ceu_info = { |
46368fa0 | 382 | .flags = SH_CEU_FLAG_USE_8BIT_BUS, |
8b2224dc MD |
383 | }; |
384 | ||
385 | static struct resource ceu_resources[] = { | |
386 | [0] = { | |
387 | .name = "CEU", | |
388 | .start = 0xfe910000, | |
389 | .end = 0xfe91009f, | |
390 | .flags = IORESOURCE_MEM, | |
391 | }, | |
392 | [1] = { | |
393 | .start = 52, | |
394 | .flags = IORESOURCE_IRQ, | |
395 | }, | |
396 | [2] = { | |
397 | /* place holder for contiguous memory */ | |
398 | }, | |
399 | }; | |
400 | ||
401 | static struct platform_device ceu_device = { | |
402 | .name = "sh_mobile_ceu", | |
a42b6dd6 | 403 | .id = 0, /* "ceu0" clock */ |
8b2224dc MD |
404 | .num_resources = ARRAY_SIZE(ceu_resources), |
405 | .resource = ceu_resources, | |
406 | .dev = { | |
407 | .platform_data = &sh_mobile_ceu_info, | |
408 | }, | |
d3a6f626 MD |
409 | .archdata = { |
410 | .hwblk_id = HWBLK_CEU, | |
411 | }, | |
8b2224dc MD |
412 | }; |
413 | ||
17f81473 MD |
414 | static struct resource sdhi0_cn3_resources[] = { |
415 | [0] = { | |
416 | .name = "SDHI0", | |
417 | .start = 0x04ce0000, | |
418 | .end = 0x04ce01ff, | |
419 | .flags = IORESOURCE_MEM, | |
420 | }, | |
421 | [1] = { | |
422 | .start = 101, | |
423 | .flags = IORESOURCE_IRQ, | |
424 | }, | |
fbdd9a70 MD |
425 | }; |
426 | ||
17f81473 MD |
427 | static struct platform_device sdhi0_cn3_device = { |
428 | .name = "sh_mobile_sdhi", | |
8b431a7e | 429 | .id = 0, /* "sdhi0" clock */ |
17f81473 MD |
430 | .num_resources = ARRAY_SIZE(sdhi0_cn3_resources), |
431 | .resource = sdhi0_cn3_resources, | |
432 | .archdata = { | |
433 | .hwblk_id = HWBLK_SDHI0, | |
fbdd9a70 MD |
434 | }, |
435 | }; | |
436 | ||
8b431a7e MD |
437 | static struct resource sdhi1_cn7_resources[] = { |
438 | [0] = { | |
439 | .name = "SDHI1", | |
440 | .start = 0x04cf0000, | |
441 | .end = 0x04cf01ff, | |
442 | .flags = IORESOURCE_MEM, | |
443 | }, | |
444 | [1] = { | |
445 | .start = 24, | |
446 | .flags = IORESOURCE_IRQ, | |
447 | }, | |
448 | }; | |
449 | ||
450 | static struct platform_device sdhi1_cn7_device = { | |
451 | .name = "sh_mobile_sdhi", | |
452 | .id = 1, /* "sdhi1" clock */ | |
453 | .num_resources = ARRAY_SIZE(sdhi1_cn7_resources), | |
454 | .resource = sdhi1_cn7_resources, | |
455 | .archdata = { | |
456 | .hwblk_id = HWBLK_SDHI1, | |
457 | }, | |
458 | }; | |
459 | ||
026953db | 460 | static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { |
a3e02706 NI |
461 | { |
462 | I2C_BOARD_INFO("pcf8563", 0x51), | |
463 | }, | |
194a1730 GL |
464 | }; |
465 | ||
466 | static struct i2c_board_info ap325rxa_i2c_camera[] = { | |
47131258 KM |
467 | { |
468 | I2C_BOARD_INFO("ov772x", 0x21), | |
194a1730 GL |
469 | }, |
470 | }; | |
471 | ||
472 | static struct ov772x_camera_info ov7725_info = { | |
473 | .buswidth = SOCAM_DATAWIDTH_8, | |
474 | .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP, | |
475 | .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), | |
0f448294 GL |
476 | }; |
477 | ||
478 | static struct soc_camera_link ov7725_link = { | |
479 | .bus_id = 0, | |
480 | .power = ov7725_power, | |
481 | .board_info = &ap325rxa_i2c_camera[0], | |
482 | .i2c_adapter_id = 0, | |
483 | .module_name = "ov772x", | |
484 | .priv = &ov7725_info, | |
194a1730 GL |
485 | }; |
486 | ||
c41debaf GL |
487 | static struct platform_device ap325rxa_camera[] = { |
488 | { | |
489 | .name = "soc-camera-pdrv", | |
490 | .id = 0, | |
491 | .dev = { | |
0f448294 | 492 | .platform_data = &ov7725_link, |
c41debaf GL |
493 | }, |
494 | }, { | |
495 | .name = "soc-camera-pdrv", | |
496 | .id = 1, | |
497 | .dev = { | |
0f448294 | 498 | .platform_data = &camera_link, |
c41debaf | 499 | }, |
47131258 | 500 | }, |
026953db MD |
501 | }; |
502 | ||
194a1730 GL |
503 | static struct platform_device *ap325rxa_devices[] __initdata = { |
504 | &smsc9118_device, | |
505 | &ap325rxa_nor_flash_device, | |
506 | &lcdc_device, | |
507 | &ceu_device, | |
508 | &nand_flash_device, | |
17f81473 | 509 | &sdhi0_cn3_device, |
8b431a7e | 510 | &sdhi1_cn7_device, |
c41debaf GL |
511 | &ap325rxa_camera[0], |
512 | &ap325rxa_camera[1], | |
194a1730 GL |
513 | }; |
514 | ||
86c7d03a MD |
515 | extern char ap325rxa_sdram_enter_start; |
516 | extern char ap325rxa_sdram_enter_end; | |
517 | extern char ap325rxa_sdram_leave_start; | |
518 | extern char ap325rxa_sdram_leave_end; | |
519 | ||
04e917b6 YG |
520 | static int __init ap325rxa_devices_setup(void) |
521 | { | |
86c7d03a MD |
522 | /* register board specific self-refresh code */ |
523 | sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF, | |
524 | &ap325rxa_sdram_enter_start, | |
525 | &ap325rxa_sdram_enter_end, | |
526 | &ap325rxa_sdram_leave_start, | |
527 | &ap325rxa_sdram_leave_end); | |
528 | ||
16587c45 MD |
529 | /* LD3 and LD4 LEDs */ |
530 | gpio_request(GPIO_PTX5, NULL); /* RUN */ | |
531 | gpio_direction_output(GPIO_PTX5, 1); | |
532 | gpio_export(GPIO_PTX5, 0); | |
533 | ||
534 | gpio_request(GPIO_PTX4, NULL); /* INDICATOR */ | |
535 | gpio_direction_output(GPIO_PTX4, 0); | |
536 | gpio_export(GPIO_PTX4, 0); | |
537 | ||
538 | /* SW1 input */ | |
539 | gpio_request(GPIO_PTF7, NULL); /* MODE */ | |
540 | gpio_direction_input(GPIO_PTF7); | |
541 | gpio_export(GPIO_PTF7, 0); | |
542 | ||
543 | /* LCDC */ | |
16587c45 MD |
544 | gpio_request(GPIO_FN_LCDD15, NULL); |
545 | gpio_request(GPIO_FN_LCDD14, NULL); | |
546 | gpio_request(GPIO_FN_LCDD13, NULL); | |
547 | gpio_request(GPIO_FN_LCDD12, NULL); | |
548 | gpio_request(GPIO_FN_LCDD11, NULL); | |
549 | gpio_request(GPIO_FN_LCDD10, NULL); | |
550 | gpio_request(GPIO_FN_LCDD9, NULL); | |
551 | gpio_request(GPIO_FN_LCDD8, NULL); | |
552 | gpio_request(GPIO_FN_LCDD7, NULL); | |
553 | gpio_request(GPIO_FN_LCDD6, NULL); | |
554 | gpio_request(GPIO_FN_LCDD5, NULL); | |
555 | gpio_request(GPIO_FN_LCDD4, NULL); | |
556 | gpio_request(GPIO_FN_LCDD3, NULL); | |
557 | gpio_request(GPIO_FN_LCDD2, NULL); | |
558 | gpio_request(GPIO_FN_LCDD1, NULL); | |
559 | gpio_request(GPIO_FN_LCDD0, NULL); | |
560 | gpio_request(GPIO_FN_LCDLCLK_PTR, NULL); | |
561 | gpio_request(GPIO_FN_LCDDCK, NULL); | |
562 | gpio_request(GPIO_FN_LCDVEPWC, NULL); | |
563 | gpio_request(GPIO_FN_LCDVCPWC, NULL); | |
564 | gpio_request(GPIO_FN_LCDVSYN, NULL); | |
565 | gpio_request(GPIO_FN_LCDHSYN, NULL); | |
566 | gpio_request(GPIO_FN_LCDDISP, NULL); | |
567 | gpio_request(GPIO_FN_LCDDON, NULL); | |
568 | ||
569 | /* LCD backlight */ | |
570 | gpio_request(GPIO_PTS3, NULL); | |
571 | gpio_direction_output(GPIO_PTS3, 1); | |
572 | ||
573 | /* CEU */ | |
16587c45 MD |
574 | gpio_request(GPIO_FN_VIO_CLK2, NULL); |
575 | gpio_request(GPIO_FN_VIO_VD2, NULL); | |
576 | gpio_request(GPIO_FN_VIO_HD2, NULL); | |
577 | gpio_request(GPIO_FN_VIO_FLD, NULL); | |
578 | gpio_request(GPIO_FN_VIO_CKO, NULL); | |
579 | gpio_request(GPIO_FN_VIO_D15, NULL); | |
580 | gpio_request(GPIO_FN_VIO_D14, NULL); | |
581 | gpio_request(GPIO_FN_VIO_D13, NULL); | |
582 | gpio_request(GPIO_FN_VIO_D12, NULL); | |
583 | gpio_request(GPIO_FN_VIO_D11, NULL); | |
584 | gpio_request(GPIO_FN_VIO_D10, NULL); | |
585 | gpio_request(GPIO_FN_VIO_D9, NULL); | |
586 | gpio_request(GPIO_FN_VIO_D8, NULL); | |
587 | ||
588 | gpio_request(GPIO_PTZ7, NULL); | |
589 | gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */ | |
590 | gpio_request(GPIO_PTZ6, NULL); | |
591 | gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */ | |
592 | gpio_request(GPIO_PTZ5, NULL); | |
86746284 | 593 | gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */ |
16587c45 MD |
594 | gpio_request(GPIO_PTZ4, NULL); |
595 | gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */ | |
596 | ||
597 | ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); | |
8b2224dc | 598 | |
908978ac | 599 | /* FLCTL */ |
dd0e20e5 PM |
600 | gpio_request(GPIO_FN_FCE, NULL); |
601 | gpio_request(GPIO_FN_NAF7, NULL); | |
602 | gpio_request(GPIO_FN_NAF6, NULL); | |
603 | gpio_request(GPIO_FN_NAF5, NULL); | |
604 | gpio_request(GPIO_FN_NAF4, NULL); | |
605 | gpio_request(GPIO_FN_NAF3, NULL); | |
606 | gpio_request(GPIO_FN_NAF2, NULL); | |
607 | gpio_request(GPIO_FN_NAF1, NULL); | |
608 | gpio_request(GPIO_FN_NAF0, NULL); | |
609 | gpio_request(GPIO_FN_FCDE, NULL); | |
610 | gpio_request(GPIO_FN_FOE, NULL); | |
611 | gpio_request(GPIO_FN_FSC, NULL); | |
612 | gpio_request(GPIO_FN_FWE, NULL); | |
613 | gpio_request(GPIO_FN_FRB, NULL); | |
908978ac YS |
614 | |
615 | ctrl_outw(0, PORT_HIZCRC); | |
616 | ctrl_outw(0xFFFF, PORT_DRVCRA); | |
617 | ctrl_outw(0xFFFF, PORT_DRVCRB); | |
618 | ||
8b2224dc | 619 | platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); |
6968980a | 620 | |
8b431a7e | 621 | /* SDHI0 - CN3 - SD CARD */ |
17f81473 MD |
622 | gpio_request(GPIO_FN_SDHI0CD_PTD, NULL); |
623 | gpio_request(GPIO_FN_SDHI0WP_PTD, NULL); | |
624 | gpio_request(GPIO_FN_SDHI0D3_PTD, NULL); | |
625 | gpio_request(GPIO_FN_SDHI0D2_PTD, NULL); | |
626 | gpio_request(GPIO_FN_SDHI0D1_PTD, NULL); | |
627 | gpio_request(GPIO_FN_SDHI0D0_PTD, NULL); | |
628 | gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL); | |
629 | gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL); | |
630 | ||
8b431a7e MD |
631 | /* SDHI1 - CN7 - MICRO SD CARD */ |
632 | gpio_request(GPIO_FN_SDHI1CD, NULL); | |
633 | gpio_request(GPIO_FN_SDHI1D3, NULL); | |
634 | gpio_request(GPIO_FN_SDHI1D2, NULL); | |
635 | gpio_request(GPIO_FN_SDHI1D1, NULL); | |
636 | gpio_request(GPIO_FN_SDHI1D0, NULL); | |
637 | gpio_request(GPIO_FN_SDHI1CMD, NULL); | |
638 | gpio_request(GPIO_FN_SDHI1CLK, NULL); | |
639 | ||
026953db MD |
640 | i2c_register_board_info(0, ap325rxa_i2c_devices, |
641 | ARRAY_SIZE(ap325rxa_i2c_devices)); | |
908978ac | 642 | |
04e917b6 YG |
643 | return platform_add_devices(ap325rxa_devices, |
644 | ARRAY_SIZE(ap325rxa_devices)); | |
645 | } | |
dbefd606 | 646 | arch_initcall(ap325rxa_devices_setup); |
04e917b6 | 647 | |
c01641b4 MD |
648 | /* Return the board specific boot mode pin configuration */ |
649 | static int ap325rxa_mode_pins(void) | |
650 | { | |
651 | /* MD0=0, MD1=0, MD2=0: Clock Mode 0 | |
652 | * MD3=0: 16-bit Area0 Bus Width | |
653 | * MD5=1: Little Endian | |
654 | * TSTMD=1, MD8=1: Test Mode Disabled | |
655 | */ | |
656 | return MODE_PIN5 | MODE_PIN8; | |
657 | } | |
658 | ||
04e917b6 YG |
659 | static struct sh_machine_vector mv_ap325rxa __initmv = { |
660 | .mv_name = "AP-325RXA", | |
c01641b4 | 661 | .mv_mode_pins = ap325rxa_mode_pins, |
04e917b6 | 662 | }; |